{"id":96958,"date":"2026-08-28T20:33:11","date_gmt":"2026-08-28T12:33:11","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/96958.html"},"modified":"2026-08-28T20:33:11","modified_gmt":"2026-08-28T12:33:11","slug":"intel-tcc%e6%a8%a1%e5%bc%8f%e4%b8%8btsc%e4%b8%8eart%e7%a1%ae%e5%ae%9a%e6%80%a7%e7%ba%bf%e6%80%a7%e5%85%b3%e7%b3%bb%e8%ae%be%e8%ae%a1%e5%8e%9f%e7%90%86","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/96958.html","title":{"rendered":"Intel TCC\u6a21\u5f0f\u4e0bTSC\u4e0eART\u786e\u5b9a\u6027\u7ebf\u6027\u5173\u7cfb\u8bbe\u8ba1\u539f\u7406"},"content":{"rendered":"<h2>Intel TCC \u6a21\u5f0f\u4e0b TSC \u4e0e ART \u7684\u786e\u5b9a\u6027\u7ebf\u6027\u5173\u7cfb\u8bbe\u8ba1<\/h2>\n<h3>1. \u6982\u8ff0<\/h3>\n<p>\u5728\u652f\u6301 Intel TCC&#xff08;Time-Coordinated Computing&#xff0c;\u65f6\u95f4\u534f\u8c03\u8ba1\u7b97&#xff09;\u6a21\u5f0f\u7684\u5904\u7406\u5668\u4e2d&#xff0c;TSC&#xff08;Time Stamp Counter&#xff09;\u4e0e ART&#xff08;Always Running Timer&#xff09;\u4e4b\u95f4\u7684\u786e\u5b9a\u6027\u7ebf\u6027\u5173\u7cfb\u662f\u901a\u8fc7\u786c\u4ef6\u7ea7\u7684\u4e0d\u53d8\u65f6\u949f\u67b6\u6784\u548c\u6807\u51c6\u5316\u7684\u9891\u7387\u6bd4\u4f8b\u56e0\u5b50\u5171\u540c\u4fdd\u8bc1\u7684\u3002<\/p>\n<p>\u8fd9\u4e00\u8bbe\u8ba1\u4f7f\u5f97\u8f6f\u4ef6\u80fd\u591f\u4ee5\u4e9a\u5fae\u79d2\u7ea7\u7cbe\u5ea6\u8ba1\u7b97\u5e76\u5173\u8054\u591a\u4e2a\u72ec\u7acb\u5b50\u7cfb\u7edf\u7684\u672c\u5730\u65f6\u949f&#xff0c;\u662f TCC \u5b9e\u73b0\u9ad8\u7cbe\u5ea6\u65f6\u95f4\u534f\u8c03\u7684\u786c\u4ef6\u57fa\u7840\u3002<\/p>\n<hr \/>\n<h3>2. ART&#xff08;Always Running Timer&#xff09;\u4f5c\u4e3a\u4e0d\u53d8\u65f6\u57fa<\/h3>\n<h4>2.1 ART \u7684\u5b9a\u4e49\u4e0e\u7279\u6027<\/h4>\n<p>ART \u662f\u5904\u7406\u5668\u5185\u90e8\u7684\u4e00\u5757\u4e13\u7528\u4e0d\u53d8\u8ba1\u65f6\u786c\u4ef6&#xff0c;\u4ee5\u56fa\u5b9a\u7684\u6838\u5fc3\u6676\u4f53\u65f6\u949f\u9891\u7387\u8fd0\u884c&#xff08;\u901a\u5e38\u4e3a 19.2 MHz&#xff09;\u3002<\/p>\n<p>ART \u7684\u5173\u952e\u7279\u6027&#xff1a;<\/p>\n<ul>\n<li>\u4e0d\u53d7 CPU \u9891\u7387\u3001P-State\/C-State\/T-State \u53d8\u5316\u5f71\u54cd&#xff0c;\u59cb\u7ec8\u4fdd\u6301\u6052\u5b9a\u901f\u7387<\/li>\n<li>\u4f5c\u4e3a\u6574\u4e2a SoC \u7684\u5168\u5c40\u65f6\u95f4\u53c2\u8003\u57fa\u51c6<\/li>\n<li>\u6240\u6709\u9700\u8981\u65f6\u95f4\u540c\u6b65\u7684\u5b50\u7cfb\u7edf&#xff08;TSC\u3001TSN \u4ee5\u592a\u7f51\u3001PCIe PTM\u3001Time-Aware GPIO\u3001High Definition Audio \u7b49&#xff09;\u90fd\u4ee5\u5176\u4e3a\u951a\u70b9<\/li>\n<\/ul>\n<h4>2.2 ART \u5728 SoC \u4e2d\u7684\u89d2\u8272<\/h4>\n<p>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510<br \/>\n\u2502                    SoC \u5168\u5c40\u65f6\u95f4\u67b6\u6784                           \u2502<br \/>\n\u2502                                                             \u2502<br \/>\n\u2502    \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510                                              \u2502<br \/>\n\u2502    \u2502   ART   \u2502  \u2190 19.2 MHz \u6838\u5fc3\u6676\u4f53\u65f6\u949f&#xff08;\u4e0d\u53d8\u65f6\u57fa&#xff09;          \u2502<br \/>\n\u2502    \u2502(19.2MHz)\u2502                                              \u2502<br \/>\n\u2502    \u2514\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2518                                              \u2502<br \/>\n\u2502         \u2502                                                   \u2502<br \/>\n\u2502    \u250c\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510      \u2502<br \/>\n\u2502    \u25bc         \u25bc            \u25bc            \u25bc            \u25bc      \u2502<br \/>\n\u2502 \u250c\u2500\u2500\u2500\u2500\u2500\u2510  \u250c\u2500\u2500\u2500\u2500\u2500\u2510     \u250c\u2500\u2500\u2500\u2500\u2500\u2510     \u250c\u2500\u2500\u2500\u2500\u2500\u2510     \u250c\u2500\u2500\u2500\u2500\u2500\u2510     \u2502<br \/>\n\u2502 \u2502 TSC \u2502  \u2502 TSN \u2502     \u2502PCIe \u2502     \u2502GPIO \u2502     \u2502Audio\u2502     \u2502<br \/>\n\u2502 \u2502 CPU \u2502  \u2502Eth  \u2502     \u2502PTM  \u2502     \u2502T-A  \u2502     \u2502\/ISH \u2502     \u2502<br \/>\n\u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2518  \u2514\u2500\u2500\u2500\u2500\u2500\u2518     \u2514\u2500\u2500\u2500\u2500\u2500\u2518     \u2514\u2500\u2500\u2500\u2500\u2500\u2518     \u2514\u2500\u2500\u2500\u2500\u2500\u2518     \u2502<br \/>\n\u2502                                                             \u2502<br \/>\n\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/p>\n<hr \/>\n<h3>3. Invariant TSC \u76f4\u63a5\u6d3e\u751f\u81ea ART<\/h3>\n<h4>3.1 Invariant TSC \u7684\u5b9a\u4e49<\/h4>\n<p>Invariant TSC \u5e76\u975e\u72ec\u7acb\u632f\u8361&#xff0c;\u800c\u662f\u57fa\u4e8e ART \u786c\u4ef6\u6d3e\u751f\u51fa\u6765\u7684\u3002Intel \u901a\u8fc7\u786c\u4ef6\u8bbe\u8ba1\u786e\u4fdd TSC \u5728\u6240\u6709 ACPI \u7535\u6e90\u72b6\u6001\u4e0b&#xff08;P-\/C-\/T-States&#xff09;\u4fdd\u6301\u6052\u5b9a\u901f\u7387\u8fd0\u884c\u3002<\/p>\n<p>\u5173\u952e\u4fdd\u8bc1&#xff1a;Invariant TSC \u5728\u6240\u6709 ACPI P-\u3001C- \u548c T-States \u4e0b\u4ee5\u6052\u5b9a\u901f\u7387\u8fd0\u884c\u3002<\/p>\n<h4>3.2 \u4e0e Legacy TSC \u7684\u533a\u522b<\/h4>\n<table>\n<tr>\u7279\u6027Legacy TSCInvariant TSC<\/tr>\n<tbody>\n<tr>\n<td>\u65f6\u949f\u6e90<\/td>\n<td>\u72ec\u7acb\u632f\u8361\u5668<\/td>\n<td>\u4ece ART \u6d3e\u751f<\/td>\n<\/tr>\n<tr>\n<td>\u9891\u7387\u7a33\u5b9a\u6027<\/td>\n<td>\u968f CPU \u9891\u7387\u53d8\u5316<\/td>\n<td>\u6052\u5b9a\u4e0d\u53d8<\/td>\n<\/tr>\n<tr>\n<td>\u8de8\u7535\u6e90\u72b6\u6001<\/td>\n<td>\u53ef\u80fd\u53d8\u5316\/\u505c\u6b62<\/td>\n<td>\u59cb\u7ec8\u4fdd\u6301<\/td>\n<\/tr>\n<tr>\n<td>\u8de8\u6838\u5fc3\u4e00\u81f4\u6027<\/td>\n<td>\u4e0d\u4fdd\u8bc1<\/td>\n<td>\u4fdd\u8bc1\u540c\u6b65<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<hr \/>\n<h3>4. CPUID Leaf 15H \u5b9a\u4e49\u786e\u5b9a\u6027\u9891\u7387\u6bd4<\/h3>\n<h4>4.1 \u6bd4\u4f8b\u56e0\u5b50\u5bc4\u5b58\u5668<\/h4>\n<p>Intel \u901a\u8fc7 CPUID Leaf 15H \u5411\u8f6f\u4ef6\u66b4\u9732 ART \u4e0e TSC \u4e4b\u95f4\u7684\u7cbe\u786e\u9891\u7387\u5173\u7cfb&#xff0c;\u4ece\u800c\u5efa\u7acb\u53ef\u8ba1\u7b97\u7684\u7ebf\u6027\u6620\u5c04&#xff1a;<\/p>\n<p>TSC_Value &#061; (ART_Value \u00d7 CPUID.15H:EBX[31:0]) \/ CPUID.15H:EAX[31:0] &#043; K<\/p>\n<p>\u5176\u4e2d&#xff1a;<\/p>\n<table>\n<tr>\u53c2\u6570\u5bc4\u5b58\u5668\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u5206\u5b50<\/td>\n<td>CPUID.15H:EBX[31:0]<\/td>\n<td>TSC \u9891\u7387\u76f8\u5bf9\u4e8e ART \u7684\u500d\u6570<\/td>\n<\/tr>\n<tr>\n<td>\u5206\u6bcd<\/td>\n<td>CPUID.15H:EAX[31:0]<\/td>\n<td>\u6bd4\u4f8b\u56e0\u5b50\u7684\u5206\u6bcd<\/td>\n<\/tr>\n<tr>\n<td>\u6bd4\u4f8b<\/td>\n<td>EBX \/ EAX<\/td>\n<td>\u786c\u4ef6\u56fa\u5b9a\u7684\u6574\u6570\u9891\u7387\u6bd4<\/td>\n<\/tr>\n<tr>\n<td>\u504f\u79fb<\/td>\n<td>K<\/td>\n<td>\u53ef\u7531\u7279\u6743\u4ee3\u7406\u8c03\u6574\u7684\u504f\u79fb\u5e38\u91cf<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>4.2 \u504f\u79fb\u91cf K \u7684\u4f5c\u7528<\/h4>\n<p>\u504f\u79fb\u5e38\u91cf K \u53ef\u7531\u7279\u6743\u4ee3\u7406&#xff08;\u5982 BIOS\u3001\u64cd\u4f5c\u7cfb\u7edf\u6216 VMM&#xff09;\u8c03\u6574&#xff0c;\u7528\u4e8e&#xff1a;<\/p>\n<ul>\n<li>\u8de8\u6838\u5fc3\u65f6\u949f\u5bf9\u9f50<\/li>\n<li>\u8de8\u7cfb\u7edf\u65f6\u949f\u540c\u6b65<\/li>\n<li>\u865a\u62df\u5316\u573a\u666f\u4e0b\u7684\u65f6\u95f4\u865a\u62df\u5316<\/li>\n<\/ul>\n<h4>4.3 \u7ebf\u6027\u5173\u7cfb\u7684\u6570\u5b66\u8868\u8fbe<\/h4>\n<p>\u7531\u4e8e\u6bd4\u4f8b\u56e0\u5b50 EBX\/EAX \u662f\u786c\u4ef6\u56fa\u5316\u7684\u5e38\u6570&#xff0c;\u56e0\u6b64 TSC \u4e0e ART \u4e4b\u95f4\u6ee1\u8db3\u4e25\u683c\u7684\u7ebf\u6027\u5173\u7cfb&#xff1a;<\/p>\n<p>\u0394TSC &#061; (EBX \/ EAX) \u00d7 \u0394ART<\/p>\n<p>\u8fd9\u610f\u5473\u7740&#xff1a;<\/p>\n<ul>\n<li>\u4efb\u610f\u4e24\u4e2a ART \u65f6\u523b\u4e4b\u95f4\u7684 TSC \u5dee\u503c\u662f\u5b8c\u5168\u786e\u5b9a\u7684<\/li>\n<li>\u8f6f\u4ef6\u53ef\u4ee5\u901a\u8fc7\u8bfb\u53d6 ART \u548c TSC&#xff0c;\u5229\u7528\u4e0a\u8ff0\u516c\u5f0f\u8fdb\u884c\u53cc\u5411\u8f6c\u6362<\/li>\n<li>\u4e0d\u5b58\u5728\u975e\u7ebf\u6027\u6f02\u79fb\u6216\u7d2f\u79ef\u8bef\u5dee<\/li>\n<\/ul>\n<hr \/>\n<h3>5. TCC \u6a21\u5f0f\u4e0b\u7684\u8de8\u5b50\u7cfb\u7edf\u540c\u6b65<\/h3>\n<h4>5.1 \u65f6\u95f4\u534f\u8c03\u8ba1\u7b97\u7684\u9700\u6c42<\/h4>\n<p>TCC \u573a\u666f\u8981\u6c42\u591a\u4e2a\u72ec\u7acb\u5b50\u7cfb\u7edf\u80fd\u591f\u4ee5\u4e9a\u5fae\u79d2\u7ea7\u7cbe\u5ea6\u8fdb\u884c\u65f6\u95f4\u5173\u8054\u548c\u540c\u6b65\u3002\u786e\u5b9a\u6027\u7ebf\u6027\u5173\u7cfb\u4f7f\u5f97\u8fd9\u4e00\u70b9\u6210\u4e3a\u53ef\u80fd\u3002<\/p>\n<h4>5.2 \u5404\u5b50\u7cfb\u7edf\u4e0e ART \u7684\u5173\u7cfb<\/h4>\n<table>\n<tr>\u5b50\u7cfb\u7edf\u4e0e ART \u7684\u5173\u7cfb\u5e94\u7528\u573a\u666f<\/tr>\n<tbody>\n<tr>\n<td>CPU TSC<\/td>\n<td>\u901a\u8fc7 CPUID.15H \u6bd4\u4f8b\u76f4\u63a5\u6d3e\u751f<\/td>\n<td>\u8f6f\u4ef6\u65f6\u95f4\u6233\u3001\u6027\u80fd\u5206\u6790<\/td>\n<\/tr>\n<tr>\n<td>TSN Ethernet<\/td>\n<td>\u4ee5 ART \u4e3a\u57fa\u51c6\u8fdb\u884c\u786c\u4ef6\u65f6\u95f4\u6233<\/td>\n<td>IEEE 802.1AS \u65f6\u95f4\u654f\u611f\u7f51\u7edc<\/td>\n<\/tr>\n<tr>\n<td>PCIe PTM<\/td>\n<td>\u672c\u5730\u65f6\u949f\u901a\u8fc7 ART \u5bf9\u9f50<\/td>\n<td>\u7cbe\u786e\u65f6\u95f4\u6d4b\u91cf&#xff08;Precision Time Measurement&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>Time-Aware GPIO<\/td>\n<td>\u8109\u51b2\u89e6\u53d1\u4e0e ART \u540c\u6b65<\/td>\n<td>\u7cbe\u786e GPIO \u89e6\u53d1\/\u6355\u83b7<\/td>\n<\/tr>\n<tr>\n<td>High Definition Audio<\/td>\n<td>\u91c7\u6837\u65f6\u949f\u53c2\u7167 ART<\/td>\n<td>\u97f3\u9891\u540c\u6b65<\/td>\n<\/tr>\n<tr>\n<td>ISH \/ CAN<\/td>\n<td>\u5404\u81ea\u672c\u5730\u65f6\u949f\u5747\u53c2\u7167 ART<\/td>\n<td>\u4f20\u611f\u5668\/\u5de5\u4e1a\u603b\u7ebf\u540c\u6b65<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>5.3 \u540c\u6b65\u7cbe\u5ea6<\/h4>\n<p>\u57fa\u4e8e ART \u7684\u7edf\u4e00\u65f6\u57fa&#xff0c;\u5404\u5b50\u7cfb\u7edf\u53ef\u4ee5\u5b9e\u73b0&#xff1a;<\/p>\n<ul>\n<li>\u6df1\u5ea6\u4e9a\u5fae\u79d2\u7ea7&#xff08;deep sub-microsecond&#xff09;\u65f6\u95f4\u5173\u8054<\/li>\n<li>\u8de8\u5b50\u7cfb\u7edf\u4e8b\u4ef6\u7684\u65f6\u95f4\u6233\u5bf9\u9f50<\/li>\n<li>\u786e\u5b9a\u6027\u5ef6\u8fdf\u6d4b\u91cf<\/li>\n<\/ul>\n<hr \/>\n<h3>6. \u590d\u4f4d\u540c\u6b65\u4fdd\u8bc1\u4e00\u81f4\u6027<\/h3>\n<h4>6.1 \u540c\u6b65\u590d\u4f4d\u673a\u5236<\/h4>\n<p>\u5f53 ART \u786c\u4ef6\u590d\u4f4d\u65f6&#xff0c;Invariant TSC \u548c\u504f\u79fb\u91cf K \u4f1a\u540c\u6b65\u590d\u4f4d&#xff0c;\u786e\u4fdd\u4e8c\u8005\u5728\u6574\u4e2a\u751f\u547d\u5468\u671f\u5185\u59cb\u7ec8\u4fdd\u6301\u4e00\u81f4\u7684\u7ebf\u6027\u5173\u7cfb&#xff0c;\u4e0d\u4f1a\u51fa\u73b0\u6f02\u79fb\u6216\u5931\u6b65\u3002<\/p>\n<p>\u5173\u952e\u4fdd\u8bc1&#xff1a;ART \u590d\u4f4d \u2192 TSC \u590d\u4f4d &#043; K \u590d\u4f4d&#xff0c;\u4e09\u8005\u4fdd\u6301\u539f\u5b50\u6027\u540c\u6b65\u3002<\/p>\n<h4>6.2 \u751f\u547d\u5468\u671f\u4e00\u81f4\u6027<\/h4>\n<p>\u65f6\u95f4\u70b9:    \u590d\u4f4d\u65f6\u523b                    \u8fd0\u884c\u671f\u95f4<br \/>\n           \u2502                           \u2502<br \/>\nART:       0 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2192 \u6301\u7eed\u8ba1\u6570<br \/>\n           \u2502                           \u2502<br \/>\nTSC:       K\u2080 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2192 \u7ebf\u6027\u589e\u957f<br \/>\n           \u2502                           \u2502<br \/>\n\u5173\u7cfb:      TSC &#061; (EBX\/EAX) \u00d7 ART &#043; K\u2080   \u59cb\u7ec8\u4fdd\u6301<br \/>\n           \u2502                           \u2502<br \/>\n           \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<br \/>\n                    \u786e\u5b9a\u6027\u7ebf\u6027\u5173\u7cfb<\/p>\n<hr \/>\n<h3>7. \u8bbe\u8ba1\u603b\u7ed3<\/h3>\n<table>\n<tr>\u8bbe\u8ba1\u8981\u7d20\u4f5c\u7528\u5173\u952e\u5c5e\u6027<\/tr>\n<tbody>\n<tr>\n<td>ART&#xff08;19.2 MHz \u6676\u4f53\u65f6\u949f&#xff09;<\/td>\n<td>\u63d0\u4f9b\u4e0d\u53d7\u7535\u6e90\u7ba1\u7406\u5f71\u54cd\u7684\u5168\u5c40\u4e0d\u53d8\u65f6\u57fa<\/td>\n<td>\u6052\u5b9a\u3001\u72ec\u7acb\u3001\u5168\u5c40\u53ef\u89c1<\/td>\n<\/tr>\n<tr>\n<td>Invariant TSC<\/td>\n<td>\u4ee5\u56fa\u5b9a\u6bd4\u4f8b\u4ece ART \u6d3e\u751f&#xff0c;\u4fdd\u8bc1\u8de8 P\/C\/T-State \u6052\u5b9a<\/td>\n<td>\u9ad8\u6027\u80fd\u3001\u4f4e\u5ef6\u8fdf\u3001\u8f6f\u4ef6\u53ef\u8bfb<\/td>\n<\/tr>\n<tr>\n<td>CPUID.15H \u6bd4\u4f8b\u56e0\u5b50<\/td>\n<td>\u786c\u4ef6\u56fa\u5316\u3001\u8f6f\u4ef6\u53ef\u8bfb\u7684\u786e\u5b9a\u6027\u9891\u7387\u6bd4<\/td>\n<td>EBX\/EAX \u4e3a\u56fa\u5b9a\u6574\u6570\u6bd4<\/td>\n<\/tr>\n<tr>\n<td>\u504f\u79fb\u91cf K<\/td>\n<td>\u652f\u6301\u7279\u6743\u7ea7\u5fae\u8c03&#xff0c;\u5b9e\u73b0\u8de8\u6838\/\u8de8\u7cfb\u7edf\u5bf9\u9f50<\/td>\n<td>\u53ef\u914d\u7f6e\u3001\u590d\u4f4d\u540c\u6b65<\/td>\n<\/tr>\n<tr>\n<td>\u540c\u6b65\u590d\u4f4d<\/td>\n<td>ART \u590d\u4f4d\u65f6 TSC \u4e0e K \u540c\u6b65\u590d\u4f4d&#xff0c;\u9632\u6b62\u6f02\u79fb<\/td>\n<td>\u539f\u5b50\u6027\u3001\u4e00\u81f4\u6027<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>7.1 \u8bbe\u8ba1\u672c\u8d28<\/h4>\n<p>\u8fd9\u5957\u8bbe\u8ba1\u7684\u672c\u8d28\u662f\u5c06**\u65f6\u95f4\u57fa\u51c6&#xff08;ART&#xff09;\u4e0e\u8f6f\u4ef6\u53ef\u89c1\u8ba1\u6570\u5668&#xff08;TSC&#xff09;**\u89e3\u8026&#xff1a;<\/p>\n<ul>\n<li>ART \u8d1f\u8d23\u63d0\u4f9b\u7edd\u5bf9\u7a33\u5b9a\u7684\u7269\u7406\u65f6\u57fa<\/li>\n<li>TSC \u8d1f\u8d23\u63d0\u4f9b\u9ad8\u6027\u80fd\u3001\u4f4e\u5ef6\u8fdf\u7684\u8f6f\u4ef6\u8bfb\u53d6\u63a5\u53e3<\/li>\n<li>CPUID.15H \u6bd4\u4f8b\u56e0\u5b50 \u786e\u4fdd\u4e8c\u8005\u4e4b\u95f4\u7684\u6620\u5c04\u662f\u5b8c\u5168\u786e\u5b9a\u3001\u53ef\u9884\u6d4b\u4e14\u7ebf\u6027\u7684<\/li>\n<\/ul>\n<h4>7.2 TCC \u5e94\u7528\u4ef7\u503c<\/h4>\n<p>\u8fd9\u4e00\u786c\u4ef6\u67b6\u6784\u4f7f\u5f97 TCC \u80fd\u591f&#xff1a;<\/p>\n<li>\u5728\u5355\u82af\u7247\u5185\u5b9e\u73b0\u591a\u5b50\u7cfb\u7edf\u7684\u65f6\u95f4\u4e00\u81f4\u6027<\/li>\n<li>\u652f\u6301\u4e9a\u5fae\u79d2\u7ea7\u7684\u786e\u5b9a\u6027\u65f6\u95f4\u534f\u8c03<\/li>\n<li>\u4e3a\u65f6\u95f4\u654f\u611f\u5e94\u7528&#xff08;TSN\u3001\u5de5\u4e1a\u63a7\u5236\u3001\u97f3\u89c6\u9891\u540c\u6b65\u7b49&#xff09;\u63d0\u4f9b\u786c\u4ef6\u7ea7\u65f6\u95f4\u4fdd\u969c<\/li>\n<hr \/>\n<h3>8. \u53c2\u8003\u4fe1\u606f<\/h3>\n<ul>\n<li>Intel\u00ae 64 and IA-32 Architectures Software Developer\u2019s Manual, Volume 3A: System Programming Guide, Part 1<\/li>\n<li>Intel\u00ae Time-Coordinated Computing (TCC) Technology Documentation<\/li>\n<li>CPUID Leaf 15H \u2014 Time Stamp Counter and Nominal Core Crystal Clock Information<\/li>\n<\/ul>\n<hr \/>\n","protected":false},"excerpt":{"rendered":"<p>Intel TCC \u6a21\u5f0f\u4e0b TSC \u4e0e ART \u7684\u786e\u5b9a\u6027\u7ebf\u6027\u5173\u7cfb\u8bbe\u8ba1<br \/>\n1. \u6982\u8ff0<br \/>\n\u5728\u652f\u6301 Intel TCC&#xff08;Time-Coordinated Computing&#xff0c;\u65f6\u95f4\u534f\u8c03\u8ba1\u7b97&#xff09;\u6a21\u5f0f\u7684\u5904\u7406\u5668\u4e2d&#xff0c;TSC&#xff08;Time Stamp Counter&#xff09;\u4e0e ART&#xff08;Always Running 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