{"id":88588,"date":"2026-08-01T13:16:57","date_gmt":"2026-08-01T05:16:57","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/88588.html"},"modified":"2026-08-01T13:16:57","modified_gmt":"2026-08-01T05:16:57","slug":"arm%e6%9c%8d%e5%8a%a1%e5%99%a8cpu%e4%b8%8ex86%e7%9a%84%e6%9e%b6%e6%9e%84%e5%b7%ae%e5%bc%82%e5%8f%8aai%e6%8e%a8%e7%90%86%e9%80%82%e9%85%8d","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/88588.html","title":{"rendered":"ARM\u670d\u52a1\u5668CPU\u4e0ex86\u7684\u67b6\u6784\u5dee\u5f02\u53caAI\u63a8\u7406\u9002\u914d"},"content":{"rendered":"

\u5f53\u6211\u4eec\u628a\u4e00\u4e2a\u5728 x86 \u670d\u52a1\u5668\u4e0a\u8fd0\u884c\u826f\u597d\u7684\u5927\u6a21\u578b\u63a8\u7406\u670d\u52a1\u8fc1\u79fb\u5230 ARM \u670d\u52a1\u5668\u65f6，\u6027\u80fd\u8868\u73b0\u5f80\u5f80\u51fa\u4e4e\u610f\u6599\u2014\u2014\u6709\u65f6\u66f4\u597d，\u6709\u65f6\u66f4\u5dee，\u6709\u65f6\u751a\u81f3\u76f4\u63a5\u5d29\u6e83\u3002\u80cc\u540e\u7684\u539f\u56e0，\u85cf\u5728\u4e24\u79cd\u67b6\u6784\u622a\u7136\u4e0d\u540c\u7684\u8bbe\u8ba1\u54f2\u5b66\u91cc\u3002<\/p>\n

\u672c\u7bc7\u7cfb\u7edf\u68b3\u7406 ARM \u670d\u52a1\u5668 CPU（\u4ee5\u9ad8\u6027\u80fd\u670d\u52a1\u5668\u7ea7 ARM \u5904\u7406\u5668\u4e3a\u4ee3\u8868）\u4e0e x86（\u4ee5 Intel\/AMD \u4e3a\u4ee3\u8868）\u7684\u6838\u5fc3\u67b6\u6784\u5dee\u5f02，\u4ee5\u53ca\u5728\u5927\u6a21\u578b\u63a8\u7406\u573a\u666f\u4e0b\u7684\u9002\u914d\u8981\u70b9\u3002<\/p>\n

\n

1 \u6307\u4ee4\u96c6\u67b6\u6784\u5dee\u5f02<\/h3>\n

1.1 RISC vs CISC<\/h4>\n\n\u7ef4\u5ea6ARM（RISC）x86（CISC）<\/tr>\n\n\n\n\n\n
\u6307\u4ee4\u590d\u6742\u5ea6<\/td>\n\u5b9a\u957f\u6307\u4ee4，\u903b\u8f91\u7b80\u5355<\/td>\n\u53d8\u957f\u6307\u4ee4，\u5355\u6761\u53ef\u5b8c\u6210\u590d\u6742\u64cd\u4f5c<\/td>\n<\/tr>\n
\u5bc4\u5b58\u5668\u6570\u91cf<\/td>\n31\u4e2a\u901a\u7528\u5bc4\u5b58\u5668<\/td>\n16\u4e2a\u901a\u7528\u5bc4\u5b58\u5668（64\u4f4d\u6a21\u5f0f）<\/td>\n<\/tr>\n
\u5185\u5b58\u8bbf\u95ee<\/td>\nLoad\/Store \u67b6\u6784，\u53ea\u6709\u4e13\u7528\u6307\u4ee4\u8bbf\u95ee\u5185\u5b58<\/td>\n\u591a\u6570\u6307\u4ee4\u53ef\u76f4\u63a5\u64cd\u4f5c\u5185\u5b58<\/td>\n<\/tr>\n
\u529f\u8017\u7279\u6027<\/td>\n\u4f4e\u529f\u8017\u8bbe\u8ba1\u539f\u751f\u652f\u6301<\/td>\n\u9ad8\u6027\u80fd\u4f18\u5148，\u529f\u8017\u76f8\u5bf9\u8f83\u9ad8<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

RISC \u7684\u7b80\u6d01\u6027\u5e26\u6765\u4e86\u66f4\u9ad8\u7684\u6d41\u6c34\u7ebf\u6548\u7387\u2014\u2014\u6bcf\u4e2a\u65f6\u949f\u5468\u671f\u80fd\u7a33\u5b9a\u5b8c\u6210\u66f4\u591a\u6307\u4ee4，\u8fd9\u5bf9\u63a8\u7406\u573a\u666f\u4e2d\u5927\u91cf\u91cd\u590d\u7684\u77e9\u9635\u4e58\u6cd5\u64cd\u4f5c\u975e\u5e38\u53cb\u597d\u3002<\/p>\n

1.2 \u5411\u91cf\u6307\u4ee4\u96c6<\/h4>\n

ARM \u670d\u52a1\u5668\u4f7f\u7528 SVE（Scalable Vector Extension） \u6216 SVE2，x86 \u4f7f\u7528 AVX-512\u3002\u4e8c\u8005\u6700\u5927\u7684\u5dee\u5f02\u5728\u4e8e\u5411\u91cf\u5bbd\u5ea6：<\/p>\n

    \n
  • AVX-512：\u56fa\u5b9a 512-bit \u5bbd\u5ea6（\u53ef\u5904\u7406 16 \u4e2a float32）<\/li>\n
  • SVE：\u5411\u91cf\u5bbd\u5ea6\u53ef\u53d8（128-bit \u5230 2048-bit），\u7531\u786c\u4ef6\u5b9e\u73b0\u51b3\u5b9a，\u8f6f\u4ef6\u7f16\u5199\u65f6\u65e0\u9700\u611f\u77e5\u5177\u4f53\u5bbd\u5ea6<\/li>\n<\/ul>\n

    SVE \u7684"\u4e0e\u5411\u91cf\u957f\u5ea6\u65e0\u5173"（VLA，Vector Length Agnostic）\u7f16\u7a0b\u6a21\u578b，\u4f7f\u5f97\u540c\u4e00\u4efd\u4ee3\u7801\u53ef\u4ee5\u5728\u4e0d\u540c SVE \u5bbd\u5ea6\u7684\u786c\u4ef6\u4e0a\u81ea\u52a8\u83b7\u5f97\u6700\u4f18\u6027\u80fd，\u65e0\u9700\u4e3a\u4e0d\u540c CPU \u7ef4\u62a4\u591a\u4e2a\u4ee3\u7801\u8def\u5f84\u3002<\/p>\n

    \n

    2 \u5185\u5b58\u5b50\u7cfb\u7edf\u5dee\u5f02<\/h3>\n

    2.1 \u7f13\u5b58\u5c42\u6b21\u7ed3\u6784<\/h4>\n

    \u5927\u6a21\u578b\u63a8\u7406\u662f\u5185\u5b58\u5e26\u5bbd\u5bc6\u96c6\u578b\u4efb\u52a1，\u7f13\u5b58\u5c42\u6b21\u5bf9\u6027\u80fd\u5f71\u54cd\u663e\u8457\u3002<\/p>\n

    ARM \u670d\u52a1\u5668 CPU（\u4ee5\u9ad8\u7aef\u578b\u53f7\u4e3a\u4f8b）\u901a\u5e38\u5177\u5907：<\/p>\n

      \n
    • \u5927\u5bb9\u91cf L3 \u7f13\u5b58（\u5f80\u5f80\u5728 64MB-256MB \u91cf\u7ea7）<\/li>\n
    • \u591a CCX（\u6838\u5fc3\u590d\u5408\u4f53）\u8bbe\u8ba1，\u6bcf\u4e2a CCX \u5171\u4eab\u4e00\u90e8\u5206 L3<\/li>\n
    • \u5bf9 NUMA（Non-Uniform Memory Access）\u67b6\u6784\u7684\u663e\u5f0f\u652f\u6301<\/li>\n<\/ul>\n

      \u63a8\u7406\u65f6，\u6a21\u578b\u6743\u91cd\u52a0\u8f7d\u7684\u8bbf\u95ee\u6a21\u5f0f\u5448\u73b0\u9ad8\u5ea6\u5c40\u90e8\u6027，\u5927 L3 \u7f13\u5b58\u53ef\u4ee5\u663e\u8457\u964d\u4f4e\u6743\u91cd\u7684\u91cd\u590d\u52a0\u8f7d\u5f00\u9500\u3002<\/p>\n

      2.2 \u5185\u5b58\u5e26\u5bbd<\/h4>\n

      ARM \u670d\u52a1\u5668\u5904\u7406\u5668\u901a\u5e38\u652f\u6301\u591a\u901a\u9053 DDR5 \u5185\u5b58，\u805a\u5408\u5185\u5b58\u5e26\u5bbd\u4e0e\u540c\u6863\u6b21 x86 \u5904\u7406\u5668\u76f8\u5f53\u3002\u5728\u8fd0\u884c 7B \u53c2\u6570\u91cf\u7ea7（FP16 \u7ea6 14GB）\u7684\u6a21\u578b\u65f6，\u6a21\u578b\u6743\u91cd\u53ef\u4ee5\u5b8c\u6574\u9a7b\u7559\u5728\u5185\u5b58\u4e2d，\u63a8\u7406\u5ef6\u8fdf\u4e3b\u8981\u7531\u5185\u5b58\u5e26\u5bbd\u51b3\u5b9a\u800c\u975e\u8ba1\u7b97\u80fd\u529b\u3002<\/p>\n

      \n

      3 AI \u63a8\u7406\u9002\u914d\u8981\u70b9<\/h3>\n

      3.1 \u7f16\u8bd1\u5668\u4e0e\u5de5\u5177\u94fe<\/h4>\n

      \u8fc1\u79fb\u5230 ARM \u670d\u52a1\u5668\u65f6，\u7b2c\u4e00\u6b65\u662f\u786e\u8ba4\u5de5\u5177\u94fe\u652f\u6301：<\/p>\n

      # \u68c0\u67e5\u5f53\u524d\u67b6\u6784<\/span>
      \nuname<\/span> -m<\/span> # \u8f93\u51fa aarch64 \u8868\u793a ARM 64\u4f4d<\/span>
      \nlscpu |<\/span> grep<\/span> -E<\/span> "Architecture|CPU(s)|Thread"<\/span><\/p>\n

      # \u68c0\u67e5 SVE \u652f\u6301<\/span>
      \ngrep<\/span> -m1<\/span> "sve"<\/span> \/proc\/cpuinfo<\/p>\n

      # \u4f7f\u7528 GCC \u7f16\u8bd1\u65f6\u542f\u7528 ARM \u4f18\u5316<\/span>
      \ngcc -O3<\/span> -march<\/span>=<\/span>armv8.2-a+sve -o<\/span> my_inference my_inference.c<\/p>\n

      3.2 Python\/PyTorch \u7684 ARM \u9002\u914d<\/h4>\n

      \u4e3b\u6d41\u6df1\u5ea6\u5b66\u4e60\u6846\u67b6\u5747\u5df2\u652f\u6301 ARM AArch64，\u4f46\u9700\u6ce8\u610f\u7248\u672c：<\/p>\n

      import<\/span> torch
      \nimport<\/span> platform<\/p>\n

      print<\/span>(<\/span>f"Architecture: <\/span>{<\/span>platform.<\/span>machine(<\/span>)<\/span>}<\/span><\/span>"<\/span><\/span>)<\/span> # aarch64<\/span>
      \nprint<\/span>(<\/span>f"PyTorch version: <\/span>{<\/span>torch.<\/span>__version__}<\/span><\/span>"<\/span><\/span>)<\/span><\/p>\n

      # \u68c0\u67e5\u662f\u5426\u542f\u7528\u4e86 ARM \u4f18\u5316\u540e\u7aef<\/span>
      \nprint<\/span>(<\/span>torch.<\/span>backends.<\/span>mkldnn.<\/span>is_available(<\/span>)<\/span>)<\/span> # ARM \u4e0a\u901a\u5e38\u4e3a False<\/span>
      \nprint<\/span>(<\/span>torch.<\/span>backends.<\/span>openmp.<\/span>is_available(<\/span>)<\/span>)<\/span> # \u5e94\u4e3a True<\/span><\/p>\n

      # ARM \u4e0a\u63a8\u8350\u4f7f\u7528 OpenBLAS \u6216 BLIS \u4f5c\u4e3a BLAS \u540e\u7aef<\/span>
      \n# \u901a\u8fc7\u73af\u5883\u53d8\u91cf\u63a7\u5236\u7ebf\u7a0b\u6570<\/span>
      \nimport<\/span> os
      \nos.<\/span>environ[<\/span>"OMP_NUM_THREADS"<\/span>]<\/span> =<\/span> "8"<\/span> # \u6839\u636e\u5b9e\u9645\u6838\u6570\u8c03\u6574<\/span>
      \nos.<\/span>environ[<\/span>"OPENBLAS_NUM_THREADS"<\/span>]<\/span> =<\/span> "8"<\/span><\/p>\n

      3.3 \u63a8\u7406\u5f15\u64ce\u9009\u578b\u5efa\u8bae<\/h4>\n\n\u63a8\u7406\u5f15\u64ceARM \u652f\u6301\u4f18\u5316\u7a0b\u5ea6\u63a8\u8350\u573a\u666f<\/tr>\n\n\n\n\n\n
      llama.cpp<\/td>\n\u539f\u751f\u652f\u6301<\/td>\n\u9ad8（\u6709 SVE\/NEON \u4e13\u7528\u8def\u5f84）<\/td>\n7B-70B \u6a21\u578b CPU \u63a8\u7406<\/td>\n<\/tr>\n
      ONNX Runtime<\/td>\n\u652f\u6301<\/td>\n\u4e2d（\u6709 ACL\/ARM NN \u540e\u7aef）<\/td>\nONNX \u683c\u5f0f\u6a21\u578b<\/td>\n<\/tr>\n
      OpenVINO<\/td>\n\u6709\u9650\u652f\u6301<\/td>\n\u4e2d<\/td>\n\u4e3b\u8981\u9488\u5bf9 Intel，ARM \u6027\u80fd\u4e00\u822c<\/td>\n<\/tr>\n
      TensorFlow Lite<\/td>\n\u652f\u6301<\/td>\n\u9ad8（\u6709 NEON \u4f18\u5316）<\/td>\n\u8f7b\u91cf\u7ea7\/\u8fb9\u7f18\u573a\u666f<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

      3.4 \u5e38\u89c1\u517c\u5bb9\u6027\u95ee\u9898<\/h4>\n

      \u95ee\u9898\u4e00：\u4e8c\u8fdb\u5236\u9884\u7f16\u8bd1\u5305\u4e0d\u517c\u5bb9<\/p>\n

      PyPI \u4e0a\u90e8\u5206\u5305\u6ca1\u6709\u63d0\u4f9b ARM \u9884\u7f16\u8bd1\u7248\u672c，pip install \u4f1a\u89e6\u53d1\u6e90\u7801\u7f16\u8bd1：<\/p>\n

      # \u5b89\u88c5\u65f6\u53ef\u80fd\u9700\u8981\u989d\u5916\u7684\u7f16\u8bd1\u4f9d\u8d56<\/span>
      \napt-get<\/span> install<\/span> -y<\/span> gcc g++ make<\/span> cmake libopenblas-dev<\/p>\n

      # \u6216\u76f4\u63a5\u4f7f\u7528 conda-forge，\u63d0\u4f9b\u66f4\u5168\u7684 ARM \u4e8c\u8fdb\u5236\u5305<\/span>
      \nconda install<\/span> -c<\/span> conda-forge pytorch torchvision<\/p>\n

      \u95ee\u9898\u4e8c：x86 \u7279\u6709\u7684 Intel \u6269\u5c55\u4e0d\u53ef\u7528<\/p>\n

      # \u4ee5\u4e0b\u5728 x86 \u4e0a\u6709\u6548，ARM \u4e0a\u9700\u66ff\u6362<\/span>
      \n# x86: import intel_extension_for_pytorch as ipex<\/span>
      \n# ARM: \u6539\u7528 torch \u539f\u751f\u6216 OpenBLAS \u540e\u7aef<\/span><\/p>\n

      # ARM \u4e0a\u7684\u66ff\u4ee3\u4f18\u5316\u65b9\u6848<\/span>
      \nmodel =<\/span> torch.<\/span>compile<\/span>(<\/span>model,<\/span> backend=<\/span>"inductor"<\/span>)<\/span> # PyTorch 2.0+ \u7f16\u8bd1\u4f18\u5316<\/span><\/p>\n

      \u95ee\u9898\u4e09：FP16 \u6027\u80fd\u5dee\u5f02<\/p>\n

      \u90e8\u5206 ARM CPU \u5bf9 FP16 \u7684\u786c\u4ef6\u52a0\u901f\u80fd\u529b\u4e0d\u5982 GPU\/NPU，\u5728\u7eaf CPU \u63a8\u7406\u65f6\u5efa\u8bae\u8bc4\u4f30 FP32 \u4e0e FP16 \u7684\u5b9e\u9645\u541e\u5410\u5dee\u5f02\u540e\u518d\u51b3\u5b9a\u7cbe\u5ea6\u683c\u5f0f\u3002<\/p>\n

      \n

      4 \u6027\u80fd\u57fa\u51c6\u5bf9\u6bd4\u601d\u8def<\/h3>\n

      \u5728\u8fdb\u884c ARM vs x86 \u63a8\u7406\u5bf9\u6bd4\u65f6，\u5efa\u8bae\u5173\u6ce8\u4ee5\u4e0b\u6307\u6807（\u4ee5\u5b9e\u6d4b\u4e3a\u51c6，\u4e0d\u7ed9\u5177\u4f53\u6570\u5b57）：<\/p>\n

    • \u5355\u8bf7\u6c42\u5ef6\u8fdf（Latency）：\u9996 token \u751f\u6210\u65f6\u95f4（TTFT）<\/li>\n
    • \u541e\u5410\u91cf（Throughput）：\u5355\u4f4d\u65f6\u95f4\u5904\u7406\u7684 token \u6570<\/li>\n
    • \u5185\u5b58\u5e26\u5bbd\u5229\u7528\u7387：\u4f7f\u7528 perf \u6216 likwid \u6d4b\u91cf<\/li>\n
    • \u6bcf\u74e6\u6027\u80fd（Perf\/Watt）：ARM \u5728\u6b64\u9879\u901a\u5e38\u6709\u4f18\u52bf<\/li>\n

      # \u4f7f\u7528 perf \u6d4b\u91cf\u5185\u5b58\u5e26\u5bbd\u5229\u7528\u7387<\/span>
      \nperf stat<\/span> -e<\/span> cache-misses,cache-references,instructions .\/inference_benchmark<\/p>\n

      # \u6d4b\u91cf\u5185\u5b58\u5e26\u5bbd<\/span>
      \nlikwid-perfctr -C<\/span> 0<\/span>-7 -g<\/span> MEM .\/inference_benchmark<\/p>\n

      \n

      5 \u603b\u7ed3<\/h3>\n

      ARM \u670d\u52a1\u5668 CPU \u5728\u5927\u6a21\u578b\u63a8\u7406\u573a\u666f\u7684\u6838\u5fc3\u4f18\u52bf\u5728\u4e8e：\u5927\u6838\u5fc3\u6570\u91cf\u3001\u9ad8\u5185\u5b58\u5e26\u5bbd\u5229\u7528\u7387\u3001SVE \u5411\u91cf\u6307\u4ee4\u96c6\u7684\u7075\u6d3b\u6027\u4ee5\u53ca\u66f4\u4f18\u7684\u6bcf\u74e6\u6027\u80fd\u3002\u9002\u914d\u65f6\u9700\u8981\u5173\u6ce8\u5de5\u5177\u94fe\u517c\u5bb9\u6027\u3001BLAS \u540e\u7aef\u9009\u62e9\u4ee5\u53ca x86 \u4e13\u6709\u4f18\u5316\u7684\u66ff\u4ee3\u65b9\u6848\u3002<\/p>\n

      \u8fc1\u79fb\u68c0\u67e5\u6e05\u5355：<\/p>\n

        \n
      • \u786e\u8ba4\u6240\u6709\u4f9d\u8d56\u5305\u6709 AArch64 \u7248\u672c\u6216\u53ef\u4ece\u6e90\u7801\u7f16\u8bd1<\/li>\n
      • \u66ff\u6362 Intel \u4e13\u6709\u6269\u5c55（IPEX\u3001MKL）\u4e3a\u901a\u7528\u66ff\u4ee3\u54c1（OpenBLAS\u3001BLIS）<\/li>\n
      • \u9a8c\u8bc1\u63a8\u7406\u5f15\u64ce\u5bf9 SVE\/NEON \u7684\u4f18\u5316\u8def\u5f84\u662f\u5426\u751f\u6548<\/li>\n
      • \u5bf9\u6bd4 FP16\/INT8\/FP32 \u5728\u76ee\u6807 CPU \u4e0a\u7684\u5b9e\u9645\u6027\u80fd，\u518d\u786e\u5b9a\u90e8\u7f72\u7cbe\u5ea6<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"

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