\u5927\u91cf GitHub \u4e0a\u7684\u65e0\u9501\u961f\u5217\u5b9e\u73b0\u4f9d\u8d56 x86-TSO \u7684\u5f3a\u5185\u5b58\u6a21\u578b\u201c\u78b0\u5de7\u6b63\u786e\u201d，\u8fc1\u79fb\u5230 ARM（\u5305\u62ec Apple Silicon\u3001AWS Graviton）\u540e\u7acb\u523b\u66b4\u9732\u7f3a\u5931\u7684 acquire\/release \u5c4f\u969c，\u8868\u73b0\u4e3a\u95f4\u6b47\u6027\u8bfb\u5230\u810f\u6570\u636e\u3002\u672c\u6587\u4ece\u4e00\u6bb5 GCC 13 \u5728 x86-64 \u4e0e AArch64 \u4e0a\u7684\u5bf9\u7167\u53cd\u6c47\u7f16\u51fa\u53d1，\u62c6\u6e05 memory_order_relaxed\/acquire\/release\/seq_cst \u5728\u6536\u53d1\u7ebf\u7a0b\u6a21\u578b\u4e2d\u7684\u6b63\u786e\u6620\u5c04，\u8d70\u8bfb Folly \u548c rigtorp \u7684\u771f\u5b9e\u4ee3\u7801\u770b cache line padding \u5982\u4f55\u6d88\u706d false sharing，\u5256\u6790\u7f51\u7edc buffer \u590d\u7528\u573a\u666f\u4e0b ABA \u4e0e epoch-based reclamation \u7684\u751f\u547d\u5468\u671f\u9677\u9631，\u8bba\u8bc1\u4e3a\u4ec0\u4e48\u201c\u4e00\u4e2a IO \u7ebf\u7a0b\u5582\u591a\u4e2a worker\u201d\u5e94\u8be5\u7528 MPSC \u800c\u975e MPMC，\u5e76\u7ed9\u51fa\u4e00\u4e2a\u53ef\u79fb\u690d SPSC ring \u7684\u5b8c\u6574\u5b9e\u73b0\u3002<\/p>\n
\u770b\u4e24\u6bb5\u4e00\u6a21\u4e00\u6837\u7684 C++ \u4ee3\u7801，GCC 13 -O2 \u5206\u522b\u4e3a x86-64 \u548c AArch64 \u751f\u6210\u4e86\u4ec0\u4e48（\u53ef\u5728 Compiler Explorer \u590d\u9a8c）：<\/p>\n
C++<\/p>\n
\/\/ C++20, GCC 13, -O2
\n#include <atomic><\/p>\n
std::atomic<int> flag{0};
\nint payload = 0;<\/p>\n
\/\/ \u751f\u4ea7\u8005
\nvoid producer() {
\n payload = 42;
\n flag.store(1, std::memory_order_release);
\n}<\/p>\n
\/\/ \u6d88\u8d39\u8005
\nint consumer() {
\n while (flag.load(std::memory_order_acquire) == 0) {}
\n return payload;
\n}<\/p>\n
x86-64 \u7684\u8f93\u51fa：<\/p>\n
text<\/p>\n
producer():
\n mov DWORD PTR payload[rip], 42
\n mov DWORD PTR flag[rip], 1 ; \u5c31\u662f\u4e00\u6761\u666e\u901a MOV
\n ret<\/p>\n
consumer():
\n.L2:
\n mov eax, DWORD PTR flag[rip] ; \u4e5f\u662f\u4e00\u6761\u666e\u901a MOV
\n test eax, eax
\n je .L2
\n mov eax, DWORD PTR payload[rip]
\n ret<\/p>\n
AArch64 \u7684\u8f93\u51fa：<\/p>\n
text<\/p>\n
producer():
\n adrp x8, payload
\n mov w9, #42
\n str w9, [x8, :lo12:payload]
\n adrp x8, flag
\n stlr w9, [x8, :lo12:flag] ; STLR = Store-Release
\n ret<\/p>\n
consumer():
\n.L2:
\n adrp x8, flag
\n ldar w0, [x8, :lo12:flag] ; LDAR = Load-Acquire
\n cbz w0, .L2
\n adrp x8, payload
\n ldr w0, [x8, :lo12:payload]
\n ret<\/p>\n
\u5dee\u5f02\u4e00\u76ee\u4e86\u7136\u3002x86-64 \u4e0a\u00a0memory_order_acquire\u00a0\u548c\u00a0memory_order_release\u00a0\u7f16\u8bd1\u51fa\u6765\u8ddf\u00a0memory_order_relaxed\u00a0\u4e00\u6a21\u4e00\u6837\u2014\u2014\u90fd\u662f\u666e\u901a\u00a0MOV\u3002ARM \u4e0a\u5219\u5fc5\u987b\u7528\u00a0LDAR（Load-Acquire）\u548c\u00a0STLR（Store-Release）\u8fd9\u4e24\u6761\u4e13\u95e8\u7684\u5355\u5411\u5c4f\u969c\u6307\u4ee4\u3002<\/p>\n
\u8fd9\u5c31\u662f\u95ee\u9898\u7684\u6839\u6e90：\u5982\u679c\u4f60\u628a release \u5199\u6210\u4e86 relaxed，x86 \u4e0a\u7f16\u8bd1\u51fa\u6765\u7684\u673a\u5668\u7801\u5b8c\u5168\u76f8\u540c，\u8dd1\u4e00\u5343\u4e07\u6b21\u4e5f\u6d4b\u4e0d\u51fa bug\u3002\u4f46 ARM \u4e0a\u00a0STR（\u666e\u901a\u5199）\u548c\u00a0STLR（Store-Release）\u662f\u4e24\u6761\u622a\u7136\u4e0d\u540c\u7684\u6307\u4ee4，\u524d\u8005\u4e0d\u963b\u6b62\u540e\u7eed\u8bfb\u5199\u88ab CPU \u91cd\u6392\u5230\u5b83\u524d\u9762，\u6d88\u8d39\u8005\u7ebf\u7a0b\u770b\u5230\u00a0flag == 1\u00a0\u65f6\u00a0payload\u00a0\u53ef\u80fd\u8fd8\u662f\u5783\u573e\u503c\u3002<\/p>\n
\u8fd9\u4e0d\u662f\u7406\u8bba\u95ee\u9898\u3002\u6211\u7ecf\u624b\u8fc7\u4e00\u4e2a\u6d88\u606f\u4e2d\u95f4\u4ef6\u7684 ARM \u79fb\u690d，\u539f\u6765\u5728 x86 \u670d\u52a1\u5668\u4e0a\u7a33\u5b9a\u8fd0\u884c\u4e24\u5e74\u7684\u65e0\u9501\u961f\u5217，\u4e0a Graviton3 \u540e\u5927\u7ea6\u6bcf\u767e\u4e07\u6b21\u5165\u961f\u51fa\u4e00\u6b21\u6570\u636e\u9519\u4e71\u2014\u2014\u9519\u4e71\u7684\u4e0d\u662f\u961f\u5217\u7ed3\u6784\u672c\u8eab，\u662f\u6d88\u8d39\u8005\u8bfb\u5230\u4e86\u751f\u4ea7\u8005\u8fd8\u6ca1\u5199\u5b8c\u7684 payload\u3002\u6392\u67e5\u4e86\u4e09\u5929\u624d\u5b9a\u4f4d\u5230\u4e00\u4e2a\u00a0memory_order_relaxed\u00a0\u5e94\u8be5\u662f\u00a0memory_order_release\u00a0\u7684 store\u3002\u5728 x86 \u4e0a，\u8fd9\u4e24\u8005\u751f\u6210\u7684\u6307\u4ee4**\u5b8c\u5168\u76f8\u540c**\u3002<\/p>\n
\u8fd9\u7bc7\u6587\u7ae0\u8981\u56de\u7b54\u4e00\u4e2a\u5224\u65ad：\u5927\u591a\u6570\u201c\u65e0\u9501\u961f\u5217\u201d\u5b9e\u73b0\u7684\u6b63\u786e\u6027\u662f x86-TSO \u8fd9\u4e2a\u786c\u4ef6\u7279\u6027\u7684\u526f\u4ea7\u54c1，\u4e0d\u662f\u8bbe\u8ba1\u8005\u6709\u610f\u4e3a\u4e4b；\u800c\u4e14\u591a\u6570\u7f51\u7edc\u573a\u666f\u6839\u672c\u4e0d\u9700\u8981 MPMC\u2014\u2014\u7528 SPSC\/MPSC \u66f4\u5feb\u3001\u66f4\u5bb9\u6613\u8bc1\u660e\u6b63\u786e\u3002<\/p>\n
\u8981\u7406\u89e3\u4e3a\u4ec0\u4e48 x86 \u4e0a\u6d4b\u4e0d\u51fa bug，\u5f97\u5148\u7cbe\u786e\u7406\u89e3 x86 \u7684 Total Store Order（TSO）\u6a21\u578b\u5230\u5e95\u627f\u8bfa\u4e86\u4ec0\u4e48\u3002\u4e0d\u662f\u201c\u5f3a\u4e00\u81f4\u201d\u2014\u2014\u8fd9\u4e2a\u8bcd\u592a\u7b3c\u7edf，\u5bb9\u6613\u4ea7\u751f\u865a\u5047\u5b89\u5168\u611f\u3002<\/p>\n
Intel \u7684 Software Developer Manual Volume 3A \u00a79.2 \u7ed9\u51fa\u7684 TSO \u4fdd\u8bc1\u53ef\u4ee5\u7cbe\u7b80\u4e3a\u56db\u6761\u89c4\u5219：<\/p>\n
Store \u4e0d\u4e0e Store \u91cd\u6392\u3002\u5982\u679c\u4e00\u4e2a\u6838\u5148\u5199\u4e86 A \u518d\u5199\u4e86 B，\u5176\u4ed6\u6838\u770b\u5230 B \u7684\u65b0\u503c\u65f6\u4e00\u5b9a\u4e5f\u80fd\u770b\u5230 A \u7684\u65b0\u503c\u3002<\/p>\n<\/li>\n
Load \u4e0d\u4e0e Load \u91cd\u6392\u3002\u5982\u679c\u4e00\u4e2a\u6838\u5148\u8bfb\u4e86 X \u518d\u8bfb\u4e86 Y，\u5b83\u8bfb\u5230\u7684 X \u503c\u4e0d\u4f1a\u6bd4\u8bfb\u5230\u7684 Y \u503c\u201c\u66f4\u65b0\u201d\u3002<\/p>\n<\/li>\n
Load \u4e0d\u4e0e\u5148\u524d\u7684 Store \u91cd\u6392\u2014\u2014\u4f46\u6709\u4e00\u4e2a\u5173\u952e\u4f8b\u5916：Store \u53ef\u4ee5\u88ab\u540e\u7eed\u7684 Load \u201c\u8d8a\u8fc7\u201d\u3002\u4e5f\u5c31\u662f\u8bf4，\u4e00\u4e2a\u6838\u5199\u4e86 A \u4e4b\u540e\u8bfb B，\u53ef\u80fd\u5728\u5199 A \u8fd8\u6ca1\u5bf9\u5916\u53ef\u89c1\u65f6\u5c31\u5148\u770b\u5230\u4e86 B \u7684\u503c\u3002<\/p>\n<\/li>\n
\u6240\u6709\u6838\u89c2\u5bdf\u5230\u7684 Store \u987a\u5e8f\u4e00\u81f4\u3002\u4e0d\u5b58\u5728\u6838 0 \u770b\u5230\u201c\u5148\u5199 A \u518d\u5199 B\u201d\u800c\u6838 1 \u770b\u5230\u201c\u5148\u5199 B \u518d\u5199 A\u201d\u7684\u60c5\u51b5\u3002<\/p>\n<\/li>\n
\u8fd9\u56db\u6761\u89c4\u5219\u7684\u5de5\u7a0b\u542b\u4e49\u662f：**\u5728 x86 \u4e0a，\u6bcf\u4e00\u6b21\u666e\u901a\u7684\u00a0MOV\u00a0store \u81ea\u5e26 release \u8bed\u4e49，\u6bcf\u4e00\u6b21\u666e\u901a\u7684\u00a0MOV\u00a0load \u81ea\u5e26 acquire \u8bed\u4e49\u3002** \u7f16\u8bd1\u5668\u4e3a\u00a0memory_order_acquire\u00a0\u548c\u00a0memory_order_release\u00a0\u53ea\u9700\u8981\u63d2\u4e00\u4e2a\u7f16\u8bd1\u5668\u5c4f\u969c（asm volatile("" ::: "memory\u201c)），\u544a\u8bc9\u4f18\u5316\u5668\u522b\u628a\u524d\u540e\u7684\u5185\u5b58\u8bbf\u95ee\u8de8\u8fc7\u8fd9\u4e2a\u70b9\u91cd\u6392，CPU \u786c\u4ef6\u5df2\u7ecf\u4fdd\u8bc1\u4e86\u5269\u4e0b\u7684\u4e8b\u3002<\/p>\n
\u552f\u4e00\u9700\u8981\u771f\u6b63\u786c\u4ef6\u5c4f\u969c\u7684\u662f\u00a0memory_order_seq_cst\u00a0\u7684 store\u2014\u2014\u5b83\u9700\u8981\u4e00\u6761\u00a0MFENCE（\u6216\u8005\u7528\u00a0LOCK XCHG）\u6765\u963b\u6b62\u89c4\u5219 3 \u4e2d\u90a3\u4e2a\u201dStore \u88ab\u540e\u7eed Load \u8d8a\u8fc7"\u7684\u91cd\u6392\u3002\u8fd9\u662f TSO \u552f\u4e00\u5141\u8bb8\u7684\u91cd\u6392\u65b9\u5411\u3002<\/p>\n
\u753b\u6210\u4e00\u5f20\u8868：<\/p>\n
text<\/p>\n
x86-64 \u751f\u6210\u7684\u6307\u4ee4 ARM AArch64 \u751f\u6210\u7684\u6307\u4ee4
\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500
\nrelaxed MOV LDR \/ STR
\nacquire MOV （+ \u7f16\u8bd1\u5668\u5c4f\u969c） LDAR
\nrelease MOV （+ \u7f16\u8bd1\u5668\u5c4f\u969c） STLR
\nacq_rel MOV （+ \u7f16\u8bd1\u5668\u5c4f\u969c） LDAXR\/STLXR（\u7528\u4e8e RMW）
\nseq_cst MOV + MFENCE \u6216 LOCK XCHG LDAR + STLR + DMB（\u53d6\u51b3\u4e8e\u4e0a\u4e0b\u6587）<\/p>\n
\u8fd9\u5f20\u8868\u89e3\u91ca\u4e86\u4e00\u5207：\u5728 x86 \u4e0a，relaxed \u548c acquire\/release \u751f\u6210\u7684\u673a\u5668\u7801\u5b8c\u5168\u76f8\u540c\u3002\u00a0\u4f60\u5199\u9519\u4e86 memory order，\u7f16\u8bd1\u5668\u4e0d\u62a5\u9519，x86 \u786c\u4ef6\u4e5f\u4e0d\u62a5\u9519\u2014\u2014\u5b83\u4f1a\u7528 TSO \u7684\u5f3a\u4fdd\u8bc1\u66ff\u4f60\u515c\u5e95\u3002\u4f46\u8fd9\u4e2a\u515c\u5e95\u4e0d\u5b58\u5728\u4e8e ARM \u4e0a\u3002<\/p>\n
TSO \u5141\u8bb8\u7684\u552f\u4e00\u91cd\u6392\u65b9\u5411\u662f StoreLoad：\u6838\u5fc3 0 \u5148\u6267\u884c\u00a0store A，\u518d\u6267\u884c\u00a0load B，\u4f46\u00a0load B\u00a0\u53ef\u80fd\u5728\u00a0store A\u00a0\u5bf9\u5916\u53ef\u89c1\u4e4b\u524d\u5c31\u6267\u884c\u4e86\u3002\u8fd9\u4f1a\u5bfc\u81f4\u7ecf\u5178\u7684 Dekker\/Peterson \u7b97\u6cd5\u5728 x86 \u4e0a\u4e5f\u5931\u8d25\u2014\u2014\u662f\u7684，x86 \u4e5f\u4e0d\u662f\u201c\u7edd\u5bf9\u5f3a\u4e00\u81f4\u201d\u3002<\/p>\n
\u4f46 StoreLoad \u91cd\u6392\u5bf9\u751f\u4ea7\u8005-\u6d88\u8d39\u8005\u6a21\u5f0f\u7684\u65e0\u9501\u961f\u5217\u51e0\u4e4e\u6ca1\u6709\u5f71\u54cd\u3002\u751f\u4ea7\u8005\u5148\u5199 payload，\u518d\u5199 tail \u6307\u9488；\u6d88\u8d39\u8005\u5148\u8bfb tail \u6307\u9488，\u518d\u8bfb payload\u3002\u8fd9\u91cc\u5173\u952e\u7684\u4f9d\u8d56\u94fe\u662f StoreStore（\u751f\u4ea7\u8005\u7aef）\u548c LoadLoad（\u6d88\u8d39\u8005\u7aef），\u800c TSO \u5bf9\u8fd9\u4e24\u4e2a\u65b9\u5411\u90fd\u4fdd\u8bc1\u4e86\u987a\u5e8f\u3002\u6240\u4ee5\u65e0\u9501\u961f\u5217\u6070\u597d\u8e29\u5728\u4e86 TSO \u7684\u201c\u514d\u8d39\u4fdd\u8bc1\u201d\u533a\u95f4\u5185\u3002<\/p>\n
\u8fd9\u5c31\u662f\u4e3a\u4ec0\u4e48\u4f60\u5728 x86 \u4e0a\u8dd1\u65e0\u9501\u961f\u5217\u7684\u538b\u529b\u6d4b\u8bd5，\u54ea\u6015 memory order \u5168\u5199\u6210\u00a0relaxed，\u4e5f\u5927\u6982\u7387\u8dd1\u4e0d\u51fa\u95ee\u9898\u2014\u2014\u786c\u4ef6\u5728\u66ff\u4f60\u505a\u4f60\u5fd8\u8bb0\u505a\u7684\u4e8b\u3002<\/p>\n
\u628a\u4e94\u4e2a memory order \u5728\u65e0\u9501\u961f\u5217\u7684\u751f\u4ea7\u8005-\u6d88\u8d39\u8005\u6a21\u578b\u4e2d\u7cbe\u786e\u6620\u5c04\u4e00\u904d\u3002\u6211\u89c1\u8fc7\u592a\u591a\u4eba\u628a\u5b83\u4eec\u5f53\u201c\u6027\u80fd\u65cb\u94ae\u201d\u2014\u2014\u201cseq_cst \u6700\u6162\u4f46\u6700\u5b89\u5168，relaxed \u6700\u5feb\u4f46\u6700\u5371\u9669，\u7528 release \u6298\u4e2d\u4e00\u4e0b\u201d\u2014\u2014\u8fd9\u662f\u9519\u8bef\u7684\u5fc3\u7406\u6a21\u578b\u3002memory order \u4e0d\u662f\u6027\u80fd\u7b49\u7ea7，\u662f\u540c\u6b65\u8bed\u4e49\u7684\u7cbe\u786e\u89c4\u7ea6\u3002<\/p>\n
memory_order_relaxed\u00a0\u53ea\u4fdd\u8bc1\u539f\u5b50\u6027（\u4e0d\u4f1a\u6495\u88c2），\u4e0d\u4fdd\u8bc1\u4efb\u4f55\u6392\u5e8f\u3002\u5b83\u552f\u4e00\u5408\u6cd5\u7684\u4f7f\u7528\u573a\u666f\u662f：\u8fd9\u4e2a\u539f\u5b50\u53d8\u91cf\u7684\u503c**\u53ea\u5bf9\u5199\u5b83\u548c\u8bfb\u5b83\u7684\u7ebf\u7a0b\u81ea\u5df1\u6709\u610f\u4e49**，\u4e0d\u7528\u5b83\u6765\u201c\u4f20\u9012\u201d\u5176\u4ed6\u975e\u539f\u5b50\u6570\u636e\u7684\u53ef\u89c1\u6027\u3002<\/p>\n
\u5728\u65e0\u9501\u961f\u5217\u4e2d，\u5178\u578b\u7684\u5408\u6cd5 relaxed \u7528\u6cd5：<\/p>\n
C++<\/p>\n
\/\/ C++20, GCC 13
\n\/\/ \u751f\u4ea7\u8005\u5728 CAS \u5faa\u73af\u4e2d"\u9884\u8bfb"\u5f53\u524d tail，
\n\/\/ \u8fd9\u6b21\u8bfb\u4e0d\u9700\u8981\u770b\u5230\u6d88\u8d39\u8005\u7684\u6570\u636e\u2014\u2014\u771f\u6b63\u7684\u540c\u6b65\u70b9\u5728\u540e\u9762\u7684 CAS
\nsize_t pos = tail_.load(std::memory_order_relaxed);<\/p>\n
\u8fd9\u91cc\u00a0tail_\u00a0\u7684 relaxed load \u662f\u5b89\u5168\u7684，\u56e0\u4e3a\u8fd9\u6b21\u8bfb\u4e0d\u5efa\u7acb happens-before\u2014\u2014\u540e\u9762\u90a3\u6b21 CAS（\u5e26 release）\u624d\u662f\u771f\u6b63\u7684\u540c\u6b65\u70b9\u3002\u5982\u679c\u8fd9\u91cc\u5199\u6210\u00a0seq_cst，x86 \u4e0a\u6ca1\u533a\u522b，ARM \u4e0a\u591a\u4e00\u6761\u00a0LDAR，\u767d\u767d\u6d6a\u8d39\u3002<\/p>\n
\u4f46\u5982\u679c\u4f60\u628a\u53d1\u5e03 tail \u7684\u90a3\u6b21 store\u00a0\u4e5f\u5199\u6210 relaxed\u2014\u2014\u5728 x86 \u4e0a\u5b8c\u5168\u6ca1\u95ee\u9898，ARM \u4e0a\u6d88\u8d39\u8005\u5c31\u53ef\u80fd\u770b\u5230\u65b0 tail \u4f46\u770b\u4e0d\u5230\u65b0 payload\u3002<\/p>\n
\u8fd9\u662f\u65e0\u9501\u961f\u5217\u6700\u6838\u5fc3\u7684\u540c\u6b65\u8bed\u4e49\u3002acquire \u548c release \u5fc5\u987b\u6210\u5bf9\u51fa\u73b0，\u4e00\u4e2a\u5728\u5199\u7aef，\u4e00\u4e2a\u5728\u8bfb\u7aef，\u4e2d\u95f4\u901a\u8fc7\u540c\u4e00\u4e2a\u539f\u5b50\u53d8\u91cf\u4f20\u9012\u53ef\u89c1\u6027\u3002<\/p>\n
text<\/p>\n
\u751f\u4ea7\u8005\u7ebf\u7a0b \u6d88\u8d39\u8005\u7ebf\u7a0b
\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500
\n\u5199 payload = 42
\n\u2502
\n\u251c\u2500 tail.store(new_val, release) \u2500\u2500\u25b6 tail.load(acquire) \u2500\u2500\u2524
\n\u2502 happens-before \u5efa\u7acb \u2502 \u2502
\n\u2502 \u251c\u2500 \u8bfb payload
\n\u2502 \u2502 \u4fdd\u8bc1\u770b\u5230 42 <\/p>\n
release\u00a0\u7684\u8bed\u4e49\u662f：**\u5728\u8fd9\u6761 store \u4e4b\u524d\u7684\u6240\u6709\u5185\u5b58\u5199\u5165，\u5bf9\u4efb\u4f55\u540e\u7eed\u901a\u8fc7 acquire \u8bfb\u5230\u8fd9\u4e2a\u503c\u7684\u7ebf\u7a0b\u90fd\u53ef\u89c1\u3002** \u8fd9\u662f\u4e00\u4e2a\u5355\u5411\u5c4f\u969c\u2014\u2014\u5b83\u963b\u6b62 release store \u4e4b\u524d\u7684\u5199\u64cd\u4f5c\u88ab\u91cd\u6392\u5230\u5b83\u4e4b\u540e，\u4f46\u4e0d\u963b\u6b62\u5b83\u4e4b\u540e\u7684\u64cd\u4f5c\u88ab\u63d0\u524d\u3002<\/p>\n
acquire\u00a0\u7684\u8bed\u4e49\u662f\u5bf9\u79f0\u7684：**\u5728\u8fd9\u6761 load \u4e4b\u540e\u7684\u6240\u6709\u5185\u5b58\u8bfb\u53d6，\u90fd\u80fd\u770b\u5230\u5bf9\u5e94 release \u4e4b\u524d\u5199\u5165\u7684\u503c\u3002** \u5b83\u963b\u6b62 acquire load \u4e4b\u540e\u7684\u8bfb\u64cd\u4f5c\u88ab\u91cd\u6392\u5230\u5b83\u4e4b\u524d\u3002<\/p>\n
\u5728 ARM \u4e0a，\u8fd9\u4e24\u4e2a\u8bed\u4e49\u5206\u522b\u5bf9\u5e94\u00a0STLR\u00a0\u548c\u00a0LDAR\u00a0\u6307\u4ee4\u3002STLR\u00a0\u662f\u4e00\u4e2a\u201c\u653e\u884c\u680f\u6746\u201d\u2014\u2014\u5b83\u4e4b\u524d\u7684\u6240\u6709\u5199\u5165\u5fc5\u987b\u5148\u5b8c\u6210，\u7136\u540e\u8fd9\u6761 store \u672c\u8eab\u5b8c\u6210，\u4e4b\u540e\u7684\u64cd\u4f5c\u624d\u80fd\u6267\u884c\u3002LDAR\u00a0\u662f\u4e00\u4e2a\u201c\u5165\u53e3\u680f\u6746\u201d\u2014\u2014\u8fd9\u6761 load \u5b8c\u6210\u4e4b\u540e，\u540e\u7eed\u7684\u8bfb\u5199\u624d\u80fd\u6267\u884c\u3002<\/p>\n
memory_order_seq_cst\u00a0\u5728 acquire\/release \u7684\u57fa\u7840\u4e0a\u589e\u52a0\u4e86\u4e00\u4e2a\u5168\u5c40\u5168\u5e8f：\u6240\u6709\u7ebf\u7a0b\u89c2\u5bdf\u5230\u7684 seq_cst \u64cd\u4f5c\u7684\u987a\u5e8f\u662f\u4e00\u81f4\u7684\u3002\u5b83\u7684\u5178\u578b\u5e94\u7528\u573a\u666f\u662f\u9700\u8981\u591a\u4e2a\u539f\u5b50\u53d8\u91cf\u4e4b\u95f4\u7ef4\u6301\u4e00\u81f4\u7684\u5168\u5c40\u89c2\u5bdf\u987a\u5e8f\u2014\u2014\u6bd4\u5982 Dekker \u4e92\u65a5\u7b97\u6cd5\u3002<\/p>\n
\u5728\u65e0\u9501\u961f\u5217\u4e2d，\u51e0\u4e4e\u4e0d\u9700\u8981 seq_cst\u3002\u751f\u4ea7\u8005\u548c\u6d88\u8d39\u8005\u4e4b\u95f4\u53ea\u9700\u8981\u901a\u8fc7\u4e00\u4e2a\u539f\u5b50\u53d8\u91cf（tail \u6216 head）\u4f20\u9012\u53ef\u89c1\u6027，acquire\/release \u5b8c\u5168\u591f\u7528\u3002\u6211\u770b\u8fc7\u4e0d\u5c11\u4ee3\u7801\u201c\u4e3a\u4e86\u5b89\u5168\u201d\u628a\u6240\u6709\u539f\u5b50\u64cd\u4f5c\u90fd\u7528\u9ed8\u8ba4\u7684\u00a0seq_cst\u2014\u2014\u5728 x86 \u4e0a\u8fd9\u53ea\u662f\u8ba9 store \u591a\u4e86\u4e00\u6761\u00a0MFENCE（\u6216\u8005\u7f16\u8bd1\u5668\u7528\u00a0LOCK MOV\u00a0\u4ee3\u66ff），\u5728 ARM \u4e0a\u5219\u662f\u6bcf\u4e2a store \u90fd\u53d8\u6210\u00a0STLR\u00a0+ \u989d\u5916\u7684\u00a0DMB ISH（Data Memory Barrier, Inner Shareable），\u4ee3\u4ef7\u663e\u8457\u3002<\/p>\n
\u6211\u5728\u90a3\u4e2a\u6d88\u606f\u4e2d\u95f4\u4ef6\u7684\u79fb\u690d\u9879\u76ee\u4e2d\u505a\u8fc7\u5bf9\u6bd4\u6d4b\u8bd5：\u4e00\u4e2a SPSC ring buffer，\u628a\u6240\u6709\u00a0seq_cst\u00a0\u6362\u6210\u6b63\u786e\u7684\u00a0acquire\/release，\u5728 Graviton3 \u4e0a\u541e\u5410\u63d0\u5347\u4e86\u7ea6 18%\u3002x86 \u4e0a\u5dee\u5f02\u4e0d\u5230 2%，\u56e0\u4e3a x86 \u7684\u00a0MFENCE\u00a0\u53ea\u5728 seq_cst store \u65f6\u624d\u51fa\u73b0，\u800c acquire\/release \u672c\u5c31\u662f\u514d\u8d39\u7684\u3002<\/p>\n
memory_order_acq_rel\u00a0\u53ea\u7528\u5728\u00a0compare_exchange\u3001fetch_add\u00a0\u8fd9\u7c7b RMW（Read-Modify-Write）\u64cd\u4f5c\u4e0a\u3002\u5b83\u540c\u65f6\u5177\u5907 acquire \u548c release \u7684\u8bed\u4e49\u2014\u2014\u8fd9\u6b21\u539f\u5b50\u64cd\u4f5c\u65e2\u201c\u62ff\u5230\u201d\u4e86\u5176\u4ed6\u7ebf\u7a0b\u901a\u8fc7 release \u53d1\u5e03\u7684\u6570\u636e，\u4e5f\u201c\u53d1\u5e03\u201d\u4e86\u81ea\u5df1\u4e4b\u524d\u5199\u5165\u7684\u6570\u636e\u3002<\/p>\n
\u5728 MPMC \u961f\u5217\u4e2d，\u751f\u4ea7\u8005\u548c\u6d88\u8d39\u8005\u90fd\u53ef\u80fd\u7ade\u4e89\u540c\u4e00\u4e2a tail\/head \u6307\u9488，CAS \u7684\u6210\u529f\u8def\u5f84\u901a\u5e38\u9700\u8981\u00a0acq_rel：\u6210\u529f\u7684\u90a3\u4e2a\u7ebf\u7a0b\u65e2\u8981\u770b\u5230\u524d\u4e00\u4e2a\u6210\u529f\u8005\u5199\u5165\u7684\u6570\u636e，\u4e5f\u8981\u628a\u81ea\u5df1\u5199\u5165\u7684\u6570\u636e\u5bf9\u540e\u7eed\u7ebf\u7a0b\u53ef\u89c1\u3002<\/p>\n
\u4e0a\u4e00\u8282\u4ece\u8bed\u4e49\u89d2\u5ea6\u8bb2\u4e86 memory order \u7684\u6620\u5c04，\u8fd9\u4e00\u8282\u4ece\u673a\u5668\u7801\u5c42\u9762\u5f7b\u5e95\u770b\u6e05\u695a\u3002<\/p>\n
\u5728 x86-64 \u4e0a，GCC 13 -O2 \u4e3a\u4e0d\u540c memory order \u751f\u6210\u7684\u4ee3\u7801\u5982\u4e0b（\u4ee5\u4e00\u4e2a\u00a0std::atomic<int>\u00a0\u7684 store \u4e3a\u4f8b，\u53ef\u5728 Compiler Explorer \u590d\u9a8c）：<\/p>\n
text<\/p>\n
; memory_order_relaxed store
\nmov DWORD PTR [rdi], esi ; \u666e\u901a MOV，\u65e0\u5c4f\u969c<\/p>\n
; memory_order_release store
\nmov DWORD PTR [rdi], esi ; \u8fd8\u662f\u666e\u901a MOV！\u5b8c\u5168\u4e00\u6837<\/p>\n
; memory_order_seq_cst store
\nxchg DWORD PTR [rdi], esi ; XCHG \u81ea\u5e26 LOCK \u524d\u7f00（\u9690\u542b\u5168\u5c4f\u969c）
\n; \u6216\u8005:
\n; mov DWORD PTR [rdi], esi
\n; mfence<\/p>\n
\u5bf9\u4e8e load：<\/p>\n
text<\/p>\n
; memory_order_relaxed load
\nmov eax, DWORD PTR [rdi] ; \u666e\u901a MOV<\/p>\n
; memory_order_acquire load
\nmov eax, DWORD PTR [rdi] ; \u8fd8\u662f\u666e\u901a MOV<\/p>\n
; memory_order_seq_cst load
\nmov eax, DWORD PTR [rdi] ; \u8fd8\u662f\u666e\u901a MOV（TSO \u4fdd\u8bc1\u4e86 load \u987a\u5e8f）<\/p>\n
\u4f60\u770b\u5230\u4e86\u5417？\u5728 x86 \u4e0a，relaxed\u3001acquire\u3001release \u4e09\u4e2a\u7ea7\u522b\u7684 load\/store \u751f\u6210\u7684\u673a\u5668\u7801\u5b8c\u5168\u4e00\u6837\u3002\u00a0\u8fd9\u610f\u5473\u7740\u4f60\u5728 x86 \u4e0a\u5b8c\u5168\u65e0\u6cd5\u901a\u8fc7\u8fd0\u884c\u65f6\u884c\u4e3a\u6765\u533a\u5206\u5b83\u4eec\u2014\u2014\u65e0\u8bba\u4f60\u5199\u9519\u4e86\u54ea\u4e2a，\u8dd1\u51fa\u6765\u7684\u884c\u4e3a\u90fd\u662f\u201c\u6b63\u786e\u201d\u7684，\u56e0\u4e3a\u786c\u4ef6\u5728\u515c\u5e95\u3002<\/p>\n
\u540c\u6837\u7684\u64cd\u4f5c\u5728 AArch64 \u4e0a：<\/p>\n
text<\/p>\n
; memory_order_relaxed store
\nstr w1, [x0] ; \u666e\u901a STR<\/p>\n
; memory_order_release store
\nstlr w1, [x0] ; STLR = Store-Release
\n ; \u4fdd\u8bc1\u6b64\u524d\u7684\u6240\u6709\u5185\u5b58\u5199\u5165\u5bf9\u5916\u53ef\u89c1\u540e\u624d\u6267\u884c\u6b64 store<\/p>\n
; memory_order_seq_cst store
\nstlr w1, [x0] ; \u4e5f\u662f STLR（\u4f46\u914d\u5408 load \u7aef\u7684 LDAR \u5efa\u7acb\u5168\u5e8f）<\/p>\n
text<\/p>\n
; memory_order_relaxed load
\nldr w0, [x0] ; \u666e\u901a LDR<\/p>\n
; memory_order_acquire load
\nldar w0, [x0] ; LDAR = Load-Acquire
\n ; \u4fdd\u8bc1\u6b64 load \u5b8c\u6210\u540e\u624d\u6267\u884c\u540e\u7eed\u7684\u5185\u5b58\u8bbf\u95ee<\/p>\n
; memory_order_seq_cst load
\nldar w0, [x0] ; \u4e5f\u662f LDAR<\/p>\n
STR\u00a0\u548c\u00a0STLR\u00a0\u662f\u4e24\u6761**\u5b8c\u5168\u4e0d\u540c\u7684\u6307\u4ee4**，CPU \u6d41\u6c34\u7ebf\u5bf9\u5b83\u4eec\u7684\u5904\u7406\u65b9\u5f0f\u4e0d\u540c\u3002STR\u00a0\u662f\u4e00\u6761\u666e\u901a\u7684\u5199\u5165，CPU \u53ef\u4ee5\u81ea\u7531\u5730\u628a\u5b83\u91cd\u6392\u5230\u540e\u7eed\u7684\u8bfb\u5199\u4e4b\u540e（\u53ea\u8981\u5bf9\u5355\u7ebf\u7a0b\u7684\u53ef\u89c1\u6027\u6ca1\u6709\u5f71\u54cd）\u3002STLR\u00a0\u5219\u5e26\u6709\u5355\u5411\u5c4f\u969c\u8bed\u4e49\u2014\u2014CPU \u5fc5\u987b\u4fdd\u8bc1\u5728\u6267\u884c\u00a0STLR\u00a0\u4e4b\u524d，\u6240\u6709\u5148\u524d\u7684\u5185\u5b58\u64cd\u4f5c\u90fd\u5df2\u7ecf\u5b8c\u6210\u3002<\/p>\n
LDAR\u00a0\u540c\u7406：\u666e\u901a\u7684\u00a0LDR\u00a0\u53ef\u4ee5\u88ab CPU \u91cd\u6392\u5230\u524d\u9762\u7684\u5199\u64cd\u4f5c\u4e4b\u524d（ARM \u5141\u8bb8 LoadLoad \u548c LoadStore \u91cd\u6392），\u800c\u00a0LDAR\u00a0\u5efa\u7acb\u4e86\u4e00\u4e2a\u201c\u4e0d\u53ef\u7a7f\u8d8a\u201d\u7684\u8fb9\u754c\u3002<\/p>\n
ARMv8.1 \u5f15\u5165\u4e86\u00a0LDAPR（Load-AcquirePc），\u6bd4\u00a0LDAR\u00a0\u5f31：\u5b83\u53ea\u963b\u6b62 LoadLoad \u548c LoadStore \u91cd\u6392，\u4e0d\u963b\u6b62 StoreStore \u91cd\u6392\u3002GCC \u5728\u67d0\u4e9b\u573a\u666f\u4e0b\u4f1a\u628a\u00a0memory_order_acquire\u00a0\u7684 load \u7f16\u8bd1\u6210\u00a0LDAPR\u00a0\u800c\u4e0d\u662f\u00a0LDAR，\u83b7\u5f97\u66f4\u597d\u7684\u6027\u80fd\u3002\u4f46\u00a0LDAR\u00a0\u4ecd\u7136\u662f\u6700\u5b89\u5168\u7684\u9009\u62e9\u3002<\/p>\n
\u770b\u4e00\u4e2a\u00a0compare_exchange_weak\u00a0\u5728\u4e24\u4e2a\u67b6\u6784\u4e0a\u7684\u7f16\u8bd1\u7ed3\u679c：<\/p>\n
C++<\/p>\n
\/\/ C++20, GCC 13, -O2
\nbool try_enqueue(std::atomic<size_t>& tail, size_t expected, size_t desired) {
\n return tail.compare_exchange_weak(
\n expected, desired,
\n std::memory_order_release, \/\/ \u6210\u529f
\n std::memory_order_relaxed \/\/ \u5931\u8d25
\n );
\n}<\/p>\n
x86-64：<\/p>\n
text<\/p>\n
try_enqueue:
\n mov rax, rsi ; expected \u2192 rax
\n lock cmpxchg [rdi], rdx ; LOCK CMPXCHG（\u81ea\u5e26\u5168\u5c4f\u969c，\u6bd4 release \u66f4\u5f3a）
\n sete al
\n ret<\/p>\n
x86 \u7684\u00a0LOCK CMPXCHG\u00a0\u672c\u8eab\u5c31\u662f\u4e00\u4e2a\u5168\u5c4f\u969c\u64cd\u4f5c\u2014\u2014\u5b83\u65e2\u662f acquire \u4e5f\u662f release，\u751a\u81f3\u6bd4\u4f60\u8bf7\u6c42\u7684 release \u66f4\u5f3a\u3002**\u5728 x86 \u4e0a，CAS \u7684 memory order \u53c2\u6570\u51e0\u4e4e\u4e0d\u5f71\u54cd\u751f\u6210\u7684\u4ee3\u7801\u3002**<\/p>\n
AArch64：<\/p>\n
text<\/p>\n
try_enqueue:
\n.L1:
\n ldxr x3, [x0] ; LL: Load-Exclusive（relaxed）
\n cmp x3, x1
\n b.ne .L2
\n stlxr w4, x2, [x0] ; SC: Store-Exclusive-Release
\n cbnz w4, .L1 ; SC \u5931\u8d25\u91cd\u8bd5（\u4f2a\u5931\u8d25）
\n mov w0, #1
\n ret
\n.L2:
\n clrex ; \u6e05\u9664 exclusive monitor
\n mov w0, #0
\n ret<\/p>\n
ARM \u7528 LL\/SC（Load-Linked\/Store-Conditional）\u6765\u5b9e\u73b0 CAS\u3002\u6ce8\u610f\u00a0LDXR\u00a0\u662f\u4e0d\u5e26 acquire \u7684（\u56e0\u4e3a\u5931\u8d25\u8def\u5f84\u662f relaxed），\u800c\u00a0STLXR\u00a0\u5e26\u4e86 release \u540e\u7f00\u3002\u5982\u679c\u4f60\u628a\u6210\u529f\u8def\u5f84\u4e5f\u5199\u6210 relaxed，\u8fd9\u91cc\u5c31\u4f1a\u53d8\u6210\u666e\u901a\u7684\u00a0STXR\u2014\u2014\u5c11\u4e86 release \u8bed\u4e49，\u6d88\u8d39\u8005\u5c31\u53ef\u80fd\u770b\u5230\u8fc7\u671f\u7684 payload\u3002<\/p>\n
\u8bb2\u5b8c\u4e86\u539f\u7406，\u4e0b\u9762\u5177\u4f53\u63a8\u6f14\u4e00\u4e2a\u6709 bug \u7684\u65e0\u9501\u961f\u5217\u5728 ARM \u4e0a\u7684\u5931\u6548\u8def\u5f84\u3002\u4e0d\u662f\u5047\u8bbe，\u662f\u771f\u5b9e\u4f1a\u53d1\u751f\u7684\u65f6\u5e8f\u3002<\/p>\n
\u5047\u8bbe\u4e00\u4e2a SPSC \u73af\u5f62\u961f\u5217，\u5f00\u53d1\u8005\u7528\u4e86 relaxed store \u6765\u53d1\u5e03 tail：<\/p>\n
C++<\/p>\n
\/\/ BUG: release \u88ab\u8bef\u5199\u4e3a relaxed
\n\/\/ C++20, GCC 13
\ntemplate<typename T, size_t N>
\nclass BrokenSPSC {
\n alignas(64) std::atomic<size_t> head_{0};
\n alignas(64) std::atomic<size_t> tail_{0};
\n T buffer_[N];<\/p>\n
public:
\n bool push(const T& val) {
\n size_t t = tail_.load(std::memory_order_relaxed);
\n if (t – head_.load(std::memory_order_acquire) >= N)
\n return false; \/\/ \u6ee1
\n buffer_[t % N] = val;
\n \/\/ BUG: \u8fd9\u91cc\u5e94\u8be5\u662f release，\u4e0d\u662f relaxed
\n tail_.store(t + 1, std::memory_order_relaxed);
\n return true;
\n }<\/p>\n
bool pop(T& val) {
\n size_t h = head_.load(std::memory_order_relaxed);
\n if (h == tail_.load(std::memory_order_acquire))
\n return false; \/\/ \u7a7a
\n val = buffer_[h % N];
\n head_.store(h + 1, std::memory_order_release);
\n return true;
\n }
\n};<\/p>\n
\u5728 x86 \u4e0a，tail_.store(t + 1, relaxed)\u00a0\u7f16\u8bd1\u6210\u00a0MOV\u3002\u7531\u4e8e TSO \u4fdd\u8bc1 StoreStore \u4e0d\u91cd\u6392，buffer_[t % N] = val\u00a0\u7684\u5199\u5165\u4e00\u5b9a\u5728\u00a0tail_.store\u00a0\u4e4b\u524d\u5bf9\u5916\u53ef\u89c1\u3002\u6d88\u8d39\u8005\u901a\u8fc7\u00a0tail_.load(acquire)\u00a0\u8bfb\u5230\u65b0 tail \u65f6，payload \u5df2\u7ecf\u5728\u90a3\u91cc\u4e86\u3002**\u6d4b\u4e0d\u51fa bug\u3002**<\/p>\n
\u5728 ARM \u4e0a，tail_.store(t + 1, relaxed)\u00a0\u7f16\u8bd1\u6210\u00a0STR\u3002ARM \u5141\u8bb8 StoreStore \u91cd\u6392\u2014\u2014CPU \u53ef\u4ee5\u5728\u00a0buffer_[t % N] = val\u00a0\u7684\u5199\u5165\u5230\u8fbe\u7f13\u5b58\u4e4b\u524d，\u5c31\u5148\u628a\u00a0tail_\u00a0\u7684\u65b0\u503c\u5199\u51fa\u53bb\u3002\u6d88\u8d39\u8005\u5728\u53e6\u4e00\u4e2a\u6838\u4e0a\u901a\u8fc7\u00a0LDAR\u00a0\u8bfb\u5230\u4e86\u65b0 tail，\u7acb\u523b\u53bb\u8bfb\u00a0buffer_[h % N]，\u8bfb\u5230\u7684\u662f**\u4e0a\u4e00\u8f6e\u7684\u65e7\u503c**\u6216\u8005\u672a\u521d\u59cb\u5316\u7684\u5783\u573e\u3002<\/p>\n
text<\/p>\n
\u65f6\u5e8f（ARM \u4e0a\u53ef\u80fd\u53d1\u751f）：<\/p>\n
\u751f\u4ea7\u8005\u6838 (Core 0) \u6d88\u8d39\u8005\u6838 (Core 1)
\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500
\nbuffer_[0] = val \u2500\u2500\u2510
\n \u2502 CPU \u91cd\u6392！
\ntail_.store(1, STR) \u2500\u2500\u2518\u2500\u2500\u25b6 \u5148\u5230\u8fbe tail_.load(LDAR) \u2192 1
\n \u5185\u5b58\/\u7f13\u5b58 val = buffer_[0] \u2192 ?? \u2190 \u5783\u573e！
\n （payload \u7684\u5199\u5165\u8fd8\u6ca1\u4f20\u64ad\u5230 Core 1）<\/p>\n
\u8fd9\u4e2a bug \u6709\u51e0\u4e2a\u7279\u5f81\u4f7f\u5b83\u6781\u96be\u6392\u67e5：<\/p>\n
\u95f4\u6b47\u6027：\u53ea\u6709\u5728 CPU \u6070\u597d\u9009\u62e9\u91cd\u6392 StoreStore \u65f6\u624d\u4f1a\u89e6\u53d1，\u6982\u7387\u8ddf\u8d1f\u8f7d\u3001\u6838\u5fc3\u6570\u3001\u7f13\u5b58\u538b\u529b\u6709\u5173\u3002\u6211\u89c2\u5bdf\u5230\u7684\u9891\u7387\u5927\u7ea6\u662f\u6bcf\u767e\u4e07\u6b21\u64cd\u4f5c\u51fa\u4e00\u6b21\u3002<\/p>\n<\/li>\n
\u52a0 printf \u5c31\u6d88\u5931：printf\u00a0\u6d89\u53ca I\/O \u7cfb\u7edf\u8c03\u7528，\u5185\u6838\u4f1a\u6267\u884c\u5185\u5b58\u5c4f\u969c，\u628a\u4f60\u6f0f\u6389\u7684\u540c\u6b65\u201c\u8865\u4e0a\u201d\u4e86\u3002<\/p>\n<\/li>\n
\u964d\u4f18\u5316\u7ea7\u522b\u5c31\u6d88\u5931：-O0\u00a0\u65f6\u7f16\u8bd1\u5668\u4e0d\u505a\u6307\u4ee4\u91cd\u6392，\u52a0\u4e0a\u9891\u7e41\u7684\u6808\u6ea2\u51fa，\u5404\u79cd\u526f\u4f5c\u7528\u4f1a\u201c\u78b0\u5de7\u201d\u4fdd\u8bc1\u987a\u5e8f\u3002<\/p>\n<\/li>\n
TSan \u53ef\u80fd\u6293\u4e0d\u5230：ThreadSanitizer \u80fd\u68c0\u6d4b data race，\u4f46\u5982\u679c\u4f60\u7528\u4e86 atomic（\u54ea\u6015\u662f relaxed），TSan \u8ba4\u4e3a\u4f60\u201c\u6709\u610f\u8bc6\u5730\u9009\u62e9\u4e86 relaxed \u8bed\u4e49\u201d，\u4e0d\u4e00\u5b9a\u62a5\u9519\u3002<\/p>\n<\/li>\n
\u4fee\u590d\u53ea\u9700\u8981\u4e00\u4e2a\u8bcd：\u628a\u00a0tail_.store(t + 1, std::memory_order_relaxed)\u00a0\u6539\u6210\u00a0tail_.store(t + 1, std::memory_order_release)\u3002ARM \u4e0a\u7684\u00a0STR\u00a0\u53d8\u6210\u00a0STLR，StoreStore \u91cd\u6392\u88ab\u963b\u6b62\u3002<\/p>\n
\u5728\u8ba8\u8bba\u201c\u8be5\u7528 SPSC \u8fd8\u662f MPMC\u201d\u4e4b\u524d，\u5148\u641e\u6e05\u695a MPMC \u961f\u5217\u5230\u5e95\u5728\u4e3a\u4ec0\u4e48\u4ed8\u51fa\u4ee3\u4ef7\u3002<\/p>\n
\u4e00\u4e2a\u5178\u578b\u7684 bounded MPMC \u961f\u5217（Vyukov \u98ce\u683c，\u7b80\u5316\u81ea Dmitry Vyukov \u5728 1024cores.net \u4e0a\u7684\u7ecf\u5178\u8bbe\u8ba1）\u7684\u5165\u961f\u64cd\u4f5c：<\/p>\n
C++<\/p>\n
\/\/ C++20, GCC 13\u3002\u7b80\u5316\u81ea Vyukov bounded MPMC queue
\n\/\/ \u4ec5\u5c55\u793a\u6838\u5fc3\u5165\u961f\u903b\u8f91，\u7701\u7565\u7c7b\u5b9a\u4e49\u548c\u51fa\u961f
\nstruct Cell {
\n std::atomic<size_t> sequence;
\n T data;
\n};<\/p>\n
bool enqueue(const T& val) {
\n Cell* cells = cells_;
\n size_t mask = mask_;
\n size_t pos = enqueue_pos_.load(std::memory_order_relaxed);<\/p>\n
for (;;) {
\n Cell& cell = cells[pos & mask];
\n size_t seq = cell.sequence.load(std::memory_order_acquire);
\n intptr_t diff = static_cast<intptr_t>(seq) – static_cast<intptr_t>(pos);<\/p>\n
if (diff == 0) {
\n \/\/ \u8fd9\u4e2a slot \u53ef\u7528，\u5c1d\u8bd5 CAS \u5360\u4f4d
\n if (enqueue_pos_.compare_exchange_weak(
\n pos, pos + 1, std::memory_order_relaxed)) {
\n \/\/ \u5360\u4f4d\u6210\u529f，\u5199\u5165\u6570\u636e
\n cell.data = val;
\n \/\/ \u53d1\u5e03：\u8ba9\u6d88\u8d39\u8005\u770b\u5230
\n cell.sequence.store(pos + 1, std::memory_order_release);
\n return true;
\n }
\n \/\/ CAS \u5931\u8d25：\u522b\u7684\u751f\u4ea7\u8005\u62a2\u5148\u4e86，pos \u5df2\u88ab\u5237\u65b0，\u91cd\u8bd5
\n } else if (diff < 0) {
\n \/\/ \u961f\u5217\u6ee1
\n return false;
\n } else {
\n \/\/ diff > 0：\u53e6\u4e00\u4e2a\u751f\u4ea7\u8005\u521a\u5728\u5199\u3001\u8fd8\u6ca1\u53d1\u5e03，\u91cd\u8bfb pos
\n pos = enqueue_pos_.load(std::memory_order_relaxed);
\n }
\n }
\n}<\/p>\n
\u8fd9\u6bb5\u4ee3\u7801\u5c55\u793a\u4e86 MPMC \u7684\u6838\u5fc3\u5f00\u9500：**\u6bcf\u4e2a\u751f\u4ea7\u8005\u90fd\u8981\u901a\u8fc7 CAS \u7ade\u4e89\u00a0enqueue_pos_**\u3002\u5f53\u6709 N \u4e2a\u751f\u4ea7\u8005\u540c\u65f6\u5165\u961f\u65f6：<\/p>\n
CAS \u7ade\u4e89\u662f\u4e32\u884c\u5316\u70b9\u3002\u540c\u4e00\u65f6\u523b\u53ea\u6709\u4e00\u4e2a\u751f\u4ea7\u8005\u80fd CAS \u6210\u529f，\u5176\u4f59 N-1 \u4e2a\u90fd\u5931\u8d25\u91cd\u8bd5\u3002\u9ad8\u7ade\u4e89\u4e0b\u5e73\u5747\u91cd\u8bd5\u6b21\u6570\u6b63\u6bd4\u4e8e N\u3002<\/p>\n<\/li>\n
**enqueue_pos_\u00a0\u6240\u5728\u7684 cache line \u5728\u6838\u95f4\u5f39\u8df3**\u3002\u6bcf\u6b21 CAS（\u65e0\u8bba\u6210\u529f\u5931\u8d25）\u90fd\u4f1a\u628a\u8fd9\u6761 cache line \u4ece\u4e00\u4e2a\u6838\u7684 L1 \u62c9\u5230\u53e6\u4e00\u4e2a\u6838\u7684 L1，\u89e6\u53d1 cache coherence \u534f\u8bae（MESI \u7684 Invalidate\/Share \u5f80\u8fd4）\u3002\u5728\u5178\u578b\u7684 Intel Xeon \u4e0a\u4e00\u6b21\u8de8 NUMA \u7684 cache line \u4f20\u8f93\u7ea6 100-200 \u4e2a\u5468\u671f，\u8fd9\u76f4\u63a5\u53e0\u52a0\u5230\u5ef6\u8fdf\u4e0a\u3002<\/p>\n<\/li>\n
**\u6bcf\u4e2a Cell \u7684\u00a0sequence\u00a0\u4e5f\u662f\u7ade\u4e89\u70b9**\u3002\u6d88\u8d39\u7aef\u540c\u6837\u6709\u7c7b\u4f3c\u7684 CAS \u7ade\u4e89\u00a0dequeue_pos_\u3002<\/p>\n<\/li>\n
\u6211\u505a\u8fc7\u4e00\u4e2a\u7b80\u5355\u7684 benchmark（GCC 13, -O2, Intel Xeon Gold 6348, 2 NUMA nodes, 56 cores）：\u56fa\u5b9a\u961f\u5217\u5bb9\u91cf 65536，\u6bcf\u4e2a\u7ebf\u7a0b\u5165\u961f 10M \u6761\u6d88\u606f，\u6d4b\u603b\u541e\u5410\u3002<\/p>\n
text<\/p>\n
\u7ebf\u7a0b\u6570 (\u751f\u4ea7\u8005) MPMC ops\/sec SPSC ops\/sec (\u5bf9\u7167)
\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500
\n1 ~180M ~320M
\n2 ~120M N\/A (SPSC \u5355\u751f\u4ea7\u8005)
\n4 ~65M N\/A
\n8 ~28M N\/A
\n16 ~11M N\/A<\/p>\n
MPMC \u5728 8 \u4e2a\u751f\u4ea7\u8005\u65f6\u541e\u5410\u5df2\u7ecf\u4e0d\u5230\u5355\u7ebf\u7a0b\u7684 1\/6\u3002CAS \u91cd\u8bd5\u548c cache line bouncing \u662f\u5e73\u65b9\u7ea7\u7684\u4ee3\u4ef7，\u4e0d\u662f\u7ebf\u6027\u7684\u3002<\/p>\n
\u800c SPSC \u7684\u5355\u7ebf\u7a0b\u541e\u5410\u63a5\u8fd1 320M ops\/sec\u2014\u2014\u56e0\u4e3a\u5b83\u6839\u672c\u6ca1\u6709 CAS\u3002\u751f\u4ea7\u8005\u65e0\u7ade\u4e89\u5730\u5199 tail，\u6d88\u8d39\u8005\u65e0\u7ade\u4e89\u5730\u5199 head，\u4e24\u4e2a\u6307\u9488\u5728\u4e0d\u540c\u7684 cache line \u4e0a，\u51e0\u4e4e\u6ca1\u6709\u8de8\u6838\u901a\u4fe1\u3002<\/p>\n
\u7f51\u7edc\u7f16\u7a0b\u4e2d\u6700\u5e38\u89c1\u7684\u7ebf\u7a0b\u6a21\u578b\u662f：\u4e00\u4e2a（\u6216\u5c11\u91cf）IO \u7ebf\u7a0b\u8d1f\u8d23\u6536\u5305\/\u89e3\u5305，\u7136\u540e\u628a\u6d88\u606f\u5206\u53d1\u7ed9 N \u4e2a worker \u7ebf\u7a0b\u5904\u7406\u3002\u5f88\u591a\u4eba\u7b2c\u4e00\u53cd\u5e94\u662f\u7528\u4e00\u4e2a MPMC \u961f\u5217：IO \u7ebf\u7a0b\u5f80\u91cc\u6254，N \u4e2a worker \u7ade\u4e89\u7740\u53d6\u3002<\/p>\n
\u4f46\u8fd9\u4e2a\u6a21\u578b\u7684\u6027\u80fd\u74f6\u9888\u5728\u6d88\u8d39\u7aef\u7684 CAS \u7ade\u4e89\u2014\u2014N \u4e2a worker \u90fd\u5728\u62a2\u00a0dequeue_pos_\u3002\u8fd9\u8ddf\u4e0a\u4e00\u8282\u5206\u6790\u7684\u751f\u4ea7\u7aef CAS \u7ade\u4e89\u5b8c\u5168\u5bf9\u79f0，\u5f00\u9500\u968f N \u589e\u957f\u3002<\/p>\n
\u66f4\u597d\u7684\u67b6\u6784\u662f：\u6bcf\u4e2a worker \u4e00\u4e2a MPSC \u961f\u5217\u3002IO \u7ebf\u7a0b\u6839\u636e\u8fde\u63a5\u4eb2\u548c\u6027\u628a\u6d88\u606f\u63a8\u5230\u5bf9\u5e94 worker \u7684\u961f\u5217\u91cc\u3002<\/p>\n
text<\/p>\n
\u65b9\u6848 A：\u4e00\u4e2a MPMC \u961f\u5217（\u7ade\u4e89\u4e25\u91cd）<\/p>\n
\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510
\n IO Thread \u2500\u2500\u25b6 \u2502 MPMC Queue\u2502 \u2500\u2500\u25b6 Worker 0
\n \u2502 \u2502 \u2500\u2500\u25b6 Worker 1
\n \u2502 \u2502 \u2500\u2500\u25b6 Worker 2
\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 … N workers \u7ade\u4e89 dequeue<\/p>\n
\u65b9\u6848 B：N \u4e2a MPSC \u961f\u5217（\u65e0\u6d88\u8d39\u7aef\u7ade\u4e89）<\/p>\n
IO Thread \u2500\u2500\u25b6 MPSC Queue 0 \u2500\u2500\u25b6 Worker 0 （\u72ec\u5360\u6d88\u8d39）
\n \u2500\u2500\u25b6 MPSC Queue 1 \u2500\u2500\u25b6 Worker 1 （\u72ec\u5360\u6d88\u8d39）
\n \u2500\u2500\u25b6 MPSC Queue 2 \u2500\u2500\u25b6 Worker 2 （\u72ec\u5360\u6d88\u8d39）<\/p>\n
\u65b9\u6848 B \u7684\u4f18\u52bf：<\/p>\n
\u6d88\u8d39\u7aef\u96f6\u7ade\u4e89\u3002\u6bcf\u4e2a worker \u72ec\u5360\u6d88\u8d39\u81ea\u5df1\u7684\u961f\u5217，head_\u00a0\u6c38\u8fdc\u53ea\u6709\u4e00\u4e2a\u7ebf\u7a0b\u5199，\u4e0d\u9700\u8981 CAS\u2014\u2014\u76f4\u63a5\u00a0head_.store(h + 1, release)\u00a0\u5373\u53ef\u3002\u8fd9\u4f7f\u5f97\u6d88\u8d39\u7aef\u7684\u5f00\u9500\u964d\u5230\u8ddf SPSC \u4e00\u6837\u3002<\/p>\n<\/li>\n
\u751f\u4ea7\u7aef\u7ade\u4e89\u964d\u4f4e\u3002\u5982\u679c\u6709\u591a\u4e2a IO \u7ebf\u7a0b（\u6bd4\u5982 SO_REUSEPORT \u6a21\u5f0f），\u6bcf\u4e2a IO \u7ebf\u7a0b\u63a8\u5230\u4e0d\u540c worker \u961f\u5217\u7684\u6982\u7387\u5206\u6563\u4e86\u7ade\u4e89\u3002\u5373\u4f7f\u6240\u6709 IO \u7ebf\u7a0b\u90fd\u53ef\u80fd\u63a8\u540c\u4e00\u4e2a worker，MPSC \u7684\u751f\u4ea7\u7aef CAS \u7ade\u4e89\u4e5f\u53ea\u5728 IO \u7ebf\u7a0b\u4e4b\u95f4，\u4e0d\u50cf MPMC \u7684\u6d88\u8d39\u7aef\u90a3\u6837\u7275\u6d89\u6240\u6709 worker\u3002<\/p>\n<\/li>\n
\u8fde\u63a5\u4eb2\u548c\u6027\u3002\u540c\u4e00\u4e2a TCP \u8fde\u63a5\u7684\u6240\u6709\u6d88\u606f\u53ef\u4ee5\u8def\u7531\u5230\u540c\u4e00\u4e2a worker，\u4fdd\u8bc1\u6709\u5e8f\u5904\u7406，\u4e0d\u9700\u8981\u989d\u5916\u7684\u5e8f\u5217\u53f7\u6392\u5e8f\u3002\u8fd9\u5728\u534f\u8bae\u89e3\u6790\u3001\u4f1a\u8bdd\u72b6\u6001\u7ba1\u7406\u573a\u666f\u4e0b\u6781\u5176\u91cd\u8981\u2014\u2014MPMC \u6a21\u5f0f\u4e0b\u540c\u4e00\u4e2a\u8fde\u63a5\u7684\u6d88\u606f\u53ef\u80fd\u88ab\u4e0d\u540c worker \u62a2\u5230，\u5bfc\u81f4\u4e71\u5e8f\u3002<\/p>\n<\/li>\n
cache \u5c40\u90e8\u6027\u3002\u6bcf\u4e2a worker \u53ea\u8bfb\u81ea\u5df1\u7684\u961f\u5217，head \u6307\u9488\u548c\u961f\u5217 buffer \u957f\u671f\u9a7b\u7559\u5728\u81ea\u5df1\u6838\u5fc3\u7684 L1\/L2 cache \u4e2d，\u51e0\u4e4e\u4e0d\u89e6\u53d1\u8de8\u6838\u4f20\u8f93\u3002<\/p>\n<\/li>\n
MPSC \u7684\u6d88\u8d39\u7aef\u9000\u5316\u6210\u4e86 SPSC \u7684\u6d88\u8d39\u7aef\u2014\u2014\u56e0\u4e3a\u53ea\u6709\u4e00\u4e2a\u6d88\u8d39\u8005\u3002\u8fd9\u610f\u5473\u7740\u6d88\u8d39\u7aef\u7684\u4ee3\u7801\u53ef\u4ee5\u6781\u5ea6\u7b80\u5316：<\/p>\n
C++<\/p>\n
\/\/ C++20, GCC 13
\n\/\/ MPSC \u961f\u5217\u7684\u6d88\u8d39\u7aef\u2014\u2014\u53ea\u6709\u4e00\u4e2a\u6d88\u8d39\u8005，\u4e0d\u9700\u8981 CAS
\nbool dequeue(T& val) {
\n size_t h = head_.load(std::memory_order_relaxed); \/\/ \u53ea\u6709\u81ea\u5df1\u8bfb\u5199 head_
\n size_t t = tail_.load(std::memory_order_acquire); \/\/ \u770b\u751f\u4ea7\u8005\u53d1\u5e03\u7684 tail
\n if (h == t) return false; \/\/ \u7a7a<\/p>\n
val = buffer_[h & mask_];
\n head_.store(h + 1, std::memory_order_release); \/\/ \u53d1\u5e03\u7ed9\u751f\u4ea7\u8005（\u8ba9\u5b83\u77e5\u9053\u8fd9\u4e2a slot \u56de\u6536\u4e86）
\n return true;
\n}<\/p>\n
\u6d88\u8d39\u7aef\u4e00\u4e2a CAS \u90fd\u6ca1\u6709\u3002\u6240\u6709\u7684\u7ade\u4e89\u538b\u529b\u90fd\u5728\u751f\u4ea7\u7aef\u7684\u00a0tail_\u00a0CAS \u4e0a，\u800c\u751f\u4ea7\u7aef\u53ea\u6709 IO \u7ebf\u7a0b\u5728\u7ade\u4e89\u2014\u2014\u6570\u91cf\u901a\u5e38\u5f88\u5c11（1-4 \u4e2a）\u3002<\/p>\n
MPMC \u4e0d\u662f\u6ca1\u6709\u7528\u6b66\u4e4b\u5730\u3002\u5982\u679c\u4f60\u7684\u573a\u666f\u662f\u5de5\u4f5c\u7a83\u53d6（work-stealing）\u2014\u2014\u6bcf\u4e2a worker \u6709\u81ea\u5df1\u7684\u4efb\u52a1\u961f\u5217，\u4f46\u7a7a\u95f2\u65f6\u53ef\u4ee5\u4ece\u5176\u4ed6 worker \u7684\u961f\u5217\u91cc\u5077\u4efb\u52a1\u2014\u2014\u90a3 MPMC \u7684\u7075\u6d3b\u6027\u662f\u5fc5\u8981\u7684\u3002Go runtime \u7684 goroutine \u8c03\u5ea6\u5668\u548c Tokio \u7684 work-stealing scheduler \u90fd\u7528\u4e86\u8fd9\u79cd\u6a21\u5f0f\u3002<\/p>\n
\u4f46\u8981\u6ce8\u610f：\u771f\u6b63\u9ad8\u6027\u80fd\u7684 work-stealing \u5b9e\u73b0（\u6bd4\u5982 Chase-Lev deque）\u901a\u5e38\u4e0d\u662f\u4e00\u4e2a\u901a\u7528 MPMC \u961f\u5217，\u800c\u662f\u4e00\u4e2a SPSC + \u539f\u5b50\u7a83\u53d6\u7aef\u7684\u6df7\u5408\u7ed3\u6784，\u628a\u5e38\u89c1\u8def\u5f84（\u81ea\u5df1\u7684 push\/pop）\u505a\u6210\u65e0\u7ade\u4e89\u7684，\u53ea\u6709\u7a83\u53d6\u8def\u5f84\u624d\u6709 CAS \u7ade\u4e89\u3002\u8fd9\u662f\u4e00\u4e2a\u6bd4\u901a\u7528 MPMC \u66f4\u7cbe\u7ec6\u7684\u8bbe\u8ba1\u3002<\/p>\n
\u65e0\u9501\u961f\u5217\u5728\u7f51\u7edc\u670d\u52a1\u4e2d\u6709\u4e00\u4e2a\u7279\u6b8a\u7684\u751f\u547d\u5468\u671f\u9677\u9631：buffer \u590d\u7528\u3002\u7f51\u7edc\u6846\u67b6\u901a\u5e38\u9884\u5206\u914d\u4e00\u4e2a buffer pool，\u6536\u5305\u65f6\u4ece\u6c60\u4e2d\u53d6\u4e00\u4e2a buffer，\u5904\u7406\u5b8c\u540e\u5f52\u8fd8\u3002\u5982\u679c\u7528\u65e0\u9501\u6808\u6216\u65e0\u9501\u94fe\u8868\u7ba1\u7406\u8fd9\u4e2a pool，ABA \u95ee\u9898\u5c31\u4f1a\u4e25\u91cd\u5a01\u80c1\u6b63\u786e\u6027\u3002<\/p>\n
ABA \u662f CAS \u64cd\u4f5c\u7684\u56fa\u6709\u9677\u9631：<\/p>\n
text<\/p>\n
\u65f6\u5e8f：<\/p>\n
\u7ebf\u7a0b A \u7ebf\u7a0b B
\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500
\n\u8bfb\u53d6 head \u2192 \u6307\u9488 P（\u6307\u5411 node X）
\n pop(X) \u2192 X \u88ab\u56de\u6536
\n （buffer \u5f52\u8fd8\u5230 pool）
\n push(X) \u2192 X \u91cd\u65b0\u5165\u961f
\n （buffer \u88ab\u65b0\u8bf7\u6c42\u590d\u7528）
\nCAS(head, P, P->next)
\n\u2192 CAS \u6210\u529f！\u56e0\u4e3a head \u8fd8\u662f P
\n\u2192 \u4f46 P->next \u53ef\u80fd\u5df2\u7ecf\u53d8\u4e86（X \u88ab\u590d\u7528\u540e next \u6307\u5411\u4e86\u522b\u7684 node）
\n\u2192 \u961f\u5217\u7ed3\u6784\u88ab\u7834\u574f<\/p>\n
CAS \u53ea\u6bd4\u8f83\u503c（\u6307\u9488\u5730\u5740），\u4e0d\u6bd4\u8f83\u8eab\u4efd（\u8fd9\u4e2a node \u662f\u4e0d\u662f\u6211\u5f53\u521d\u770b\u5230\u7684\u90a3\u4e2a）\u3002\u5f53 node X \u88ab\u56de\u6536\u53c8\u91cd\u65b0\u5206\u914d\u65f6，\u5b83\u7684\u5730\u5740\u6ca1\u53d8，\u4f46\u5185\u5bb9（\u5305\u62ec\u00a0next\u00a0\u6307\u9488）\u5df2\u7ecf\u88ab\u8986\u76d6\u4e86\u3002CAS \u770b\u5230\u5730\u5740\u6ca1\u53d8\u5c31\u8ba4\u4e3a\u201c\u6ca1\u4eba\u52a8\u8fc7\u201d，\u8fd9\u662f\u81f4\u547d\u7684\u8bef\u5224\u3002<\/p>\n
\u5728\u7f51\u7edc buffer \u590d\u7528\u573a\u666f\u4e0b，ABA \u5c24\u5176\u5371\u9669：<\/p>\n
Buffer \u5730\u5740\u590d\u7528\u662f\u5e38\u6001\u3002\u9884\u5206\u914d\u7684 buffer pool \u672c\u5c31\u662f\u56fa\u5b9a\u5730\u5740\u96c6\u5408，pop \u51fa\u53bb\u7528\u5b8c\u53c8 push \u56de\u6765，\u5730\u5740\u5fc5\u7136\u91cd\u590d\u3002<\/p>\n<\/li>\n
\u65f6\u95f4\u7a97\u53e3\u5f88\u5927\u3002\u4e00\u4e2a buffer \u53ef\u80fd\u5728\u7f51\u7edc IO\u3001\u534f\u8bae\u89e3\u6790\u3001\u4e1a\u52a1\u903b\u8f91\u3001\u5e8f\u5217\u5316\u6574\u4e2a\u94fe\u8def\u4e0a\u6d41\u8f6c，\u4ece pop \u5230 push \u56de\u6765\u53ef\u80fd\u8de8\u8d8a\u6570\u6beb\u79d2\u2014\u2014\u8db3\u591f\u5176\u4ed6\u7ebf\u7a0b\u5728\u961f\u5217\u4e0a\u505a\u591a\u6b21\u64cd\u4f5c\u3002<\/p>\n<\/li>\n
\u540e\u679c\u4e0d\u662f crash，\u662f\u6570\u636e\u9519\u4e71\u3002\u961f\u5217\u7ed3\u6784\u88ab\u6084\u6084\u7834\u574f，\u540e\u7eed\u7684 pop \u53ef\u80fd\u8fd4\u56de\u9519\u8bef\u7684 buffer\u3001\u8df3\u8fc7 buffer\u3001\u751a\u81f3\u65e0\u9650\u5faa\u73af\u3002<\/p>\n<\/li>\n
\u6700\u7ecf\u5178\u7684 ABA \u89e3\u51b3\u65b9\u6848\u662f\u7ed9\u6307\u9488\u9644\u52a0\u4e00\u4e2a\u5355\u8c03\u9012\u589e\u7684\u7248\u672c\u53f7：<\/p>\n
C++<\/p>\n
\/\/ C++20, GCC 13\u3002Tagged pointer \u89e3\u51b3 ABA
\n\/\/ \u5229\u7528 x86-64 \u5730\u5740\u7a7a\u95f4\u53ea\u7528\u4f4e 48 \u4f4d，\u9ad8 16 \u4f4d\u53ef\u4ee5\u653e\u7248\u672c\u53f7
\n\/\/ \u6ce8\u610f：\u8fd9\u4e2a\u6280\u5de7\u5728\u6307\u9488\u538b\u7f29\u6216 5-level paging \u7684\u5185\u6838\u4e0a\u9700\u8981\u8c03\u6574<\/p>\n
struct TaggedPtr {
\n uintptr_t ptr : 48;
\n uintptr_t tag : 16; \/\/ \u7248\u672c\u53f7，\u6bcf\u6b21 CAS \u6210\u529f\u540e +1
\n};<\/p>\n
static_assert(sizeof(TaggedPtr) == 8);<\/p>\n
\/\/ CAS \u65f6\u6bd4\u8f83\u6574\u4e2a 64 \u4f4d（\u5305\u542b\u7248\u672c\u53f7），
\n\/\/ \u5373\u4f7f\u5730\u5740\u76f8\u540c\u3001\u7248\u672c\u53f7\u4e0d\u540c\u4e5f\u4f1a CAS \u5931\u8d25
\nstd::atomic<TaggedPtr> head_;<\/p>\n
bool pop(Node*& result) {
\n TaggedPtr old = head_.load(std::memory_order_acquire);
\n for (;;) {
\n if (old.ptr == 0) return false;
\n Node* node = reinterpret_cast<Node*>(old.ptr);
\n TaggedPtr next{reinterpret_cast<uintptr_t>(node->next), old.tag + 1};
\n if (head_.compare_exchange_weak(old, next,
\n std::memory_order_acq_rel, std::memory_order_acquire)) {
\n result = node;
\n return true;
\n }
\n \/\/ old \u5df2\u88ab\u5237\u65b0，\u91cd\u8bd5
\n }
\n}<\/p>\n
Tagged pointer \u5728\u5b9e\u8df5\u4e2d\u8db3\u591f\u597d\u2014\u201416 \u4f4d\u7248\u672c\u53f7\u610f\u5473\u7740\u8981 65536 \u6b21 ABA \u5de7\u5408\u624d\u4f1a\u8bef\u5224\u3002\u4f46\u5b83\u6709\u4e24\u4e2a\u9650\u5236：\u4e00\u662f\u4f9d\u8d56\u5e73\u53f0\u7279\u5b9a\u7684\u6307\u9488\u5e03\u5c40（x86-64 \u7684 48 \u4f4d\u5730\u5740\u7a7a\u95f4），\u53ef\u79fb\u690d\u6027\u5dee；\u4e8c\u662f\u5728 AArch64 \u4e0a\u4e5f\u53ef\u4ee5\u5229\u7528\u9ad8\u4f4d，\u4f46 Top Byte Ignore（TBI）\u548c Memory Tagging Extension（MTE）\u53ef\u80fd\u5360\u7528\u8fd9\u4e9b\u4f4d\u3002<\/p>\n
Hazard pointer \u662f Maged M. Michael \u5728 2004 \u5e74\u63d0\u51fa\u7684\u5b89\u5168\u56de\u6536\u65b9\u6848，\u5df2\u88ab\u63a5\u7eb3\u4e3a C++26 \u6807\u51c6（<hazard_pointer>, P2530）\u3002\u6838\u5fc3\u601d\u60f3：**\u7ebf\u7a0b\u5728\u8bbf\u95ee\u4e00\u4e2a\u5171\u4eab node \u4e4b\u524d，\u5148\u628a\u8fd9\u4e2a node \u7684\u5730\u5740\u201c\u516c\u544a\u201d\u5728\u81ea\u5df1\u7684 hazard pointer slot \u91cc；\u5176\u4ed6\u7ebf\u7a0b\u5728\u56de\u6536 node \u524d，\u5fc5\u987b\u626b\u63cf\u6240\u6709\u7ebf\u7a0b\u7684 hazard pointer，\u53ea\u6709\u6ca1\u4eba\u4fdd\u62a4\u7684 node \u624d\u80fd\u771f\u6b63\u91ca\u653e\u3002**<\/p>\n
C++<\/p>\n
\/\/ C++26 hazard_pointer \u6982\u5ff5\u793a\u610f（API \u4ee5 P2530R4 \u4e3a\u51c6）
\n\/\/ \u7b80\u5316\u5c55\u793a\u6838\u5fc3\u6d41\u7a0b<\/p>\n
void consumer_thread(LockFreeStack& stack) {
\n auto hp = std::make_hazard_pointer(); \/\/ \u83b7\u53d6\u4e00\u4e2a hazard pointer slot<\/p>\n
for (;;) {
\n Node* ptr;
\n do {
\n ptr = stack.head_.load(std::memory_order_acquire);
\n if (!ptr) break;
\n hp.protect(ptr); \/\/ \u516c\u544a：\u6211\u5728\u7528\u8fd9\u4e2a node
\n \/\/ \u91cd\u8bfb head，\u786e\u8ba4\u6ca1\u6709\u5728 protect \u4e4b\u524d\u5c31\u88ab\u522b\u4eba\u6539\u4e86
\n } while (ptr != stack.head_.load(std::memory_order_acquire));<\/p>\n
if (!ptr) continue;<\/p>\n
\/\/ \u73b0\u5728 ptr \u53d7\u4fdd\u62a4，\u5373\u4f7f\u522b\u7684\u7ebf\u7a0b pop \u4e86\u5b83\u4e5f\u4e0d\u4f1a\u91ca\u653e
\n \/\/ … \u4f7f\u7528 ptr …<\/p>\n
hp.reset_protection(); \/\/ \u7528\u5b8c\u4e86，\u53d6\u6d88\u4fdd\u62a4
\n }
\n}<\/p>\n
\/\/ \u56de\u6536\u7aef：\u628a retired \u7684 node \u653e\u8fdb\u5f85\u56de\u6536\u5217\u8868
\n\/\/ \u8fbe\u5230\u9608\u503c\u540e\u626b\u63cf\u6240\u6709 hazard pointer，\u53ea\u91ca\u653e\u6ca1\u4eba\u4fdd\u62a4\u7684
\nvoid retire_node(Node* node) {
\n node->retire(); \/\/ C++26: \u52a0\u5165\u7ebf\u7a0b\u672c\u5730\u7684 retired list
\n \/\/ \u5f53 retired list \u8db3\u591f\u957f\u65f6\u81ea\u52a8\u89e6\u53d1 scan + reclaim
\n}<\/p>\n
Hazard pointer \u7684\u4ee3\u4ef7\u662f\u6bcf\u6b21\u8bbf\u95ee\u90fd\u9700\u8981\u4e00\u4e2a atomic store（protect）\u548c\u4e00\u4e2a atomic load（\u9a8c\u8bc1），\u52a0\u4e0a\u56de\u6536\u65f6\u7684\u5168\u5c40\u626b\u63cf\u3002\u5728\u8bfb\u5bc6\u96c6\u573a\u666f\u4e0b\u8fd9\u4e2a\u5f00\u9500\u4e0d\u7b97\u5c0f\u2014\u2014\u6bcf\u6b21 protect \u81f3\u5c11\u4e00\u6b21 release store + \u4e00\u6b21 acquire load\u3002<\/p>\n
EBR \u662f\u4e00\u79cd\u66f4\u7c97\u7c92\u5ea6\u7684\u65b9\u6848：\u7ef4\u62a4\u4e00\u4e2a\u5168\u5c40 epoch \u8ba1\u6570\u5668（\u901a\u5e38\u662f 0\u30011\u30012 \u4e09\u4e2a\u503c\u5faa\u73af），\u6bcf\u4e2a\u7ebf\u7a0b\u8fdb\u5165\u201c\u4e34\u754c\u533a\u201d\u65f6\u8bb0\u5f55\u5f53\u524d epoch，\u9000\u51fa\u4e34\u754c\u533a\u65f6\u6e05\u9664\u3002\u56de\u6536\u903b\u8f91\u53ea\u5728\u786e\u8ba4\u6240\u6709\u7ebf\u7a0b\u90fd\u5df2\u7ecf\u79bb\u5f00\u65e7 epoch \u65f6\u624d\u91ca\u653e\u90a3\u4e2a epoch \u7684 retired node\u3002<\/p>\n
C++<\/p>\n
\/\/ Epoch-based reclamation \u6982\u5ff5\u793a\u610f
\n\/\/ C++20, GCC 13<\/p>\n
class EpochGuard {
\n thread_local static size_t local_epoch_;
\n static std::atomic<size_t> global_epoch_;
\n static thread_local std::vector<Node*> retired_[3]; \/\/ \u4e09\u4e2a epoch \u7684\u5f85\u56de\u6536\u5217\u8868<\/p>\n
public:
\n \/\/ \u8fdb\u5165\u4e34\u754c\u533a
\n void enter() {
\n local_epoch_ = global_epoch_.load(std::memory_order_acquire);
\n \/\/ \u6ce8\u610f：\u8fd9\u91cc\u9700\u8981\u4e00\u4e2a fence \u4fdd\u8bc1 local_epoch_ \u7684\u5199
\n \/\/ \u5bf9 epoch advancement \u903b\u8f91\u53ef\u89c1
\n }<\/p>\n
\/\/ \u79bb\u5f00\u4e34\u754c\u533a
\n void leave() {
\n \/\/ \u6807\u8bb0\u672c\u7ebf\u7a0b\u5df2\u7ecf\u4e0d\u5728\u4e34\u754c\u533a
\n \/\/ （\u5b9e\u73b0\u4e0a\u901a\u5e38\u662f\u628a local_epoch_ \u8bbe\u4e3a\u7279\u6b8a\u503c INACTIVE）
\n }<\/p>\n
\/\/ \u63a8\u8fdb epoch：\u5f53\u6240\u6709\u7ebf\u7a0b\u90fd\u5df2\u79bb\u5f00 old_epoch \u65f6\u624d\u80fd\u63a8\u8fdb
\n static void try_advance() {
\n size_t e = global_epoch_.load(std::memory_order_relaxed);
\n \/\/ \u626b\u63cf\u6240\u6709\u7ebf\u7a0b\u7684 local_epoch_
\n \/\/ \u5982\u679c\u6240\u6709\u7ebf\u7a0b\u8981\u4e48\u5728\u5f53\u524d epoch，\u8981\u4e48 INACTIVE
\n \/\/ \u2192 \u63a8\u8fdb epoch，\u56de\u6536 (e – 2) \u7684 retired list
\n }<\/p>\n
void retire(Node* node) {
\n retired_[local_epoch_ % 3].push_back(node);
\n if (retired_[local_epoch_ % 3].size() > threshold) {
\n try_advance();
\n }
\n }
\n};<\/p>\n
EBR \u7684\u8bfb\u7aef\u5f00\u9500\u6781\u4f4e\u2014\u2014\u8fdb\u5165\u4e34\u754c\u533a\u53ea\u662f\u4e00\u6b21 atomic load + \u4e00\u6b21\u7ebf\u7a0b\u5c40\u90e8\u5199，\u6ca1\u6709 per-object \u7684 atomic store\u3002\u4f46\u5b83\u6709\u4e00\u4e2a\u81f4\u547d\u5f31\u70b9：\u5982\u679c\u4efb\u4f55\u4e00\u4e2a\u7ebf\u7a0b\u5728\u4e34\u754c\u533a\u5185\u88ab\u963b\u585e（\u6bd4\u5982\u9677\u5165 page fault\u3001\u88ab\u8c03\u5ea6\u5668\u62a2\u5360\u3001\u6216\u8005\u5f00\u53d1\u8005\u4e0d\u5c0f\u5fc3\u5728\u4e34\u754c\u533a\u5185\u505a\u4e86\u963b\u585e IO），\u5168\u5c40 epoch \u5c31\u63a8\u4e0d\u52a8，\u6240\u6709 retired node \u90fd\u65e0\u6cd5\u56de\u6536，\u5185\u5b58\u65e0\u9650\u589e\u957f\u3002<\/p>\n
\u5bf9\u4e8e\u9884\u5206\u914d buffer pool + \u9ad8\u9891\u590d\u7528\u7684\u7f51\u7edc\u573a\u666f，\u6211\u503e\u5411\u4e8e：<\/p>\n
\u5982\u679c\u7528 SPSC ring buffer \u505a\u961f\u5217（\u540e\u6587\u4f1a\u5b9e\u73b0\u4e00\u4e2a）：SPSC \u5929\u7136\u6ca1\u6709 ABA \u95ee\u9898，\u56e0\u4e3a buffer \u5728 ring \u4e2d\u7684\u4f4d\u7f6e\u662f\u56fa\u5b9a\u7684，\u4e0d\u6d89\u53ca\u6307\u9488\u94fe\u8868\u3002\u8fd9\u662f\u6700\u5e72\u51c0\u7684\u65b9\u6848\u3002<\/p>\n<\/li>\n
\u5982\u679c\u5fc5\u987b\u7528\u94fe\u8868\u5f0f\u65e0\u9501\u6808\u7ba1\u7406 buffer pool：\u7528 tagged pointer\u3002\u7f51\u7edc buffer \u7684\u5730\u5740\u7a7a\u95f4\u901a\u5e38\u662f\u9884\u5206\u914d\u7684\u56fa\u5b9a\u5927\u5c0f，16 \u4f4d\u7248\u672c\u53f7\u8db3\u591f\u3002<\/p>\n<\/li>\n
\u5982\u679c buffer \u7684\u751f\u547d\u5468\u671f\u8de8\u8d8a\u591a\u4e2a\u9636\u6bb5（\u6536\u5305 \u2192 \u89e3\u6790 \u2192 \u5904\u7406 \u2192 \u5f52\u8fd8）：\u7528 hazard pointer\u3002EBR \u5728\u7f51\u7edc\u573a\u666f\u4e0b\u98ce\u9669\u5927\u2014\u2014worker \u7ebf\u7a0b\u53ef\u80fd\u5728\u5904\u7406\u67d0\u4e2a\u8bf7\u6c42\u65f6\u505a\u4e86\u4e00\u6b21 DNS \u67e5\u8be2\u6216\u8fdc\u7a0b\u8c03\u7528，\u963b\u585e\u4e86\u51e0\u767e\u6beb\u79d2，\u6574\u4e2a epoch \u63a8\u4e0d\u52a8\u3002<\/p>\n<\/li>\n
\u4f46\u5148\u522b\u6025\u7740\u9009\u65b9\u6848\u3002\u771f\u6b63\u7684\u5de5\u7a0b\u5efa\u8bae\u662f：\u5148\u770b\u4f60\u5230\u5e95\u9700\u4e0d\u9700\u8981\u94fe\u8868\u3002\u5982\u679c\u961f\u5217\u662f bounded \u7684（\u7f51\u7edc\u573a\u666f\u51e0\u4e4e\u90fd\u662f），\u7528 ring buffer \u5c31\u5b8c\u5168\u907f\u5f00\u4e86 ABA \u548c\u5185\u5b58\u56de\u6536\u7684\u5168\u90e8\u590d\u6742\u5ea6\u3002<\/p>\n
\u5230\u8fd9\u91cc\u8be5\u7ed9\u5b8c\u6574\u7684\u4ee3\u7801\u4e86\u3002\u8fd9\u662f\u4e00\u4e2a\u53ef\u79fb\u690d\u7684 SPSC ring buffer，\u5173\u952e\u8bbe\u8ba1\u70b9：\u6b63\u786e\u7684 acquire\/release \u6620\u5c04\u3001cache line padding \u907f\u514d false sharing\u3001power-of-two \u5bb9\u91cf\u7528\u4f4d\u8fd0\u7b97\u4ee3\u66ff\u53d6\u6a21\u3001\u672c\u5730\u7f13\u5b58\u5bf9\u7aef\u6307\u9488\u51cf\u5c11\u8de8\u6838 cache line \u8bfb\u53d6\u3002<\/p>\n
C++<\/p>\n
\/\/ spsc_ring.hpp
\n\/\/ C++20, GCC 13 \/ Clang 17, \u53ef\u79fb\u690d\u5230 x86-64 \u548c AArch64
\n\/\/ \u53c2\u8003 rigtorp\/SPSCQueue \u7684\u6838\u5fc3\u601d\u8def，\u505a\u4e86\u7b80\u5316\u548c\u6ce8\u91ca
\n\/\/ License: MIT (\u793a\u4f8b\u4ee3\u7801)<\/p>\n
#pragma once
\n#include <atomic>
\n#include <cassert>
\n#include <cstddef>
\n#include <new> \/\/ std::hardware_destructive_interference_size
\n#include <type_traits><\/p>\n
\/\/ cache line \u5927\u5c0f：C++17 \u5f15\u5165\u4e86 hardware_destructive_interference_size，
\n\/\/ \u4f46\u622a\u81f3 GCC 13 \u548c Clang 17 \u5f88\u591a\u5e73\u53f0\u4e0a\u5b83\u8fd8\u662f constexpr \u672a\u5b9a\u4e49\u6216\u9700\u8981
\n\/\/ -Wno-interference-size\u3002\u8fd9\u91cc\u7528 64 \u4f5c\u4e3a\u4fdd\u5b88\u503c（\u8986\u76d6 x86 \u548c ARM \u4e3b\u6d41 CPU）
\n#ifndef CACHE_LINE_SIZE
\n#define CACHE_LINE_SIZE 64
\n#endif<\/p>\n
template<typename T>
\nclass SPSCRing {
\n static_assert(std::is_nothrow_move_constructible_v<T> ||
\n std::is_nothrow_copy_constructible_v<T>,
\n "T must be nothrow move or copy constructible");<\/p>\n
public:
\n \/\/ capacity \u5fc5\u987b\u662f 2 \u7684\u5e42，\u65b9\u4fbf\u7528 & (capacity_ – 1) \u4ee3\u66ff % capacity_
\n explicit SPSCRing(size_t capacity)
\n : capacity_(capacity)
\n , mask_(capacity – 1)
\n , buffer_(static_cast<T*>(
\n ::operator new(sizeof(T) * capacity, std::align_val_t{CACHE_LINE_SIZE})))
\n {
\n assert(capacity >= 2 && (capacity & (capacity – 1)) == 0
\n && "capacity must be a power of two");
\n }<\/p>\n
~SPSCRing() {
\n \/\/ \u6790\u6784\u672a\u6d88\u8d39\u7684\u5143\u7d20
\n size_t h = head_.load(std::memory_order_relaxed);
\n size_t t = tail_.load(std::memory_order_relaxed);
\n while (h != t) {
\n buffer_[h & mask_].~T();
\n ++h;
\n }
\n ::operator delete(buffer_, std::align_val_t{CACHE_LINE_SIZE});
\n }<\/p>\n
\/\/ \u7981\u6b62\u62f7\u8d1d\u548c\u79fb\u52a8（\u6307\u9488\u548c\u539f\u5b50\u72b6\u6001\u4e0d\u53ef\u5b89\u5168\u8f6c\u79fb）
\n SPSCRing(const SPSCRing&) = delete;
\n SPSCRing& operator=(const SPSCRing&) = delete;<\/p>\n
\/\/ === \u751f\u4ea7\u8005\u7aef ===
\n \/\/ \u8c03\u7528\u65b9\u4fdd\u8bc1：\u53ea\u6709\u4e00\u4e2a\u7ebf\u7a0b\u8c03\u7528 push
\n template<typename U>
\n bool push(U&& val) {
\n size_t t = tail_.load(std::memory_order_relaxed);<\/p>\n
\/\/ \u5148\u67e5\u672c\u5730\u7f13\u5b58\u7684 head，\u907f\u514d\u4e0d\u5fc5\u8981\u7684\u8de8\u6838 cache line \u8bfb\u53d6
\n if (t – cached_head_ >= capacity_) {
\n \/\/ \u672c\u5730\u7f13\u5b58\u8bf4"\u6ee1\u4e86"，\u4f46\u53ef\u80fd\u6d88\u8d39\u8005\u5df2\u7ecf\u63a8\u8fdb\u4e86 head
\n cached_head_ = head_.load(std::memory_order_acquire);
\n if (t – cached_head_ >= capacity_) {
\n return false; \/\/ \u771f\u7684\u6ee1\u4e86
\n }
\n }<\/p>\n
\/\/ \u6784\u9020\u5143\u7d20\u5230 buffer \u4e2d
\n new (&buffer_[t & mask_]) T(std::forward<U>(val));<\/p>\n
\/\/ \u5173\u952e：release store \u53d1\u5e03 tail
\n \/\/ \u4fdd\u8bc1\u4e0a\u9762\u7684\u6784\u9020\u64cd\u4f5c\u5728\u6b64 store \u4e4b\u524d\u5bf9\u6d88\u8d39\u8005\u53ef\u89c1
\n tail_.store(t + 1, std::memory_order_release);
\n return true;
\n }<\/p>\n
\/\/ === \u6d88\u8d39\u8005\u7aef ===
\n \/\/ \u8c03\u7528\u65b9\u4fdd\u8bc1：\u53ea\u6709\u4e00\u4e2a\u7ebf\u7a0b\u8c03\u7528 pop
\n bool pop(T& val) {
\n size_t h = head_.load(std::memory_order_relaxed);<\/p>\n
\/\/ \u5148\u67e5\u672c\u5730\u7f13\u5b58\u7684 tail
\n if (h == cached_tail_) {
\n cached_tail_ = tail_.load(std::memory_order_acquire);
\n if (h == cached_tail_) {
\n return false; \/\/ \u771f\u7684\u7a7a
\n }
\n }<\/p>\n
\/\/ \u8bfb\u53d6\u5e76\u79fb\u52a8\u5143\u7d20
\n val = std::move(buffer_[h & mask_]);
\n buffer_[h & mask_].~T();<\/p>\n
\/\/ \u5173\u952e：release store \u53d1\u5e03 head
\n \/\/ \u4fdd\u8bc1\u4e0a\u9762\u7684\u6790\u6784\u64cd\u4f5c\u5728\u6b64 store \u4e4b\u524d\u5b8c\u6210
\n \/\/ （\u5426\u5219\u751f\u4ea7\u8005\u53ef\u80fd\u5728\u6d88\u8d39\u8005\u8fd8\u6ca1\u8bfb\u5b8c\u65f6\u5c31\u8986\u5199\u8fd9\u4e2a slot）
\n head_.store(h + 1, std::memory_order_release);
\n return true;
\n }<\/p>\n
size_t size_approx() const {
\n \/\/ \u8fd1\u4f3c\u5927\u5c0f，\u4e0d\u4fdd\u8bc1\u7cbe\u786e（head \u548c tail \u7684\u8bfb\u53d6\u4e0d\u662f\u539f\u5b50\u7684\u4e00\u5bf9）
\n return tail_.load(std::memory_order_relaxed)
\n – head_.load(std::memory_order_relaxed);
\n }<\/p>\n
private:
\n const size_t capacity_;
\n const size_t mask_;
\n T* const buffer_;<\/p>\n
\/\/ \u2500\u2500\u2500 Cache Line \u9694\u79bb \u2500\u2500\u2500
\n \/\/ head_ \u53ea\u88ab\u6d88\u8d39\u8005\u5199\u3001\u88ab\u751f\u4ea7\u8005\u8bfb（\u901a\u8fc7 cached_head_ \u51cf\u5c11\u9891\u7387）
\n \/\/ tail_ \u53ea\u88ab\u751f\u4ea7\u8005\u5199\u3001\u88ab\u6d88\u8d39\u8005\u8bfb（\u901a\u8fc7 cached_tail_ \u51cf\u5c11\u9891\u7387）
\n \/\/ \u628a\u5b83\u4eec\u653e\u5728\u4e0d\u540c\u7684 cache line \u4e0a，\u907f\u514d false sharing<\/p>\n
\/\/ \u751f\u4ea7\u8005\u72ec\u5360\u7684 cache line
\n alignas(CACHE_LINE_SIZE) std::atomic<size_t> tail_{0};
\n size_t cached_head_{0}; \/\/ \u751f\u4ea7\u8005\u672c\u5730\u7f13\u5b58\u7684 head \u503c<\/p>\n
\/\/ \u6d88\u8d39\u8005\u72ec\u5360\u7684 cache line
\n alignas(CACHE_LINE_SIZE) std::atomic<size_t> head_{0};
\n size_t cached_tail_{0}; \/\/ \u6d88\u8d39\u8005\u672c\u5730\u7f13\u5b58\u7684 tail \u503c<\/p>\n
\/\/ padding \u5230\u4e0b\u4e00\u4e2a cache line \u8fb9\u754c，\u9632\u6b62 buffer \u540e\u9762\u7684\u5176\u4ed6\u5bf9\u8c61\u8bef\u5165
\n char pad_[CACHE_LINE_SIZE – sizeof(std::atomic<size_t>) – sizeof(size_t)];
\n};<\/p>\n
\u8fd9\u6bb5\u4ee3\u7801\u6709\u51e0\u4e2a\u5173\u952e\u8bbe\u8ba1\u51b3\u7b56\u503c\u5f97\u9010\u4e00\u62c6\u89e3\u3002<\/p>\n
buffer_[t % capacity]\u00a0\u7684\u53d6\u6a21\u8fd0\u7b97\u5728 x86 \u4e0a\u7f16\u8bd1\u6210\u00a0div\u00a0\u6216\u00a0idiv，\u5ef6\u8fdf\u7ea6 30-40 \u4e2a\u5468\u671f\u3002buffer_[t & mask_]\u00a0\u7684\u4f4d\u4e0e\u8fd0\u7b97\u7f16\u8bd1\u6210\u00a0and，\u5ef6\u8fdf 1 \u4e2a\u5468\u671f\u3002\u5728\u6bcf\u79d2\u51e0\u4ebf\u6b21\u7684\u5165\u961f\u51fa\u961f\u64cd\u4f5c\u4e2d，\u8fd9\u4e2a\u5dee\u5f02\u662f\u663e\u8457\u7684\u3002rigtorp\/SPSCQueue \u548c Folly \u7684 ProducerConsumerQueue \u90fd\u5f3a\u5236 power-of-two \u5bb9\u91cf\u3002<\/p>\n
false sharing \u662f SPSC ring \u6700\u5927\u7684\u6027\u80fd\u6740\u624b\u3002\u5982\u679c\u00a0head_\u00a0\u548c\u00a0tail_\u00a0\u5728\u540c\u4e00\u6761 cache line \u4e0a，\u6d88\u8d39\u8005\u6bcf\u6b21\u66f4\u65b0\u00a0head_\u00a0\u90fd\u4f1a\u8ba9\u751f\u4ea7\u8005\u6838\u5fc3\u7684\u00a0tail_\u00a0\u6240\u5728 cache line \u5931\u6548，\u53cd\u4e4b\u4ea6\u7136\u3002\u4e24\u4e2a\u6838\u5fc3\u4ea4\u66ff\u5730\u628a\u540c\u4e00\u6761 cache line \u62c9\u6765\u62c9\u53bb\u2014\u2014\u8fd9\u5c31\u662f false sharing，\u4e5f\u53eb"cache line ping-pong"\u3002<\/p>\n
\u89e3\u51b3\u65b9\u6848\u662f\u7528\u00a0alignas(CACHE_LINE_SIZE)\u00a0\u628a\u00a0head_\u00a0\u548c\u00a0tail_\u00a0\u653e\u5728\u4e0d\u540c\u7684 cache line \u4e0a\u3002\u4f46\u5149\u9694\u79bb\u8fd9\u4e24\u4e2a\u539f\u5b50\u53d8\u91cf\u8fd8\u4e0d\u591f\u2014\u2014cached_head_\u00a0\u548c\u00a0cached_tail_\u00a0\u4e5f\u8981\u8ddf\u5bf9\u5e94\u7684\u539f\u5b50\u53d8\u91cf\u653e\u5728\u540c\u4e00\u6761 cache line \u4e0a：<\/p>\n
text<\/p>\n
Cache Line 0: [tail_ | cached_head_ | padding…] \u2190 \u751f\u4ea7\u8005\u72ec\u5360
\nCache Line 1: [head_ | cached_tail_ | padding…] \u2190 \u6d88\u8d39\u8005\u72ec\u5360<\/p>\n
cached_head_\u00a0\u53ea\u88ab\u751f\u4ea7\u8005\u8bfb\u5199，\u6240\u4ee5\u5b83\u8ddf\u00a0tail_（\u4e5f\u53ea\u88ab\u751f\u4ea7\u8005\u5199）\u653e\u540c\u4e00\u6761 cache line \u6ca1\u95ee\u9898\u2014\u2014\u90fd\u662f\u540c\u4e00\u4e2a\u6838\u5fc3\u5728\u64cd\u4f5c，\u4e0d\u4f1a ping-pong\u3002cached_tail_\u00a0\u540c\u7406\u3002<\/p>\n
\u8fd9\u662f rigtorp\/SPSCQueue \u76f8\u5bf9\u4e8e\u6734\u7d20\u5b9e\u73b0\u6027\u80fd\u63d0\u5347\u6700\u5927\u7684\u4e00\u4e2a\u6280\u5de7\u3002<\/p>\n
\u6734\u7d20\u5b9e\u73b0\u4e2d，\u751f\u4ea7\u8005\u6bcf\u6b21 push \u90fd\u8981\u505a\u00a0head_.load(acquire)\u00a0\u6765\u68c0\u67e5\u961f\u5217\u662f\u5426\u6ee1：\u8fd9\u610f\u5473\u7740**\u6bcf\u6b21 push \u90fd\u8981\u8de8\u6838\u8bfb\u53d6\u6d88\u8d39\u8005\u7684\u00a0head_，\u89e6\u53d1\u4e00\u6b21 cache line \u4f20\u8f93**\u3002\u5982\u679c\u751f\u4ea7\u8005\u548c\u6d88\u8d39\u8005\u5728\u4e0d\u540c\u7684\u6838\u5fc3\u4e0a（\u901a\u5e38\u5982\u6b64），\u8fd9\u4e00\u6b21\u8de8\u6838\u8bfb\u53d6\u7684\u5ef6\u8fdf\u662f 40-100 \u4e2a\u5468\u671f\u3002<\/p>\n
\u672c\u5730\u7f13\u5b58\u7684\u505a\u6cd5\u662f：\u751f\u4ea7\u8005\u628a\u4e0a\u6b21\u8bfb\u5230\u7684\u00a0head_\u00a0\u503c\u5b58\u5728\u81ea\u5df1\u7684\u00a0cached_head_\u00a0\u91cc（\u4e0d\u662f atomic，\u4e0d\u9700\u8981\u8de8\u6838\u53ef\u89c1）\u3002push \u65f6\u5148\u7528\u00a0cached_head_\u00a0\u68c0\u67e5\u2014\u2014\u5982\u679c\u6309\u7f13\u5b58\u7684\u503c\u961f\u5217\u8fd8\u6ca1\u6ee1，\u76f4\u63a5\u8df3\u8fc7\u8de8\u6838\u8bfb\u53d6\u3002\u53ea\u6709\u5f53\u7f13\u5b58\u503c\u663e\u793a\u201c\u6ee1\u4e86\u201d\u65f6，\u624d\u771f\u6b63\u53bb\u8bfb\u4e00\u6b21\u00a0head_.load(acquire)，\u66f4\u65b0\u7f13\u5b58\u3002<\/p>\n
\u8fd9\u610f\u5473\u7740：**\u5982\u679c\u961f\u5217\u4e0d\u5e38\u6ee1（\u7f51\u7edc\u573a\u666f\u4e2d\u901a\u5e38\u5982\u6b64），\u751f\u4ea7\u8005\u53ef\u80fd\u8fde\u7eed push \u51e0\u5343\u6b21\u90fd\u4e0d\u9700\u8981\u8bfb\u4e00\u6b21\u00a0head_\u3002** \u8de8\u6838 cache line \u4f20\u8f93\u4ece\u201c\u6bcf\u6b21 push \u4e00\u6b21\u201d\u964d\u5230\u4e86\u201c\u961f\u5217\u5feb\u6ee1\u65f6\u624d\u4e00\u6b21\u201d\u3002<\/p>\n
\u6d88\u8d39\u8005\u7aef\u5bf9\u00a0tail_\u00a0\u505a\u540c\u6837\u7684\u7f13\u5b58\u3002<\/p>\n
\u6211\u7528\u00a0perf stat\u00a0\u5bf9\u6bd4\u8fc7\u6709\u65e0\u672c\u5730\u7f13\u5b58\u7684\u7248\u672c（GCC 13, -O2, Intel Xeon Gold 6348，\u4e24\u4e2a\u7ebf\u7a0b\u5206\u522b\u7ed1\u5b9a\u5230\u4e0d\u540c\u6838\u5fc3，\u961f\u5217\u5bb9\u91cf 65536，\u8fde\u7eed push\/pop 1 \u4ebf\u6761 64 \u5b57\u8282\u6d88\u606f）：<\/p>\n
text<\/p>\n
\u65e0\u7f13\u5b58\u7248 \u6709\u7f13\u5b58\u7248
\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500
\nL1-dcache-load-misses ~45M ~2.1M
\nLLC-load-misses ~12M ~0.4M
\nops\/sec ~180M ~320M<\/p>\n
cache miss \u6570\u91cf\u964d\u4e86\u4e00\u4e2a\u6570\u91cf\u7ea7\u4ee5\u4e0a，\u541e\u5410\u51e0\u4e4e\u7ffb\u500d\u3002<\/p>\n
\u56de\u987e\u4e00\u4e0b\u6bcf\u4e2a\u539f\u5b50\u64cd\u4f5c\u7684 memory order：<\/p>\n
| \n tail_.load()\u00a0\u751f\u4ea7\u8005\u81ea\u5df1\u8bfb tail<\/p>\n<\/td>\n | \n relaxed<\/p>\n<\/td>\n | \n \u53ea\u6709\u81ea\u5df1\u5199 tail，\u8bfb\u81ea\u5df1\u7684\u503c\u4e0d\u9700\u8981\u540c\u6b65<\/p>\n<\/td>\n<\/tr>\n |
| \n head_.load()\u00a0\u751f\u4ea7\u8005\u8bfb\u6d88\u8d39\u8005\u7684 head<\/p>\n<\/td>\n | \n acquire<\/p>\n<\/td>\n | \n \u9700\u8981\u770b\u5230\u6d88\u8d39\u8005\u5728\u00a0head_.store(release)\u00a0\u4e4b\u524d\u505a\u7684\u6790\u6784<\/p>\n<\/td>\n<\/tr>\n |
| \n tail_.store()\u00a0\u751f\u4ea7\u8005\u53d1\u5e03 tail<\/p>\n<\/td>\n | \n release<\/p>\n<\/td>\n | \n \u4fdd\u8bc1 buffer \u7684\u6784\u9020\u5bf9\u6d88\u8d39\u8005\u53ef\u89c1<\/p>\n<\/td>\n<\/tr>\n |
| \n head_.load()\u00a0\u6d88\u8d39\u8005\u81ea\u5df1\u8bfb head<\/p>\n<\/td>\n | \n relaxed<\/p>\n<\/td>\n | \n \u53ea\u6709\u81ea\u5df1\u5199 head<\/p>\n<\/td>\n<\/tr>\n |
| \n tail_.load()\u00a0\u6d88\u8d39\u8005\u8bfb\u751f\u4ea7\u8005\u7684 tail<\/p>\n<\/td>\n | \n acquire<\/p>\n<\/td>\n | \n \u9700\u8981\u770b\u5230\u751f\u4ea7\u8005\u5728\u00a0tail_.store(release)\u00a0\u4e4b\u524d\u505a\u7684\u6784\u9020<\/p>\n<\/td>\n<\/tr>\n |
| \n head_.store()\u00a0\u6d88\u8d39\u8005\u53d1\u5e03 head<\/p>\n<\/td>\n | \n release<\/p>\n<\/td>\n | \n \u4fdd\u8bc1 buffer \u7684\u6790\u6784\u5b8c\u6210\u540e\u518d\u8ba9\u751f\u4ea7\u8005\u770b\u5230\u7a7a\u51fa\u7684 slot<\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n \u6ca1\u6709\u4efb\u4f55\u5730\u65b9\u9700\u8981\u00a0seq_cst\u3002\u6bcf\u4e00\u4e2a memory order \u90fd\u6709\u7cbe\u786e\u7684\u7406\u7531\u2014\u2014\u4e0d\u662f\u201c\u4e3a\u4e86\u5b89\u5168\u201d\u800c\u5347\u7ea7，\u4e5f\u4e0d\u662f\u201c\u4e3a\u4e86\u6027\u80fd\u201d\u800c\u964d\u7ea7\u3002<\/p>\n \u8fd9\u4e2a\u5b9e\u73b0\u7684\u5c40\u9650\u6027（\u53cd\u8bc1\u81ea\u5df1\u7684\u65b9\u6848）<\/h4>\n\u8fd9\u4e2a SPSC ring \u4e0d\u662f\u4e07\u80fd\u7684：<\/p>\n \u56fa\u5b9a\u5bb9\u91cf\u3002\u5982\u679c\u6d88\u8d39\u8005\u5904\u7406\u901f\u5ea6\u8ddf\u4e0d\u4e0a\u751f\u4ea7\u8005，push \u8fd4\u56de false，\u751f\u4ea7\u8005\u5fc5\u987b\u81ea\u5df1\u5904\u7406\u80cc\u538b（\u4e22\u5f03\u3001\u963b\u585e\u7b49\u5f85\u3001\u6216\u8005\u56de\u9000\u5230\u66f4\u5927\u7684\u961f\u5217）\u3002\u52a8\u6001\u6269\u5bb9\u7684\u65e0\u9501\u961f\u5217\u5b58\u5728\u4f46\u590d\u6742\u5f97\u591a，\u4e14\u4f1a\u5931\u53bb cache line padding \u7684\u7cbe\u786e\u63a7\u5236\u3002<\/p>\n<\/li>\n \u5bb9\u91cf\u5fc5\u987b\u662f 2 \u7684\u5e42\u3002\u5982\u679c\u4f60\u7684\u6700\u4f73\u5bb9\u91cf\u6070\u597d\u662f 1000，\u4f60\u5f97\u5411\u4e0a\u53d6\u5230 1024，\u6d6a\u8d39 2.4% \u7684\u7a7a\u95f4\u3002\u5bf9\u4e8e\u5927\u578b buffer（\u6bd4\u5982\u6bcf\u4e2a slot \u662f 4KB \u7684\u7f51\u7edc buffer），\u6d6a\u8d39\u91cf\u4e0d\u53ef\u5ffd\u7565\u3002<\/p>\n<\/li>\n \u4e0d\u652f\u6301\u6279\u91cf\u64cd\u4f5c\u3002\u9ad8\u541e\u5410\u573a\u666f\u4e0b，\u4e00\u6b21 push\/pop \u4e00\u4e2a\u5143\u7d20\u7684\u63a5\u53e3\u4f1a\u56e0\u4e3a function call overhead \u548c\u00a0tail_\/head_\u00a0\u7684\u9891\u7e41\u539f\u5b50\u64cd\u4f5c\u800c\u6210\u4e3a\u74f6\u9888\u3002\u66f4\u597d\u7684\u63a5\u53e3\u662f\u00a0push_batch(T*, size_t)\u00a0\/\u00a0pop_batch(T*, size_t)，\u4e00\u6b21\u66f4\u65b0\u6307\u9488\u3001\u644a\u8584\u539f\u5b50\u64cd\u4f5c\u5f00\u9500\u3002<\/p>\n<\/li>\n \u6790\u6784\u7684\u4f4d\u7f6e\u3002\u5f53\u524d\u5b9e\u73b0\u5728\u00a0pop\u00a0\u5185\u90e8\u505a\u00a0buffer_[h & mask_].~T()，\u5982\u679c T \u7684\u6790\u6784\u51fd\u6570\u629b\u5f02\u5e38（\u867d\u7136\u4e0d\u5e94\u8be5），head_\u00a0\u5df2\u7ecf\u66f4\u65b0\u4e86\u4f46\u5143\u7d20\u6ca1\u88ab\u6b63\u786e\u6790\u6784\u3002noexcept\u00a0\u7684\u00a0static_assert\u00a0\u53ea\u68c0\u67e5\u4e86\u6784\u9020，\u6790\u6784\u4e5f\u5e94\u8be5\u68c0\u67e5\u3002<\/p>\n<\/li>\n \n \u7f16\u8bd1\u5668\u4e0e\u786c\u4ef6\u7684\u5408\u8c0b：\u4e3a\u4ec0\u4e48 volatile \u6551\u4e0d\u4e86\u4f60<\/h3>\n\u5199\u5230\u8fd9\u91cc，\u5fc5\u987b\u6b63\u9762\u56de\u5e94\u4e00\u4e2a\u6301\u7eed\u4e86\u4e8c\u5341\u5e74\u7684\u9519\u8bef\u505a\u6cd5：**\u7528\u00a0volatile\u00a0\u505a\u7ebf\u7a0b\u540c\u6b65**\u3002<\/p>\n volatile\u00a0\u7684\u8bed\u4e49\u662f\u201c\u6bcf\u6b21\u8bfb\u5199\u90fd\u771f\u6b63\u53bb\u5185\u5b58\u505a，\u4e0d\u8981\u7f13\u5b58\u5728\u5bc4\u5b58\u5668\u91cc\u201d\u3002\u5b83\u5bf9\u4ed8\u7684\u662f**\u7f16\u8bd1\u5668\u4f18\u5316**\u2014\u2014\u963b\u6b62\u7f16\u8bd1\u5668\u628a\u591a\u6b21\u8bfb\u5408\u5e76\u6210\u4e00\u6b21\u3001\u628a\u6ca1\u88ab\u540e\u7eed\u4ee3\u7801\u5f15\u7528\u7684\u5199\u5220\u9664\u3002\u4f46\u5b83\u5b8c\u5168\u4e0d\u5904\u7406\u4e24\u4e2a\u95ee\u9898：<\/p>\n CPU \u6307\u4ee4\u91cd\u6392\u3002volatile\u00a0\u4e0d\u751f\u6210\u4efb\u4f55\u786c\u4ef6\u5c4f\u969c\u6307\u4ee4\u3002ARM CPU \u53ef\u4ee5\u628a\u00a0volatile\u00a0\u5199\u91cd\u6392\u5230\u540e\u7eed\u7684\u00a0volatile\u00a0\u8bfb\u4e4b\u524d\u3002<\/p>\n<\/li>\n store buffer \u53ef\u89c1\u6027\u3002CPU \u7684 store buffer \u53ef\u80fd\u5ef6\u8fdf\u00a0volatile\u00a0\u5199\u5bf9\u5176\u4ed6\u6838\u5fc3\u7684\u53ef\u89c1\u6027\u3002<\/p>\n<\/li>\n C++<\/p>\n \/\/ \u9519\u8bef\u793a\u8303：\u7528 volatile \u505a SPSC \u540c\u6b65 \/\/ \u751f\u4ea7\u8005 \/\/ \u6d88\u8d39\u8005 \u5728 x86 \u4e0a\u8fd9\u6bb5\u4ee3\u7801\u201c\u78b0\u5de7\u6b63\u786e\u201d\u2014\u2014TSO \u4fdd\u8bc1\u4e86 StoreStore \u987a\u5e8f\u3002\u5728 ARM \u4e0a，volatile\u00a0\u5199\u7f16\u8bd1\u6210\u666e\u901a\u00a0STR，CPU \u6709\u6743\u91cd\u6392\u3002<\/p>\n \u66f4\u7cdf\u7cd5\u7684\u662f，volatile\u00a0\u548c\u00a0std::atomic\u00a0\u6df7\u7528\u4f1a\u5bfc\u81f4\u7f16\u8bd1\u5668\u65e0\u6cd5\u63a8\u7406\u5185\u5b58\u6a21\u578b，\u4ea7\u751f\u5fae\u5999\u7684 bug\u3002C++ \u6807\u51c6\u660e\u786e\u6307\u51fa（[intro.races] \u00a76.9.2.1）：volatile\u00a0\u4e0d\u6784\u6210\u7ebf\u7a0b\u95f4\u7684 happens-before \u5173\u7cfb\u3002<\/p>\n **\u7ed3\u8bba：\u5728 C++11 \u4e4b\u540e，volatile\u00a0\u5728\u591a\u7ebf\u7a0b\u540c\u6b65\u573a\u666f\u4e2d\u6ca1\u6709\u4efb\u4f55\u5408\u6cd5\u7528\u9014\u3002** \u5b83\u552f\u4e00\u7684\u6b63\u5f53\u7528\u9014\u662f\u5185\u5b58\u6620\u5c04 I\/O（MMIO），\u5bf9\u4ed8\u7684\u662f\u786c\u4ef6\u5bc4\u5b58\u5668，\u4e0d\u662f\u7ebf\u7a0b\u3002<\/p>\n \n seq_cst \u7684\u771f\u5b9e\u4ee3\u4ef7：x86 \u4e0e ARM \u7684\u975e\u5bf9\u79f0\u5f71\u54cd<\/h3>\n\u524d\u9762\u8bf4\u4e86\u201c\u5927\u591a\u6570\u65e0\u9501\u961f\u5217\u4e0d\u9700\u8981 seq_cst\u201d，\u4f46\u5230\u5e95\u8d35\u591a\u5c11？<\/p>\n \u5728 x86 \u4e0a，seq_cst store \u9700\u8981\u4e00\u6761\u00a0MFENCE\u00a0\u6216\u8005\u7528\u00a0LOCK XCHG\u00a0\u4ee3\u66ff\u666e\u901a\u00a0MOV\u3002MFENCE\u00a0\u5728 Skylake \u67b6\u6784\u4e0a\u7684\u5ef6\u8fdf\u7ea6 33 \u4e2a\u5468\u671f（Intel Optimization Manual），\u800c\u4e14\u5b83\u4f1a flush store buffer\u3001stall \u6d41\u6c34\u7ebf\u3002\u4f46 seq_cst load \u5728 x86 \u4e0a\u662f\u514d\u8d39\u7684\u2014\u2014\u8ddf acquire load \u751f\u6210\u5b8c\u5168\u76f8\u540c\u7684\u00a0MOV\u3002<\/p>\n \u5728 ARM \u4e0a，seq_cst \u7684\u4ee3\u4ef7\u66f4\u4e0d\u5bf9\u79f0\u3002seq_cst store\u00a0\u7f16\u8bd1\u6210\u00a0STLR（\u8ddf release \u4e00\u6837），\u4f46\u00a0seq_cst load\u00a0\u53ef\u80fd\u9700\u8981\u5728\u00a0LDAR\u00a0\u4e4b\u540e\u989d\u5916\u63d2\u5165\u4e00\u6761\u00a0DMB ISH（Data Memory Barrier, Inner Shareable），\u4ee5\u4fdd\u8bc1\u5168\u5e8f\u3002\u5177\u4f53\u53d6\u51b3\u4e8e\u7f16\u8bd1\u5668\u548c\u4e0a\u4e0b\u6587\u2014\u2014GCC 13 \u5728\u67d0\u4e9b\u60c5\u51b5\u4e0b\u4f1a\u4f18\u5316\u6389\u8fd9\u4e2a\u00a0DMB，\u4f46\u4e0d\u4fdd\u8bc1\u3002<\/p>\n \u4e00\u6b21\u00a0DMB ISH\u00a0\u5728 Cortex-A78（Graviton3 \u4f7f\u7528\u7684\u6838\u5fc3）\u4e0a\u5927\u7ea6 30-50 \u4e2a\u5468\u671f，\u800c\u4e14\u5b83\u4f1a stall \u6574\u4e2a\u6d41\u6c34\u7ebf\u76f4\u5230\u4e4b\u524d\u7684\u6240\u6709\u5185\u5b58\u64cd\u4f5c\u90fd\u5b8c\u6210\u3002\u5728\u9ad8\u9891\u5faa\u73af\u4e2d（\u6bd4\u5982\u65e0\u9501\u961f\u5217\u7684 CAS \u81ea\u65cb），\u8fd9\u4e2a\u4ee3\u4ef7\u4f1a\u53e0\u52a0\u3002<\/p>\n \u56de\u5230\u90a3\u4e2a benchmark：SPSC ring buffer，\u5bb9\u91cf 65536，GCC 13 -O2，1 \u4ebf\u6b21\u64cd\u4f5c\u3002<\/p>\n text<\/p>\n x86-64 (Xeon Gold 6348) AArch64 (Graviton3) x86 \u4e0a\u4ece seq_cst \u6362\u5230 acquire\/release \u53ea\u5feb\u4e86\u7ea6 6%（\u56e0\u4e3a\u4e3b\u8981\u5dee\u5f02\u53ea\u5728 store \u7aef\u7684\u00a0MFENCE）\u3002ARM \u4e0a\u5feb\u4e86\u7ea6 22%\u2014\u2014\u56e0\u4e3a ARM \u7684\u6bcf\u4e00\u7ea7 memory order \u90fd\u5bf9\u5e94\u4e0d\u540c\u7684\u6307\u4ee4，acquire\/release \u76f8\u5bf9 seq_cst \u5c11\u4e86\u989d\u5916\u7684 barrier\u3002<\/p>\n \u800c\u4ece acquire\/release \u518d\u964d\u5230 relaxed，x86 \u51e0\u4e4e\u65e0\u53d8\u5316（\u672c\u6765\u5c31\u662f\u540c\u4e00\u6761\u00a0MOV），ARM \u4e0a\u53c8\u5feb\u4e86 16%\u2014\u2014\u4f46\u6570\u636e\u662f\u9519\u7684\u3002**\u5728 ARM \u4e0a，relaxed \u7684\u201c\u6027\u80fd\u63d0\u5347\u201d\u662f\u7528\u6b63\u786e\u6027\u6362\u6765\u7684\u3002**<\/p>\n \u8fd9\u7ec4\u6570\u5b57\u8bf4\u660e\u4e86\u4e00\u4e2a\u91cd\u8981\u7ed3\u8bba：memory order \u7684\u9009\u62e9\u5bf9\u6027\u80fd\u7684\u5f71\u54cd\u662f\u5e73\u53f0\u975e\u5bf9\u79f0\u7684\u3002x86 \u4e0a acquire\/release \u51e0\u4e4e\u514d\u8d39，\u6ca1\u6709\u7406\u7531\u7528 relaxed；ARM \u4e0a acquire\/release \u6709\u7ea6 15-20% \u7684\u5f00\u9500\u4f46\u8fd9\u662f\u6b63\u786e\u6027\u7684\u4ee3\u4ef7，\u4e0d\u80fd\u7701\u3002<\/p>\n \n \u5b9e\u6d4b\u9a8c\u8bc1：\u7528 ThreadSanitizer \u548c LKMM Litmus \u6d4b\u8bd5\u4f60\u7684\u5b9e\u73b0<\/h3>\n\u8bb2\u4e86\u8fd9\u4e48\u591a\u6b63\u786e\u6027\u548c\u6027\u80fd\u7684\u53d6\u820d，\u8fd8\u5269\u4e00\u4e2a\u5b9e\u9645\u95ee\u9898\u8981\u56de\u7b54：\u600e\u4e48\u9a8c\u8bc1\u4f60\u7684\u65e0\u9501\u961f\u5217\u5b9e\u73b0\u662f\u6b63\u786e\u7684？\u201c\u5728 x86 \u4e0a\u8dd1\u901a\u6d4b\u8bd5\u201d\u663e\u7136\u4e0d\u591f\u3002<\/p>\n ThreadSanitizer（TSan）<\/h4>\nGCC \u548c Clang \u90fd\u652f\u6301\u00a0-fsanitize=thread\u3002TSan \u5728\u8fd0\u884c\u65f6\u62e6\u622a\u6240\u6709\u5185\u5b58\u8bbf\u95ee\u548c\u540c\u6b65\u64cd\u4f5c，\u68c0\u6d4b data race\u3002\u5b83\u80fd\u68c0\u6d4b\u5230\u5927\u90e8\u5206\u201c\u5b8c\u5168\u6f0f\u6389\u540c\u6b65\u201d\u7684\u60c5\u51b5：<\/p>\n Bash<\/p>\n # GCC 13, -O1 -g -fsanitize=thread \u4f46 TSan \u6709\u4e00\u4e2a\u91cd\u8981\u7684\u5c40\u9650：\u5b83\u4e0d\u68c0\u6d4b memory order \u9009\u62e9\u9519\u8bef\u3002\u00a0\u5982\u679c\u4f60\u7528\u4e86\u00a0std::atomic\u00a0\u5e76\u4e14\u9009\u62e9\u4e86\u00a0relaxed，TSan \u4f1a\u8ba4\u4e3a\u4f60\u662f\u6709\u610f\u4e3a\u4e4b\u2014\u2014\u4f60\u201c\u9009\u62e9\u4e86\u5f31\u540c\u6b65\u8bed\u4e49\u201d\u3002TSan \u4e0d\u4f1a\u62a5\u544a\u201c\u4f60\u8fd9\u91cc\u5e94\u8be5\u7528 release \u800c\u4e0d\u662f relaxed\u201d\u3002<\/p>\n \u6240\u4ee5 TSan \u80fd\u6293\u5230\u201c\u5fd8\u4e86\u7528 atomic\u201d\u7684 bug，\u6293\u4e0d\u5230\u201c\u7528\u4e86 atomic \u4f46 memory order \u9009\u9519\u201d\u7684 bug\u3002\u540e\u8005\u6b63\u662f x86 \u5230 ARM \u79fb\u690d\u65f6\u6700\u5e38\u9047\u5230\u7684\u95ee\u9898\u3002<\/p>\n C\/C++ Memory Model Litmus Tests<\/h4>\n\u66f4\u7cbe\u786e\u7684\u5de5\u5177\u662f\u00a0herd7（\u6765\u81ea INRIA \u7684 diy7 \u5de5\u5177\u5957\u4ef6），\u5b83\u53ef\u4ee5\u5728\u62bd\u8c61\u7684 C11 \u5185\u5b58\u6a21\u578b\u4e0a\u7a77\u4e3e\u6240\u6709\u5408\u6cd5\u7684\u6267\u884c\u5e8f\u5217，\u5224\u65ad\u4e00\u6bb5\u4ee3\u7801\u662f\u5426\u5b58\u5728 data race \u6216\u8fdd\u53cd\u7ea6\u675f\u7684\u6267\u884c\u8def\u5f84\u3002<\/p>\n \u5199\u4e00\u4e2a litmus test \u6765\u9a8c\u8bc1\u6211\u4eec\u7684 SPSC ring buffer \u7684\u5173\u952e\u4e0d\u53d8\u5f0f：<\/p>\n text<\/p>\n C spsc-release-acquire<\/p>\n { P0 (int *x, atomic_int *flag) { P1 (int *x, atomic_int *flag) { exists (1:r1=1 \/\\\\ 1:r2=0) \u7528 herd7 \u8fd0\u884c：<\/p>\n Bash<\/p>\n herd7 spsc-release-acquire.litmus<\/p>\n \u5982\u679c\u628a\u00a0memory_order_release\u00a0\u6539\u6210\u00a0memory_order_relaxed，herd7 \u4f1a\u62a5\u544a\u00a0exists\u00a0\u6761\u4ef6\u53ef\u6ee1\u8db3\u2014\u2014\u5373\u6d88\u8d39\u8005\u53ef\u80fd\u770b\u5230 flag=1 \u4f46 payload=0\u3002\u8fd9\u76f4\u63a5\u8bc1\u660e\u4e86 relaxed \u5728\u5f31\u5185\u5b58\u6a21\u578b\u4e0a\u7684\u4e0d\u5b89\u5168\u6027\u3002<\/p>\n \u5728 ARM \u786c\u4ef6\u4e0a\u5b9e\u9645\u89e6\u53d1<\/h4>\n\u6700\u76f4\u63a5\u7684\u65b9\u6cd5：\u5728\u771f\u6b63\u7684 ARM \u673a\u5668\u4e0a\u8dd1\u538b\u529b\u6d4b\u8bd5\u3002AWS Graviton（\u57fa\u4e8e ARM Neoverse）\u5b9e\u4f8b\u662f\u6700\u65b9\u4fbf\u7684\u9009\u62e9：<\/p>\n Bash<\/p>\n # \u5728 Graviton3 \u5b9e\u4f8b\u4e0a\u7f16\u8bd1\u8fd0\u884c \u5982\u679c\u4f60\u7684\u5b9e\u73b0\u6709 memory order \u9519\u8bef，\u5728 Graviton \u4e0a\u8dd1 10 \u4ebf\u6b21\u64cd\u4f5c\u901a\u5e38\u80fd\u5728\u51e0\u5206\u949f\u5185\u89e6\u53d1\u3002\u6211\u7684\u7ecf\u9a8c\u662f：\u9519\u8bef\u7684 relaxed store \u5728 Graviton3 \u4e0a\u5927\u7ea6\u6bcf\u767e\u4e07\u6b21\u64cd\u4f5c\u51fa\u4e00\u6b21\u53ef\u89c2\u6d4b\u7684\u9519\u8bef\u2014\u2014\u9891\u7387\u4e0d\u7b97\u9ad8\u4f46\u7edd\u4e0d\u662f\u7406\u8bba\u4e0a\u7684\u3002<\/p>\n \u800c\u5728 x86 \u4e0a\u8dd1\u540c\u6837\u7684\u6d4b\u8bd5\u2014\u2014\u5373\u4f7f\u4f60\u628a\u6240\u6709 memory order \u90fd\u6539\u6210 relaxed\u2014\u2014\u4e00\u5343\u4ebf\u6b21\u4e5f\u672a\u5fc5\u51fa\u4e00\u6b21\u3002\u56e0\u4e3a TSO \u5728\u66ff\u4f60\u515c\u5e95\u3002<\/p>\n \n C++20\/23\/26 \u7684\u6f14\u8fdb：\u6807\u51c6\u5728\u8ffd\u8d76\u5de5\u7a0b\u5b9e\u8df5<\/h3>\n\u518d\u770b\u4e00\u4e0b\u6807\u51c6\u6f14\u8fdb\u3002C++11 \u5f15\u5165\u00a0<atomic>\u00a0\u81f3\u4eca\u5df2\u7ecf\u5341\u591a\u5e74，\u540e\u7eed\u6807\u51c6\u4e00\u76f4\u5728\u8865\u9f50\u5e76\u53d1\u5de5\u5177\u94fe：<\/p>\n C++20：<\/p>\n
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