{"id":79205,"date":"2026-03-01T12:42:14","date_gmt":"2026-03-01T04:42:14","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/79205.html"},"modified":"2026-03-01T12:42:14","modified_gmt":"2026-03-01T04:42:14","slug":"stm32%e5%9b%ba%e4%bb%b6%e5%ba%93%ef%bc%88spl%ef%bc%89%e6%b7%b1%e5%ba%a6%e8%a7%a3%e6%9e%90%ef%bc%9a%e4%bb%8e%e5%af%84%e5%ad%98%e5%99%a8%e6%98%a0%e5%b0%84%e5%88%b0%e5%b7%a5%e7%a8%8b%e5%ae%9e%e8%b7%b5","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/79205.html","title":{"rendered":"STM32\u56fa\u4ef6\u5e93\uff08SPL\uff09\u6df1\u5ea6\u89e3\u6790\uff1a\u4ece\u5bc4\u5b58\u5668\u6620\u5c04\u5230\u5de5\u7a0b\u5b9e\u8df5"},"content":{"rendered":"

\n 1. \u56fa\u4ef6\u5e93\u7684\u672c\u8d28\u4e0e\u5de5\u7a0b\u5b9a\u4f4d
\n<\/h3>\n

\n \u56fa\u4ef6\u5e93（Standard Peripheral Library，SPL）\u4e0d\u662f\u4e00\u5957\u9ed1\u76d2\u5de5\u5177\u96c6，\u800c\u662fST\u5b98\u65b9\u4e3aSTM32\u7cfb\u5217\u5fae\u63a7\u5236\u5668\u63d0\u4f9b\u7684\u3001\u4ecb\u4e8e\u786c\u4ef6\u5bc4\u5b58\u5668\u64cd\u4f5c\u4e0e\u9ad8\u7ea7\u62bd\u8c61\u6846\u67b6\u4e4b\u95f4\u7684\u4e2d\u95f4\u5c42\u8f6f\u4ef6\u7ec4\u4ef6\u3002\u5b83\u65e2\u4e0d\u7b49\u540c\u4e8eCMSIS\u5185\u6838\u5c42\u7684\u6807\u51c6\u5316\u63a5\u53e3，\u4e5f\u4e0d\u5177\u5907HAL\u5e93\u7684\u8de8\u7cfb\u5217\u517c\u5bb9\u6027\u8bbe\u8ba1，\u5176\u6838\u5fc3\u4ef7\u503c\u5728\u4e8e：<\/p>\n

\u4ee5C\u8bed\u8a00\u7ed3\u6784\u4f53\u548c\u51fd\u6570\u5c01\u88c5\u7684\u65b9\u5f0f，\u5c06F10x\u7cfb\u5217\u82af\u7247\u5916\u8bbe\u5bc4\u5b58\u5668\u7684\u64cd\u4f5c\u903b\u8f91\u56fa\u5316\u4e3a\u53ef\u590d\u7528\u3001\u53ef\u914d\u7f6e\u3001\u53ef\u8ffd\u6eaf\u7684\u5de5\u7a0b\u6a21\u5757<\/p>\n

\u3002\n<\/p>\n

\n \u5728\u5b9e\u9645\u5d4c\u5165\u5f0f\u5f00\u53d1\u4e2d，\u56fa\u4ef6\u5e93\u7684\u5de5\u7a0b\u5b9a\u4f4d\u975e\u5e38\u660e\u786e：\u5b83\u662f\u9762\u5411\u7279\u5b9a\u82af\u7247\u5bb6\u65cf（F10x）\u3001\u7279\u5b9a\u5185\u6838\u67b6\u6784（Cortex-M3）\u3001\u7279\u5b9a\u7f16\u8bd1\u73af\u5883（ARM GCC\/Keil\/IAR）\u7684<\/p>\n

\u751f\u4ea7\u7ea7\u9a71\u52a8\u57fa\u7840<\/p>\n

\u3002\u8fd9\u610f\u5473\u7740\u5f00\u53d1\u8005\u65e0\u9700\u4ece\u96f6\u5f00\u59cb\u7f16\u5199GPIO\u7ffb\u8f6c\u3001USART\u6ce2\u7279\u7387\u8ba1\u7b97\u3001TIM\u5b9a\u65f6\u5668\u91cd\u88c5\u8f7d\u503c\u914d\u7f6e\u7b49\u91cd\u590d\u6027\u4ee3\u7801，\u4f46\u540c\u65f6\u4e5f\u8981\u6c42\u5f00\u53d1\u8005\u5fc5\u987b\u7406\u89e3\u5176\u5185\u90e8\u6620\u5c04\u5173\u7cfb\u2014\u2014\u56e0\u4e3a\u6bcf\u4e00\u4e2a<\/p>\n

GPIO_Init()<\/p>\n

\u8c03\u7528\u80cc\u540e，\u90fd\u5bf9\u5e94\u7740\u5bf9<\/p>\n

GPIOx_CRL<\/p>\n

\/<\/p>\n

GPIOx_CRH<\/p>\n

\u5bc4\u5b58\u5668\u7684\u4f4d\u64cd\u4f5c；\u6bcf\u4e00\u6b21<\/p>\n

USART_SendData()<\/p>\n

\u6267\u884c，\u672c\u8d28\u90fd\u662f\u5411<\/p>\n

USART_DR<\/p>\n

\u5bc4\u5b58\u5668\u5199\u5165\u6570\u636e\u5e76\u8f6e\u8be2<\/p>\n

TXE<\/p>\n

\u6807\u5fd7\u4f4d\u3002\n<\/p>\n

\n \u8fd9\u79cd\u201c\u534a\u62bd\u8c61\u201d\u7279\u6027\u51b3\u5b9a\u4e86\u56fa\u4ef6\u5e93\u7684\u5b66\u4e60\u8def\u5f84\u4e0d\u80fd\u505c\u7559\u5728API\u8c03\u7528\u5c42\u9762\u3002\u82e5\u4ec5\u8bb0\u4f4f<\/p>\n

RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE)<\/p>\n

\u8fd9\u884c\u4ee3\u7801，\u5374\u4e0d\u7406\u89e3\u5b83\u4e3a\u4f55\u64cd\u4f5c<\/p>\n

RCC->APB2ENR<\/p>\n

\u5bc4\u5b58\u5668\u3001\u4e3a\u4f55<\/p>\n

GPIOA<\/p>\n

\u7684\u4f7f\u80fd\u4f4d\u4f4d\u4e8e\u8be5\u5bc4\u5b58\u5668\u7b2c2\u4f4d\u3001\u4e3a\u4f55APB2\u603b\u7ebf\u65f6\u949f\u9891\u7387\u76f4\u63a5\u5f71\u54cdGPIO\u7ffb\u8f6c\u901f\u5ea6，\u5219\u4e00\u65e6\u9047\u5230\u65f6\u5e8f\u5f02\u5e38\u6216\u5916\u8bbe\u65e0\u54cd\u5e94\u95ee\u9898，\u5c06\u5b8c\u5168\u4e27\u5931\u8c03\u8bd5\u80fd\u529b\u3002\u56e0\u6b64，\u56fa\u4ef6\u5e93\u76ee\u5f55\u7ed3\u6784\u7684\u5206\u6790，\u672c\u8d28\u4e0a\u662f\u5bf9\u8fd9\u5957\u8f6f\u4ef6\u6620\u5c04\u5173\u7cfb\u7684\u9006\u5411\u5de5\u7a0b\u89e3\u6784\u3002\n<\/p>\n

\n 2. \u76ee\u5f55\u7ed3\u6784\u5168\u666f\u89e3\u6790：\u4ece\u6839\u76ee\u5f55\u5230\u5bc4\u5b58\u5668\u6620\u5c04
\n<\/h3>\n

\n \u56fa\u4ef6\u5e933.5.0\u7248\u672c\u7684\u76ee\u5f55\u5c42\u7ea7\u5e76\u975e\u968f\u610f\u7ec4\u7ec7，\u800c\u662f\u4e25\u683c\u9075\u5faa\u201c\u82af\u7247\u62bd\u8c61\u2192\u5185\u6838\u62bd\u8c61\u2192\u5916\u8bbe\u9a71\u52a8\u2192\u5de5\u7a0b\u6a21\u677f\u201d\u7684\u5206\u5c42\u903b\u8f91\u3002\u4ee5\u4e0b\u6309\u5b9e\u9645\u5de5\u7a0b\u4f9d\u8d56\u987a\u5e8f\u5c55\u5f00\u89e3\u6790，\u6240\u6709\u8def\u5f84\u5747\u57fa\u4e8e\u6807\u51c6\u5b89\u88c5\u7ed3\u6784（\u5982<\/p>\n

STM32F10x_StdPeriph_Lib_V3.5.0<\/p>\n

）\u3002\n<\/p>\n

\n 2.1 \u6839\u76ee\u5f55\u6982\u89c8\u4e0e\u65e0\u5173\u9879\u8bc6\u522b
\n<\/h4>\n

\n \u8fdb\u5165\u56fa\u4ef6\u5e93\u6839\u76ee\u5f55\u540e，\u9996\u5148\u53ef\u89c1\u591a\u4e2a\u4e00\u7ea7\u5b50\u76ee\u5f55：<\/p>\n

–<\/p>\n

Libraries\/<\/p>\n

：\u6838\u5fc3\u9a71\u52a8\u4ee3\u7801\u5b58\u653e\u533a，<\/p>\n

\u552f\u4e00\u9700\u8981\u6df1\u5ea6\u5173\u6ce8\u7684\u76ee\u5f55<\/p>\n

–<\/p>\n

Project\/<\/p>\n

：\u5b98\u65b9\u793a\u4f8b\u5de5\u7a0b\u96c6\u5408，\u5305\u542b\u4e0d\u540cIDE\u7684\u5de5\u7a0b\u6a21\u677f<\/p>\n

–<\/p>\n

Utilities\/<\/p>\n

：\u8bc4\u4f30\u677f（Evaluation Board）\u4e13\u7528\u4ee3\u7801，\u5982<\/p>\n

STM32_EVAL<\/p>\n

\u7cfb\u5217，<\/p>\n

\u5bf9\u81ea\u5b9a\u4e49\u786c\u4ef6\u65e0\u76f4\u63a5\u53c2\u8003\u4ef7\u503c<\/p>\n

–<\/p>\n

License.txt<\/p>\n

\u3001<\/p>\n

Release_Notes.html<\/p>\n

：\u6cd5\u5f8b\u58f0\u660e\u4e0e\u7248\u672c\u8bf4\u660e，\u5f00\u53d1\u4e2d\u53ef\u5ffd\u7565\n<\/p>\n

\n \u5173\u952e\u8ba4\u77e5：<\/p>\n

Utilities\/<\/p>\n

\u76ee\u5f55\u4e0b\u7684\u6240\u6709\u5185\u5bb9（\u5982<\/p>\n

STM3210C_EVAL<\/p>\n

\u3001<\/p>\n

STM3210E_EVAL<\/p>\n

）\u5747\u9488\u5bf9ST\u5b98\u65b9\u63a8\u51fa\u7684\u7279\u5b9a\u8bc4\u4f30\u677f\u8bbe\u8ba1，\u5176\u4ee3\u7801\u4e2d\u5927\u91cf\u4f7f\u7528\u677f\u7ea7\u5b8f\u5b9a\u4e49（\u5982<\/p>\n

LED1<\/p>\n

\u3001<\/p>\n

JOY_LEFT<\/p>\n

）\u548c\u4e13\u7528\u9a71\u52a8（\u5982LCD\u63a7\u5236\u5668\u521d\u59cb\u5316）\u3002\u9664\u975e\u4f60\u624b\u63e1\u4e00\u5757STM3210E-EVAL\u677f\u5e76\u9700\u5feb\u901f\u9a8c\u8bc1\u529f\u80fd，\u5426\u5219\u8be5\u76ee\u5f55\u5bf9\u7edd\u5927\u591a\u6570\u57fa\u4e8e\u91ce\u706b\u3001\u6b63\u70b9\u539f\u5b50\u7b49\u56fd\u4ea7\u5f00\u53d1\u677f\u7684\u9879\u76ee\u6beb\u65e0\u610f\u4e49\u3002\u5f3a\u884c\u79fb\u690d\u5176\u4e2d\u4ee3\u7801\u5f80\u5f80\u5bfc\u81f4\u5f15\u811a\u51b2\u7a81\u3001\u65f6\u949f\u914d\u7f6e\u9519\u8bef\u7b49\u6df1\u5c42\u95ee\u9898\u3002\n<\/p>\n

\n 2.2 Project\u76ee\u5f55：\u6a21\u677f\u4e0e\u793a\u4f8b\u7684\u5de5\u7a0b\u4ef7\u503c
\n<\/h4>\n

Project\/<\/p>\n

\u76ee\u5f55\u662f\u56fa\u4ef6\u5e93\u4e2d<\/p>\n

\u6700\u5177\u5de5\u7a0b\u5b9e\u8df5\u6307\u5bfc\u610f\u4e49\u7684\u90e8\u5206<\/p>\n

，\u5206\u4e3a\u4e24\u4e2a\u5173\u952e\u5b50\u76ee\u5f55：\n<\/p>\n

\n 2.2.1 Templates：\u8de8\u7f16\u8bd1\u5668\u5de5\u7a0b\u9aa8\u67b6
\n<\/h5>\n

Project\/Templates\/<\/p>\n

\u4e0b\u5b58\u5728\u591a\u4e2a\u5b50\u76ee\u5f55，\u5982<\/p>\n

ARM\/<\/p>\n

\u3001<\/p>\n

GCC\/<\/p>\n

\u3001<\/p>\n

IAR\/<\/p>\n

，\u5206\u522b\u5bf9\u5e94Keil MDK\u3001GNU ARM GCC\u3001IAR EWARM\u4e09\u79cd\u4e3b\u6d41\u7f16\u8bd1\u73af\u5883\u3002\u6bcf\u4e2a\u5b50\u76ee\u5f55\u5185\u5305\u542b：<\/p>\n

–<\/p>\n

startup_stm32f10x_hd.s<\/p>\n

：\u542f\u52a8\u6587\u4ef6（\u540e\u6587\u8be6\u8ff0）<\/p>\n

–<\/p>\n

stm32f10x_conf.h<\/p>\n

：\u5916\u8bbe\u9a71\u52a8\u5934\u6587\u4ef6\u5305\u542b\u914d\u7f6e<\/p>\n

–<\/p>\n

main.c<\/p>\n

：\u7a7a\u4e3b\u51fd\u6570\u6846\u67b6<\/p>\n

–<\/p>\n

stm32f10x_it.c\/h<\/p>\n

：\u4e2d\u65ad\u670d\u52a1\u51fd\u6570\u6846\u67b6\n<\/p>\n

\n \u8fd9\u4e9b\u6a21\u677f\u7684\u4ef7\u503c\u5728\u4e8e：<\/p>\n

\u63d0\u4f9b\u4e86\u7b26\u5408\u5404\u7f16\u8bd1\u5668\u89c4\u8303\u7684\u6700\u5c0f\u53ef\u8fd0\u884c\u5de5\u7a0b\u7ed3\u6784<\/p>\n

\u3002\u4f8b\u5982，Keil\u6a21\u677f\u4e2d<\/p>\n

startup_stm32f10x_hd.s<\/p>\n

\u5df2\u9884\u7f6e\u5411\u91cf\u8868\u5730\u5740\u3001\u5806\u6808\u521d\u59cb\u5316\u3001\u7cfb\u7edf\u65f6\u949f\u914d\u7f6e\u5165\u53e3（<\/p>\n

SystemInit<\/p>\n

），\u800cGCC\u6a21\u677f\u5219\u4f7f\u7528<\/p>\n

.s<\/p>\n

\u6c47\u7f16\u8bed\u6cd5\u5b9a\u4e49\u76f8\u540c\u529f\u80fd\u3002\u5f00\u53d1\u8005\u65b0\u5efa\u5de5\u7a0b\u65f6，\u5e94\u76f4\u63a5\u590d\u5236\u5bf9\u5e94\u7f16\u8bd1\u5668\u7684Templates\u76ee\u5f55，\u518d\u9010\u6b65\u66ff\u6362<\/p>\n

main.c<\/p>\n

\u4e2d\u7684\u4e1a\u52a1\u903b\u8f91，\u800c\u975e\u4ece\u96f6\u521b\u5efa\u542f\u52a8\u6587\u4ef6\u2014\u2014\u8fd9\u662f\u907f\u514d\u94fe\u63a5\u9519\u8bef\u3001\u590d\u4f4d\u5411\u91cf\u9519\u4f4d\u7b49\u5e95\u5c42\u95ee\u9898\u7684\u5173\u952e\u3002\n<\/p>\n

\n 2.2.2 Examples：\u5916\u8bbe\u9a71\u52a8\u7684\u6743\u5a01\u5b9e\u73b0\u8303\u672c
\n<\/h5>\n

Project\/Examples\/<\/p>\n

\u76ee\u5f55\u6309\u5916\u8bbe\u7c7b\u578b\u7ec4\u7ec7，\u5982<\/p>\n

ADC\/<\/p>\n

\u3001<\/p>\n

EXTI\/<\/p>\n

\u3001<\/p>\n

USART\/<\/p>\n

\u7b49\u3002\u6bcf\u4e2a\u5916\u8bbe\u5b50\u76ee\u5f55\u5185\u5305\u542b：<\/p>\n

–<\/p>\n

main.c<\/p>\n

：\u5e94\u7528\u4e3b\u903b\u8f91<\/p>\n

–<\/p>\n

stm32f10x_it.c<\/p>\n

：\u4e2d\u65ad\u5904\u7406<\/p>\n

–<\/p>\n

system_stm32f10x.c<\/p>\n

：\u7cfb\u7edf\u65f6\u949f\u914d\u7f6e<\/p>\n

–<\/p>\n

README.txt<\/p>\n

：\u529f\u80fd\u8bf4\u660e\u4e0e\u914d\u7f6e\u8981\u70b9\n<\/p>\n

\n \u4ee5<\/p>\n

USART\/Interrupt\/<\/p>\n

\u4e3a\u4f8b，\u5176<\/p>\n

README.txt<\/p>\n

\u660e\u786e\u8bf4\u660e：\u201cThis example provides a basic demonstration of USART communication using Interrupt mode. It configures USART1 for 115200 bps, 8 data bits, 1 stop bit, no parity\u2026\u201d\u3002\u8fd9\u79cd\u6587\u6863\u4e0d\u662f\u88c5\u9970\u54c1，\u800c\u662fST\u5de5\u7a0b\u5e08\u5bf9\u9a71\u52a8\u884c\u4e3a\u7684\u5951\u7ea6\u5f0f\u58f0\u660e\u3002\u66f4\u91cd\u8981\u7684\u662f，\u6240\u6709\u793a\u4f8b\u4ee3\u7801\u5747\u901a\u8fc7<\/p>\n

#include "stm32f10x_usart.h"<\/p>\n

\u5f15\u5165\u6807\u51c6\u5934\u6587\u4ef6，\u5e76\u8c03\u7528<\/p>\n

USART_Init()<\/p>\n

\u3001<\/p>\n

USART_ITConfig()<\/p>\n

\u7b49\u6807\u51c6API，\u5176\u521d\u59cb\u5316\u53c2\u6570（\u5982<\/p>\n

USART_InitStruct.USART_BaudRate = 115200<\/p>\n

）\u4e0e\u6570\u636e\u624b\u518c\u4e2d\u6ce2\u7279\u7387\u8ba1\u7b97\u516c\u5f0f\u5b8c\u5168\u4e00\u81f4\u3002\u8fd9\u610f\u5473\u7740：<\/p>\n

\u5f53\u4f60\u5728\u9879\u76ee\u4e2d\u9047\u5230USART\u63a5\u6536\u4e22\u5931\u6570\u636e\u7684\u95ee\u9898\u65f6，\u5e94\u9996\u5148\u6bd4\u5bf9\u793a\u4f8b\u5de5\u7a0b\u7684NVIC\u4f18\u5148\u7ea7\u914d\u7f6e\u3001\u4e2d\u65ad\u670d\u52a1\u51fd\u6570\u4e2d<\/p>\n

USART_GetITStatus()<\/p>\n

\u4e0e<\/p>\n

USART_ClearITPendingBit()<\/p>\n

\u7684\u8c03\u7528\u987a\u5e8f，\u800c\u975e\u76f2\u76ee\u641c\u7d22\u7f51\u7edc\u8bba\u575b<\/p>\n

\u3002\n<\/p>\n

\n 2.3 Libraries\u76ee\u5f55：\u9a71\u52a8\u6838\u5fc3\u7684\u7269\u7406\u8f7d\u4f53
\n<\/h4>\n

Libraries\/<\/p>\n

\u662f\u56fa\u4ef6\u5e93\u7684\u7edd\u5bf9\u6838\u5fc3，\u5176\u7ed3\u6784\u76f4\u63a5\u6620\u5c04\u82af\u7247\u786c\u4ef6\u67b6\u6784：\n<\/p>\n

Libraries\/
\n\u251c\u2500\u2500 CMSIS\/ # Cortex-M3\u5185\u6838\u6807\u51c6\u63a5\u53e3
\n\u2502 \u2514\u2500\u2500 Device\/ # ST\u5b9a\u5236\u5316\u5185\u6838\u5c42
\n\u2502 \u2514\u2500\u2500 ST\/ # ST\u5382\u5546\u6269\u5c55
\n\u2502 \u2514\u2500\u2500 STM32F10x\/ # F10x\u7cfb\u5217\u4e13\u5c5e
\n\u251c\u2500\u2500 STM32F10x_StdPeriph_Driver\/ # \u5916\u8bbe\u9a71\u52a8\u6e90\u7801
\n\u2502 \u251c\u2500\u2500 inc\/ # \u5934\u6587\u4ef6（.h）
\n\u2502 \u2514\u2500\u2500 src\/ # \u6e90\u6587\u4ef6（.c）<\/p>\n

\n \u6b64\u5206\u5c42\u4f53\u73b0\u4e86ST\u5bf9ARM\u751f\u6001\u7684\u9075\u5faa：CMSIS\u5c42\u4fdd\u8bc1\u5185\u6838\u5bc4\u5b58\u5668\u8bbf\u95ee\u7684\u6807\u51c6\u5316，StdPeriph_Driver\u5c42\u5b9e\u73b0\u5916\u8bbe\u5bc4\u5b58\u5668\u7684C\u8bed\u8a00\u5c01\u88c5\u3002\u4efb\u4f55\u8bd5\u56fe\u7ed5\u8fc7\u6b64\u7ed3\u6784\u76f4\u63a5\u64cd\u4f5c\u5bc4\u5b58\u5668\u7684\u884c\u4e3a，\u90fd\u5c06\u5931\u53bb\u56fa\u4ef6\u5e93\u5e26\u6765\u7684\u53ef\u7ef4\u62a4\u6027\u4e0e\u53ef\u79fb\u690d\u6027\u4f18\u52bf\u3002\n<\/p>\n

\n 3. CMSIS\u5c42\u6df1\u5ea6\u5256\u6790：\u5185\u6838\u5bc4\u5b58\u5668\u7684\u6807\u51c6\u5316\u6620\u5c04
\n<\/h3>\n

\n CMSIS（Cortex Microcontroller Software Interface Standard）\u662fARM\u5b98\u65b9\u5236\u5b9a\u7684\u3001\u7528\u4e8e\u7edf\u4e00Cortex-M\u7cfb\u5217\u5185\u6838\u8f6f\u4ef6\u63a5\u53e3\u7684\u6807\u51c6\u3002\u5728F10x\u56fa\u4ef6\u5e93\u4e2d，CMSIS\u5c42\u4f4d\u4e8e<\/p>\n

Libraries\/CMSIS\/Device\/ST\/STM32F10x\/<\/p>\n

，\u5176\u8bbe\u8ba1\u76ee\u6807\u662f：<\/p>\n

\u8ba9\u5f00\u53d1\u8005\u65e0\u9700\u5173\u5fc3\u5185\u6838\u5bc4\u5b58\u5668\u7684\u7269\u7406\u5730\u5740，\u4ec5\u901a\u8fc7\u6807\u51c6\u5316\u7684\u7ed3\u6784\u4f53\u6210\u5458\u5373\u53ef\u5b8c\u6210\u5185\u6838\u7ea7\u914d\u7f6e<\/p>\n

\u3002\n<\/p>\n

\n 3.1 core_cm3.h：\u5185\u6838\u5916\u8bbe\u7684C\u8bed\u8a00\u89c6\u56fe
\n<\/h4>\n

core_cm3.h<\/p>\n

\u662fCMSIS\u7684\u6838\u5fc3\u5934\u6587\u4ef6，\u5b83\u5b9a\u4e49\u4e86\u6240\u6709Cortex-M3\u5185\u6838\u5916\u8bbe\u7684\u5bc4\u5b58\u5668\u7ed3\u6784\u4f53\u3002\u4ee5NVIC（Nested Vectored Interrupt Controller）\u4e3a\u4f8b，\u8be5\u6587\u4ef6\u4e2d\u5b9a\u4e49：\n<\/p>\n

typedef struct {
\n __IO uint32_t ISER[8]; \/*!< Offset: 0x000 (R\/W) Interrupt Set Enable Register *\/
\n uint32_t RESERVED0[24]; \/*!< Offset: 0x080 Reserved *\/
\n __IO uint32_t ICER[8]; \/*!< Offset: 0x180 (R\/W) Interrupt Clear Enable Register *\/
\n uint32_t RSERVED1[24]; \/*!< Offset: 0x200 Reserved *\/
\n __IO uint32_t ISPR[8]; \/*!< Offset: 0x280 (R\/W) Interrupt Set Pending Register *\/
\n \/\/ … \u66f4\u591a\u5bc4\u5b58\u5668
\n} NVIC_Type;<\/p>\n

\n \u6b64\u7ed3\u6784\u4f53\u5c06NVIC\u7684\u8fde\u7eed\u5185\u5b58\u7a7a\u95f4\u6620\u5c04\u4e3aC\u8bed\u8a00\u53ef\u64cd\u4f5c\u7684\u6570\u7ec4\u3002\u5f53\u4ee3\u7801\u4e2d\u51fa\u73b0<\/p>\n

NVIC->ISER[0] = 0x00000001;<\/p>\n

\u65f6，\u7f16\u8bd1\u5668\u81ea\u52a8\u5c06\u5176\u8f6c\u6362\u4e3a\u5bf9\u5730\u5740<\/p>\n

0xE000E100<\/p>\n

\u7684\u5199\u64cd\u4f5c（NVIC_ISER0\u5bc4\u5b58\u5668\u57fa\u5740）\u3002\u8fd9\u79cd\u6620\u5c04\u6d88\u9664\u4e86\u624b\u52a8\u8ba1\u7b97\u5bc4\u5b58\u5668\u5730\u5740\u7684\u9519\u8bef\u98ce\u9669，\u662f\u56fa\u4ef6\u5e93\u7a33\u5b9a\u6027\u7684\u57fa\u77f3\u3002\n<\/p>\n

\n 3.2 system_stm32f10x.c：\u65f6\u949f\u6811\u7684\u53ef\u914d\u7f6e\u5f15\u64ce
\n<\/h4>\n

Libraries\/CMSIS\/Device\/ST\/STM32F10x\/system_stm32f10x.c<\/p>\n

\u6587\u4ef6\u5b9e\u73b0\u4e86F10x\u7cfb\u5217\u7684\u7cfb\u7edf\u65f6\u949f\u521d\u59cb\u5316\u3002\u5176\u6838\u5fc3\u51fd\u6570<\/p>\n

SystemInit()<\/p>\n

\u7684\u903b\u8f91\u5982\u4e0b：\n<\/p>\n

void SystemInit (void) {
\n \/* Reset the RCC clock configuration to the default reset state *\/
\n RCC->CR |= (uint32_t)0x00000001; \/\/ HSI ON
\n RCC->CFGR = 0x00000000; \/\/ Reset SW, HPRE, PPRE1, PPRE2, ADCPRE, MCO
\n RCC->CIR = 0x00000000; \/\/ Disable all interrupts<\/p>\n

\/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers *\/
\n \/* Configure the Flash Latency cycles and enable prefetch buffer *\/
\n #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
\n \/* … VL\u7cfb\u5217\u914d\u7f6e … *\/
\n #elif defined (STM32F10X_LD) || (defined STM32F10X_MD) || (defined STM32F10X_HD) || \\\\
\n (defined STM32F10X_XL) || (defined STM32F10X_CL)
\n \/* … HD\/Medium-Density\u914d\u7f6e … *\/
\n SetSysClock();
\n #endif
\n}<\/p>\n

\n \u5173\u952e\u70b9\u5728\u4e8e<\/p>\n

SetSysClock()<\/p>\n

\u51fd\u6570\u2014\u2014\u5b83\u6839\u636e\u9884\u7f16\u8bd1\u5b8f（\u5982<\/p>\n

USE_STDPERIPH_DRIVER<\/p>\n

\u3001<\/p>\n

HSE_VALUE<\/p>\n

）\u9009\u62e9\u4e0d\u540c\u7684\u65f6\u949f\u914d\u7f6e\u8def\u5f84\u3002\u4f8b\u5982，\u5f53\u5b9a\u4e49<\/p>\n

HSE_VALUE=8000000<\/p>\n

\u4e14\u76ee\u6807\u4e3aHD\u7cfb\u5217\u65f6，<\/p>\n

SetSysClock()<\/p>\n

\u4f1a\u8c03\u7528<\/p>\n

SetSysClockTo72()<\/p>\n

，\u8be5\u51fd\u6570\u5185\u90e8\u6267\u884c：<\/p>\n

1. \u4f7f\u80fdHSE\u632f\u8361\u5668：<\/p>\n

RCC->CR |= ((uint32_t)RCC_CR_HSEON);<\/p>\n

2. \u7b49\u5f85HSE\u5c31\u7eea：<\/p>\n

while((RCC->CR & RCC_CR_HSERDY) == 0x00);<\/p>\n

3. \u914d\u7f6ePLL\u500d\u9891：<\/p>\n

RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);<\/p>\n

4. \u4f7f\u80fdPLL：<\/p>\n

RCC->CR |= RCC_CR_PLLON;<\/p>\n

5. \u5207\u6362\u7cfb\u7edf\u65f6\u949f\u6e90：<\/p>\n

RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;<\/p>\n

\n \u8fd9\u79cd\u57fa\u4e8e\u5b8f\u5b9a\u4e49\u7684\u6761\u4ef6\u7f16\u8bd1\u673a\u5236，\u4f7f\u5f97\u540c\u4e00\u4efd\u56fa\u4ef6\u5e93\u4ee3\u7801\u53ef\u9002\u914d\u4e0d\u540c\u6676\u632f\u9891\u7387（4MHz\/8MHz\/12MHz）\u548c\u4e0d\u540c\u6027\u80fd\u9700\u6c42（24MHz\/72MHz\u7cfb\u7edf\u65f6\u949f），\u5f00\u53d1\u8005\u53ea\u9700\u4fee\u6539<\/p>\n

stm32f10x.h<\/p>\n

\u4e2d\u7684<\/p>\n

HSE_VALUE<\/p>\n

\u5b8f，\u5373\u53ef\u5168\u81ea\u52a8\u5b8c\u6210\u65f6\u949f\u6811\u91cd\u6784\u3002\n<\/p>\n

\n 3.3 startup_stm32f10x_hd.s：\u542f\u52a8\u8fc7\u7a0b\u7684\u7cbe\u786e\u63a7\u5236
\n<\/h4>\n

\n \u542f\u52a8\u6587\u4ef6（\u5982<\/p>\n

startup_stm32f10x_hd.s<\/p>\n

）\u662f\u56fa\u4ef6\u5e93\u4e0e\u786c\u4ef6\u7684\u9996\u4e2a\u63a5\u89e6\u70b9，\u5176\u91cd\u8981\u6027\u5e38\u88ab\u4f4e\u4f30\u3002\u8be5\u6587\u4ef6\u5b9a\u4e49\u4e86：<\/p>\n

–<\/p>\n

\u5411\u91cf\u8868（Vector Table）<\/p>\n

：\u4f4d\u4e8eFlash\u8d77\u59cb\u5730\u5740<\/p>\n

0x08000000<\/p>\n

，\u5305\u542b\u590d\u4f4d\u5411\u91cf\u3001NMI\u3001HardFault\u7b4916\u4e2a\u5185\u6838\u5f02\u5e38\u5411\u91cf\u53ca\u540e\u7eed84\u4e2a\u5916\u8bbe\u4e2d\u65ad\u5411\u91cf\u3002<\/p>\n

–<\/p>\n

\u5806\u6808\u6307\u9488\u521d\u59cb\u5316<\/p>\n

：<\/p>\n

Stack_Size EQU 0x00000400<\/p>\n

\u5b9a\u4e49\u5806\u5927\u5c0f，<\/p>\n

__initial_sp<\/p>\n

\u6307\u5411\u5806\u6808\u9876\u3002<\/p>\n

–<\/p>\n

\u590d\u4f4d\u5904\u7406\u6d41\u7a0b<\/p>\n

：<\/p>\n

Reset_Handler<\/p>\n

\u6807\u7b7e\u5904\u6267\u884c<\/p>\n

SystemInit()<\/p>\n

（\u7cfb\u7edf\u65f6\u949f\u521d\u59cb\u5316）\u2192<\/p>\n

__main<\/p>\n

（C\u5e93\u521d\u59cb\u5316）\u2192<\/p>\n

main()<\/p>\n

（\u7528\u6237\u4e3b\u51fd\u6570）\u3002\n<\/p>\n

\n \u7279\u522b\u6ce8\u610f：<\/p>\n

startup_stm32f10x_hd.s<\/p>\n

\u4e2d\u7684<\/p>\n

hd<\/p>\n

\u540e\u7f00\u4ee3\u8868\u201cHigh-Density\u201d，\u5373Flash\u5bb9\u91cf\u4e3a256KB\u81f3512KB\u7684F103\u7cfb\u5217（\u5982F103ZET6）\u3002\u82e5\u8bef\u7528<\/p>\n

startup_stm32f10x_md.s<\/p>\n

（Medium-Density，64KB-128KB），\u4f1a\u5bfc\u81f4\u5411\u91cf\u8868\u6ea2\u51fa\u3001\u4e2d\u65ad\u65e0\u6cd5\u89e6\u53d1\u7b49\u9690\u853d\u6545\u969c\u3002\u91ce\u706b\u9738\u9053\u6307\u5357\u8005\u5f00\u53d1\u677f\u91c7\u7528F103ZE\u82af\u7247（512KB Flash），\u5fc5\u987b\u9009\u7528<\/p>\n

hd<\/p>\n

\u7248\u672c\u542f\u52a8\u6587\u4ef6\u3002\n<\/p>\n

\n 4. StdPeriph_Driver\u5c42：\u5916\u8bbe\u9a71\u52a8\u7684\u5b9e\u73b0\u539f\u7406
\n<\/h3>\n

Libraries\/STM32F10x_StdPeriph_Driver\/<\/p>\n

\u76ee\u5f55\u5305\u542b\u6240\u6709F10x\u5916\u8bbe\u7684C\u8bed\u8a00\u9a71\u52a8，\u5176\u8bbe\u8ba1\u9075\u5faa\u7edf\u4e00\u6a21\u5f0f：<\/p>\n

\u6bcf\u4e2a\u5916\u8bbe\u5bf9\u5e94\u4e00\u5bf9\u6587\u4ef6（<\/p>\n

.c<\/p>\n

\u4e0e<\/p>\n

.h<\/p>\n

），\u5934\u6587\u4ef6\u5b9a\u4e49\u521d\u59cb\u5316\u7ed3\u6784\u4f53\u4e0eAPI\u539f\u578b，\u6e90\u6587\u4ef6\u5b9e\u73b0\u5bc4\u5b58\u5668\u64cd\u4f5c\u903b\u8f91<\/p>\n

\u3002\n<\/p>\n

\n 4.1 \u5934\u6587\u4ef6\u89c4\u8303：\u7ed3\u6784\u4f53\u4e0e\u679a\u4e3e\u7684\u8bed\u4e49\u5316\u5b9a\u4e49
\n<\/h4>\n

\n \u4ee5<\/p>\n

stm32f10x_gpio.h<\/p>\n

\u4e3a\u4f8b，\u5176\u6838\u5fc3\u5b9a\u4e49\u5305\u62ec：\n<\/p>\n

\/**
\n * @brief GPIO Init structure definition
\n *\/
\ntypedef struct {
\n uint16_t GPIO_Pin; \/*!< Specifies the GPIO pins to be configured.
\n This parameter can be any value of @ref GPIO_pins_define *\/<\/p>\n

GPIOSpeed_TypeDef GPIO_Speed; \/*!< Specifies the speed for the selected pins.
\n This parameter can be a value of @ref GPIOSpeed_TypeDef *\/<\/p>\n

GPIOMode_TypeDef GPIO_Mode; \/*!< Specifies the operating mode for the selected pins.
\n This parameter can be a value of @ref GPIOMode_TypeDef *\/
\n} GPIO_InitTypeDef;<\/p>\n

\/** @defgroup GPIOMode_TypeDef
\n * @{
\n *\/
\ntypedef enum {
\n GPIO_Mode_AIN = 0x0, \/*!< Analog input mode *\/
\n GPIO_Mode_IN_FLOATING = 0x04, \/*!< Floating input mode *\/
\n GPIO_Mode_IPD = 0x28, \/*!< Input with pull-down mode *\/
\n GPIO_Mode_IPU = 0x48, \/*!< Input with pull-up mode *\/
\n GPIO_Mode_Out_OD = 0x14, \/*!< Output open-drain mode *\/
\n GPIO_Mode_Out_PP = 0x10, \/*!< Output push-pull mode *\/
\n GPIO_Mode_AF_OD = 0x1C, \/*!< Output Alternate Function open-drain mode *\/
\n GPIO_Mode_AF_PP = 0x18 \/*!< Output Alternate Function push-pull mode *\/
\n} GPIOMode_TypeDef;<\/p>\n

\n \u6b64\u5904<\/p>\n

GPIOMode_TypeDef<\/p>\n

\u679a\u4e3e\u503c\u5e76\u975e\u968f\u610f\u7f16\u7801，\u800c\u662f\u76f4\u63a5\u5bf9\u5e94<\/p>\n

GPIOx_CRL<\/p>\n

\/<\/p>\n

GPIOx_CRH<\/p>\n

\u5bc4\u5b58\u5668\u4e2dMODE[1:0]\u4e0eCNF[1:0]\u4f4d\u7684\u7ec4\u5408\u3002\u4f8b\u5982<\/p>\n

GPIO_Mode_Out_PP = 0x10<\/p>\n

，\u5176\u4e8c\u8fdb\u5236\u4e3a<\/p>\n

00010000<\/p>\n

，\u62c6\u89e3\u4e3aMODE=0b10（\u8f93\u51fa\u6a21\u5f0f，\u6700\u5927\u901f\u738750MHz）\u3001CNF=0b00（\u63a8\u633d\u8f93\u51fa），\u4e0e\u6570\u636e\u624b\u518c\u4e2d\u5bc4\u5b58\u5668\u4f4d\u5b9a\u4e49\u5b8c\u5168\u4e00\u81f4\u3002\u8fd9\u79cd\u8bbe\u8ba1\u4f7f\u5f00\u53d1\u8005\u80fd\u901a\u8fc7\u679a\u4e3e\u540d\u76f4\u89c9\u7406\u89e3\u786c\u4ef6\u884c\u4e3a，\u907f\u514d\u67e5\u8868\u9519\u8bef\u3002\n<\/p>\n

\n 4.2 \u6e90\u6587\u4ef6\u5b9e\u73b0：\u5bc4\u5b58\u5668\u64cd\u4f5c\u7684\u7cbe\u51c6\u7ffb\u8bd1
\n<\/h4>\n

stm32f10x_gpio.c<\/p>\n

\u4e2d\u7684<\/p>\n

GPIO_Init()<\/p>\n

\u51fd\u6570\u662f\u7406\u89e3\u9a71\u52a8\u539f\u7406\u7684\u94a5\u5319：\n<\/p>\n

void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) {
\n uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
\n \/\/ … \u53c2\u6570\u5408\u6cd5\u6027\u68c0\u67e5 …<\/p>\n

\/* Configure the port pins *\/
\n currentpin = GPIO_InitStruct->GPIO_Pin;
\n for (pinpos = 0x00; pinpos < 0x10; pinpos++) {
\n pos = ((uint32_t)0x01) << pinpos;
\n if ((currentpin & pos) != 0x00) {
\n \/* Configure the port pin *\/
\n if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) ||
\n (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) ||
\n (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) ||
\n (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD)) {
\n \/* Output mode *\/
\n \/\/ … \u914d\u7f6eCRL\/CRH\u7684MODE\u4f4d …
\n } else {
\n \/* Input mode *\/
\n \/\/ … \u914d\u7f6eCRL\/CRH\u7684CNF\u4f4d …
\n }
\n \/\/ … \u914d\u7f6eODR\u5bc4\u5b58\u5668（\u8f93\u51fa\u7535\u5e73）…
\n }
\n }
\n}<\/p>\n

\n \u6b64\u51fd\u6570\u904d\u5386<\/p>\n

GPIO_InitStruct->GPIO_Pin<\/p>\n

\u4e2d\u7f6e\u4f4d\u7684\u6bcf\u4e00\u4f4d（\u5982<\/p>\n

GPIO_Pin_5 | GPIO_Pin_6<\/p>\n

），\u5bf9\u6bcf\u4e2a\u5f15\u811a\u5355\u72ec\u914d\u7f6e\u5176<\/p>\n

CRL<\/p>\n

（\u4f4e8\u4f4d）\u6216<\/p>\n

CRH<\/p>\n

（\u9ad88\u4f4d）\u5bc4\u5b58\u5668\u3002\u5173\u952e\u6d1e\u5bdf\u5728\u4e8e：<\/p>\n

\u56fa\u4ef6\u5e93\u5e76\u672a\u4e00\u6b21\u6027\u5199\u5165\u6574\u4e2aCRL\u5bc4\u5b58\u5668，\u800c\u662f\u901a\u8fc7\u8bfb-\u6539-\u5199（Read-Modify-Write）\u65b9\u5f0f，\u4ec5\u4fee\u6539\u76ee\u6807\u5f15\u811a\u5bf9\u5e94\u76844\u4f4d\u5b57\u6bb5，\u786e\u4fdd\u5176\u4ed6\u5f15\u811a\u914d\u7f6e\u4e0d\u53d7\u5f71\u54cd<\/p>\n

\u3002\u8fd9\u662f\u88f8\u673a\u7f16\u7a0b\u4e2d\u6781\u6613\u51fa\u9519\u7684\u73af\u8282，\u56fa\u4ef6\u5e93\u901a\u8fc7\u5c01\u88c5\u5c06\u5176\u81ea\u52a8\u5316\u3002\n<\/p>\n

\n 4.3 \u5916\u8bbe\u65f6\u949f\u4f7f\u80fd：\u603b\u7ebf\u8fde\u63a5\u7684\u786c\u6027\u7ea6\u675f
\n<\/h4>\n

\n \u6240\u6709\u5916\u8bbe\u9a71\u52a8\u51fd\u6570（\u5982<\/p>\n

USART_Init()<\/p>\n

\u3001<\/p>\n

TIM_TimeBaseInit()<\/p>\n

）\u5747\u9690\u542b\u4e00\u4e2a\u524d\u63d0：\u5bf9\u5e94\u5916\u8bbe\u65f6\u949f\u5fc5\u987b\u5df2\u4f7f\u80fd\u3002\u8fd9\u4e00\u7ea6\u675f\u6e90\u4e8eSTM32\u7684\u603b\u7ebf\u67b6\u6784\u2014\u2014APB1\/APB2\u603b\u7ebf\u4e0a\u7684\u5916\u8bbe，\u5176\u5bc4\u5b58\u5668\u53ea\u6709\u5728\u65f6\u949f\u4f7f\u80fd\u540e\u624d\u53ef\u88abCPU\u8bbf\u95ee\u3002\u4f8b\u5982，\u521d\u59cb\u5316USART1\u524d\u5fc5\u987b\u6267\u884c：\n<\/p>\n

RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_USART1, ENABLE);<\/p>\n

\n \u8be5\u51fd\u6570\u5b9e\u9645\u64cd\u4f5c<\/p>\n

RCC->APB2ENR<\/p>\n

\u5bc4\u5b58\u5668，\u5c06\u7b2c14\u4f4d\u7f6e1（USART1\u4f7f\u80fd\u4f4d）\u3002\u82e5\u9057\u6f0f\u6b64\u6b65，<\/p>\n

USART_Init()<\/p>\n

\u4e2d\u5bf9<\/p>\n

USART1->BRR<\/p>\n

\u5bc4\u5b58\u5668\u7684\u5199\u64cd\u4f5c\u5c06\u65e0\u6548，\u5bfc\u81f4\u4e32\u53e3\u6c38\u8fdc\u65e0\u6cd5\u5de5\u4f5c\u3002\u56fa\u4ef6\u5e93\u672a\u5728\u6b64\u7c7b\u51fd\u6570\u5185\u81ea\u52a8\u4f7f\u80fd\u65f6\u949f，\u6b63\u662f\u4e3a\u4e86\u5f3a\u5236\u5f00\u53d1\u8005\u5efa\u7acb\u201c\u65f6\u949f\u5148\u884c\u201d\u7684\u786c\u4ef6\u601d\u7ef4\u4e60\u60ef\u3002\n<\/p>\n

\n 5. \u6587\u6863\u4e0e\u6e90\u7801\u534f\u540c：\u9ad8\u6548\u638c\u63e1\u56fa\u4ef6\u5e93\u7684\u65b9\u6cd5\u8bba
\n<\/h3>\n

\n \u9762\u5bf9\u56fa\u4ef6\u5e93\u5e9e\u5927\u7684API\u4f53\u7cfb，\u76f2\u76ee\u9605\u8bfb\u624b\u518c\u6216\u7f51\u7edc\u6559\u7a0b\u6548\u7387\u6781\u4f4e\u3002\u7ecf\u8fc7\u6570\u767e\u4e2a\u9879\u76ee\u9a8c\u8bc1，\u6700\u9ad8\u6548\u7684\u638c\u63e1\u8def\u5f84\u662f：<\/p>\n

\u4ee5\u6e90\u7801\u4e3a\u552f\u4e00\u771f\u76f8\u6e90，\u4ee5\u6570\u636e\u624b\u518c\u4e3a\u786c\u4ef6\u4f9d\u636e，\u4ee5\u793a\u4f8b\u5de5\u7a0b\u4e3a\u884c\u4e3a\u9a8c\u8bc1<\/p>\n

\u3002\n<\/p>\n

\n 5.1 \u653e\u5f03\u4e2d\u6587\u624b\u518c：\u82f1\u6587\u539f\u7248\u6587\u6863\u7684\u6b63\u786e\u6253\u5f00\u65b9\u5f0f
\n<\/h4>\n

\n \u56fa\u4ef6\u5e93\u6839\u76ee\u5f55\u4e0b\u7684<\/p>\n

Documentation\/<\/p>\n

\u6587\u4ef6\u5939\u4e2d，<\/p>\n

stm32f10x_stdperiph_lib_um.chm<\/p>\n

（CHM\u683c\u5f0f）\u662f\u552f\u4e00\u7684\u5b98\u65b9API\u53c2\u8003\u624b\u518c\u3002\u4f46\u9700\u6e05\u9192\u8ba4\u8bc6：<\/p>\n

\u8be5\u624b\u518c\u4ec5\u63cf\u8ff0\u51fd\u6570\u529f\u80fd\u4e0e\u53c2\u6570，\u4e0d\u89e3\u91ca\u5176\u5b9e\u73b0\u539f\u7406，\u4e14\u90e8\u5206\u7248\u672c\u5b58\u5728\u7ffb\u8bd1\u6ede\u540e<\/p>\n

\u3002\u66f4\u81f4\u547d\u7684\u662f，\u7f51\u4e0a\u6d41\u4f20\u7684\u6240\u8c13\u201c\u4e2d\u6587\u56fa\u4ef6\u5e93\u624b\u518c\u201d\u591a\u4e3aV1.0\u7248\u672c（2007\u5e74\u53d1\u5e03），\u5176\u5185\u5bb9\u4e0eV3.5.0\u5b58\u5728\u5de8\u5927\u5dee\u5f02\u2014\u2014V1.0\u4e2d<\/p>\n

GPIO_Init()<\/p>\n

\u53c2\u6570\u4e3a<\/p>\n

GPIO_Mode_Out_PP<\/p>\n

，\u800cV3.5.0\u4e2d\u5df2\u6539\u4e3a<\/p>\n

GPIO_Mode_Out_PP<\/p>\n

（\u540d\u79f0\u4e00\u81f4\u4f46\u5185\u90e8\u4f4d\u5b9a\u4e49\u53ef\u80fd\u53d8\u5316），\u76f4\u63a5\u5957\u7528\u65e7\u624b\u518c\u5c06\u5bfc\u81f4\u914d\u7f6e\u9519\u8bef\u3002\n<\/p>\n

\n \u6b63\u786e\u505a\u6cd5\u662f：\u5c06<\/p>\n

stm32f10x_stdperiph_lib_um.chm<\/p>\n

\u4f5c\u4e3a\u901f\u67e5\u5b57\u5178，\u4ec5\u5728\u9700\u8981\u786e\u8ba4\u67d0\u51fd\u6570\u53c2\u6570\u8303\u56f4\u65f6\u67e5\u9605\u3002\u4f8b\u5982，\u5f53\u4e0d\u786e\u5b9a<\/p>\n

USART_InitTypeDef.USART_StopBits<\/p>\n

\u53ef\u53d6\u503c\u65f6，\u5feb\u901f\u641c\u7d22\u624b\u518c\u4e2d<\/p>\n

USART_StopBits_TypeDef<\/p>\n

\u679a\u4e3e，\u786e\u8ba4\u5176\u5305\u542b<\/p>\n

USART_StopBits_1<\/p>\n

\u3001<\/p>\n

USART_StopBits_2<\/p>\n

\u7b49\u9009\u9879\u3002\n<\/p>\n

\n 5.2 \u6e90\u7801\u5373\u6587\u6863：\u51fd\u6570\u539f\u578b\u7684\u6df1\u5ea6\u89e3\u8bfb\u6280\u5de7
\n<\/h4>\n

\n \u56fa\u4ef6\u5e93\u771f\u6b63\u7684\u201c\u624b\u518c\u201d\u85cf\u5728\u5176\u6e90\u7801\u4e2d\u3002\u4ee5<\/p>\n

GPIO_SetBits()<\/p>\n

\u51fd\u6570\u4e3a\u4f8b，\u5176\u58f0\u660e\u4f4d\u4e8e<\/p>\n

stm32f10x_gpio.h<\/p>\n

：\n<\/p>\n

void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);<\/p>\n

\n \u4f46\u4ec5\u770b\u6b64\u58f0\u660e\u65e0\u6cd5\u7406\u89e3\u5176\u884c\u4e3a\u3002\u6b64\u65f6\u5e94：<\/p>\n

1. \u5728IDE\u4e2d\u53f3\u952e\u70b9\u51fb\u51fd\u6570\u540d \u2192 \u201cGo to Definition\u201d（\u6216\u6309F12），\u8df3\u8f6c\u81f3<\/p>\n

stm32f10x_gpio.c<\/p>\n

\u4e2d\u5b9e\u73b0：\n<\/p>\n

void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) {
\n GPIOx->BSRR = GPIO_Pin;
\n}<\/p>\n

  • \n \u67e5\u770b<\/p>\n

    BSRR<\/p>\n

    \u5bc4\u5b58\u5668\u5728\u6570\u636e\u624b\u518c\u4e2d\u7684\u5b9a\u4e49：BSRR（Bit Set\/Reset Register）\u662f\u4e00\u4e2a32\u4f4d\u5bc4\u5b58\u5668，\u4f4e16\u4f4d（BS0-BS15）\u4e3a\u7f6e\u4f4d\u63a9\u7801，\u9ad816\u4f4d（BR0-BR15）\u4e3a\u590d\u4f4d\u63a9\u7801\u3002\u5411BSRR\u5199\u5165<\/p>\n

    0x0020<\/p>\n

    （\u5373<\/p>\n

    GPIO_Pin_5<\/p>\n

    ），\u7b49\u6548\u4e8e\u8bbe\u7f6e<\/p>\n

    GPIOx_BSRR[5] = 1<\/p>\n

    ，\u5f3a\u5236<\/p>\n

    GPIOx_ODR[5]<\/p>\n

    \u4e3a1，\u4e14\u4e0d\u5f71\u54cd\u5176\u4ed6\u4f4d\u3002\n <\/li>\n

  • \n \u7ed3\u5408\u6570\u636e\u624b\u518c\u9a8c\u8bc1：<\/p>\n

    BSRR<\/p>\n

    \u5bc4\u5b58\u5668\u5730\u5740\u4e3a<\/p>\n

    0x00000018<\/p>\n

    \u76f8\u5bf9\u504f\u79fb，<\/p>\n

    GPIOx<\/p>\n

    \u57fa\u5740（\u5982<\/p>\n

    GPIOA_BASE = 0x40010800<\/p>\n

    ）\u52a0\u504f\u79fb\u5f97<\/p>\n

    0x40010818<\/p>\n

    ，\u4e0e\u624b\u518c\u4e00\u81f4\u3002\n <\/li>\n

    \n \u6b64\u8fc7\u7a0b\u5c06\u62bd\u8c61API\u8fd8\u539f\u4e3a\u5177\u4f53\u786c\u4ef6\u64cd\u4f5c，\u5efa\u7acb\u8d77\u201c\u4ee3\u7801\u2192\u5bc4\u5b58\u5668\u2192\u786c\u4ef6\u201d\u7684\u5b8c\u6574\u8ba4\u77e5\u94fe\u3002\u4e00\u4e2a\u7ecf\u9a8c\u6cd5\u5219：<\/p>\n

    \u82b120\u5206\u949f\u7cbe\u8bfb\u4e00\u4e2a\u9a71\u52a8\u6587\u4ef6（\u5982<\/p>\n

    stm32f10x_usart.c<\/p>\n

    ）\u7684\u5168\u90e8\u51fd\u6570\u5b9e\u73b0，\u80dc\u8fc7\u6d4f\u89c82\u5c0f\u65f6\u4e2d\u6587\u535a\u5ba2<\/p>\n

    \u3002\n<\/p>\n

    \n 5.3 \u793a\u4f8b\u5de5\u7a0b\u8c03\u8bd5：\u4ece\u73b0\u8c61\u5230\u672c\u8d28\u7684\u95ed\u73af\u9a8c\u8bc1
    \n<\/h4>\n

    \n \u5f53\u7406\u8bba\u5b66\u4e60\u9047\u5230\u74f6\u9888\u65f6，\u793a\u4f8b\u5de5\u7a0b\u662f\u6700\u53ef\u9760\u7684\u9a8c\u8bc1\u573a\u3002\u4ee5<\/p>\n

    ADC\/Regular_Conversion\/<\/p>\n

    \u4e3a\u4f8b，\u5176<\/p>\n

    main.c<\/p>\n

    \u4e2d\u5173\u952e\u4ee3\u7801：\n<\/p>\n

    ADC_DeInit(ADC1);
    \nADC_StructInit(&ADC_InitStructure);
    \nADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
    \nADC_InitStructure.ADC_ScanConvMode = DISABLE;
    \nADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
    \nADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
    \nADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
    \nADC_InitStructure.ADC_NbrOfChannel = 1;
    \nADC_Init(ADC1, &ADC_InitStructure);<\/p>\n

    \/\/ … \u901a\u9053\u914d\u7f6e …
    \nADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_239Cycles5);<\/p>\n

    ADC_Cmd(ADC1, ENABLE);
    \nADC_ResetCalibration(ADC1);
    \nwhile(ADC_GetResetCalibrationStatus(ADC1));
    \nADC_StartCalibration(ADC1);
    \nwhile(ADC_GetCalibrationStatus(ADC1));<\/p>\n

    ADC_SoftwareStartConvCmd(ADC1, ENABLE);<\/p>\n

    \n \u82e5\u5b9e\u6d4bADC\u8bfb\u6570\u59cb\u7ec8\u4e3a0，\u8c03\u8bd5\u6b65\u9aa4\u5e94\u4e3a：<\/p>\n

    1. \u4f7f\u7528\u903b\u8f91\u5206\u6790\u4eea\u6355\u83b7<\/p>\n

    ADC1->DR<\/p>\n

    \u5bc4\u5b58\u5668\u8bfb\u53d6\u65f6\u5e8f，\u786e\u8ba4\u662f\u5426\u771f\u6709\u6570\u636e；<\/p>\n

    2. \u68c0\u67e5<\/p>\n

    RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1, ENABLE)<\/p>\n

    \u662f\u5426\u6267\u884c；<\/p>\n

    3. \u9a8c\u8bc1<\/p>\n

    ADC_RegularChannelConfig()<\/p>\n

    \u4e2d<\/p>\n

    ADC_Channel_0<\/p>\n

    \u662f\u5426\u5bf9\u5e94PA0\u5f15\u811a（\u6570\u636e\u624b\u518cTable 5）；<\/p>\n

    4. \u5728<\/p>\n

    ADC_SoftwareStartConvCmd()<\/p>\n

    \u540e\u6dfb\u52a0<\/p>\n

    while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));<\/p>\n

    \u7b49\u5f85\u8f6c\u6362\u5b8c\u6210，\u800c\u975e\u76f4\u63a5\u8bfb<\/p>\n

    ADC_GetConversionValue()<\/p>\n

    \u3002\n<\/p>\n

    \n \u6b64\u8fc7\u7a0b\u5c06\u95ee\u9898\u4ece\u201c\u4e3a\u4ec0\u4e48ADC\u4e0d\u5de5\u4f5c\u201d\u964d\u7ef4\u4e3a\u201c\u54ea\u4e2a\u5bc4\u5b58\u5668\u914d\u7f6e\u672a\u751f\u6548\u201d，\u6781\u5927\u7f29\u77ed\u8c03\u8bd5\u5468\u671f\u3002\n<\/p>\n

    \n 6. \u5de5\u7a0b\u5b9e\u8df5\u8b66\u793a：\u5e38\u89c1\u9677\u9631\u4e0e\u89c4\u907f\u7b56\u7565
    \n<\/h3>\n

    \n \u56fa\u4ef6\u5e93\u867d\u7b80\u5316\u5f00\u53d1，\u4f46\u5176\u62bd\u8c61\u5c42\u4e5f\u9690\u85cf\u7740\u8bf8\u591a\u6613\u8e29\u6df1\u5751\u3002\u4ee5\u4e0b\u662f\u91ce\u706bF103\u5f00\u53d1\u4e2d\u9ad8\u9891\u51fa\u73b0\u7684\u516d\u4e2a\u5178\u578b\u95ee\u9898\u53ca\u5176\u672c\u8d28\u539f\u56e0：\n<\/p>\n

    \n 6.1 \u542f\u52a8\u6587\u4ef6\u9009\u578b\u9519\u8bef：HD vs MD\u7684\u81f4\u547d\u5dee\u5f02
    \n<\/h4>\n

    \n \u73b0\u8c61：\u7a0b\u5e8f\u4e0b\u8f7d\u540e\u65e0\u6cd5\u8fd0\u884c，J-Link\u63d0\u793a\u201cTarget not connected\u201d\u3002<\/p>\n

    \u6839\u6e90：F103ZE（512KB Flash）\u5c5e\u4e8eHD\u7cfb\u5217，\u5fc5\u987b\u4f7f\u7528<\/p>\n

    startup_stm32f10x_hd.s<\/p>\n

    \u3002\u82e5\u8bef\u7528MD\u7cfb\u5217\u542f\u52a8\u6587\u4ef6，\u5176\u5411\u91cf\u8868\u4ec5\u9884\u755964\u4e2a\u4e2d\u65ad\u5411\u91cf（MD\u7cfb\u5217\u6700\u591a64\u5916\u8bbe\u4e2d\u65ad），\u800cHD\u7cfb\u5217\u9700\u652f\u630184\u4e2a，\u5bfc\u81f4<\/p>\n

    USART1_IRQn<\/p>\n

    \u7b49\u5173\u952e\u5411\u91cf\u5730\u5740\u9519\u4f4d，\u590d\u4f4d\u540e\u8df3\u8f6c\u81f3\u975e\u6cd5\u5730\u5740\u3002<\/p>\n

    \u89c4\u907f：\u4e25\u683c\u5bf9\u7167\u82af\u7247Flash\u5bb9\u91cf\u9009\u62e9\u542f\u52a8\u6587\u4ef6\u2014\u2014HD（256-512KB）\u3001MD（64-128KB）\u3001XL（512KB+）\u3001CL（\u4e92\u8054\u578b）\u3002\n<\/p>\n

    \n 6.2 \u4e2d\u65ad\u4f18\u5148\u7ea7\u5206\u7ec4\u6df7\u4e71：\u62a2\u5360\u4f18\u5148\u7ea7\u5931\u6548
    \n<\/h4>\n

    \n \u73b0\u8c61：\u914d\u7f6e<\/p>\n

    NVIC_InitTypeDef.NVIC_IRQChannelPreemptionPriority = 0<\/p>\n

    ，\u4f46\u9ad8\u4f18\u5148\u7ea7\u4e2d\u65ad\u4ecd\u88ab\u4f4e\u4f18\u5148\u7ea7\u4e2d\u65ad\u6253\u65ad\u3002<\/p>\n

    \u6839\u6e90：<\/p>\n

    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0)<\/p>\n

    \u672a\u8c03\u7528\u3002F10x\u9ed8\u8ba4\u5206\u7ec4\u4e3a<\/p>\n

    NVIC_PriorityGroup_0<\/p>\n

    （0\u4f4d\u62a2\u5360，4\u4f4d\u5b50\u4f18\u5148\u7ea7），\u82e5\u672a\u663e\u5f0f\u914d\u7f6e，<\/p>\n

    NVIC_Init()<\/p>\n

    \u4e2d<\/p>\n

    NVIC_IRQChannelPreemptionPriority<\/p>\n

    \u53c2\u6570\u5c06\u88ab\u5ffd\u7565，\u5b9e\u9645\u4f7f\u7528\u9ed8\u8ba4\u5206\u7ec4\u3002<\/p>\n

    \u89c4\u907f：\u5728<\/p>\n

    NVIC_Init()<\/p>\n

    \u524d\u5fc5\u987b\u8c03\u7528<\/p>\n

    NVIC_PriorityGroupConfig()<\/p>\n

    ，\u4e14\u5206\u7ec4\u9009\u62e9\u9700\u5339\u914d\u9879\u76ee\u9700\u6c42（\u5982\u4ec5\u97002\u7ea7\u62a2\u5360\u5219\u9009<\/p>\n

    NVIC_PriorityGroup_1<\/p>\n

    ）\u3002\n<\/p>\n

    \n 6.3 GPIO\u590d\u7528\u529f\u80fd\u672a\u4f7f\u80fd：AFIO\u65f6\u949f\u7f3a\u5931
    \n<\/h4>\n

    \n \u73b0\u8c61：\u914d\u7f6e<\/p>\n

    GPIO_Mode_AF_PP<\/p>\n

    \u540e，USART\/TIM\u7b49\u590d\u7528\u529f\u80fd\u5f15\u811a\u65e0\u8f93\u51fa\u3002<\/p>\n

    \u6839\u6e90：\u590d\u7528\u529f\u80fd\u7531AFIO（Alternate Function I\/O）\u5355\u5143\u7ba1\u7406，\u5176\u65f6\u949f\u9700\u5355\u72ec\u4f7f\u80fd：<\/p>\n

    RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);<\/p>\n

    \u3002\u82e5\u9057\u6f0f，<\/p>\n

    GPIO_PinRemapConfig()<\/p>\n

    \u7b49\u51fd\u6570\u65e0\u6548\u3002<\/p>\n

    \u89c4\u907f：\u6240\u6709\u6d89\u53ca<\/p>\n

    GPIO_PinRemapConfig()<\/p>\n

    \u3001<\/p>\n

    GPIO_RemapSWJ_JTAGDisable()<\/p>\n

    \u7684\u64cd\u4f5c\u524d，\u5fc5\u987b\u4f7f\u80fdAFIO\u65f6\u949f\u3002\n<\/p>\n

    \n 6.4 SysTick\u4e2d\u65ad\u672a\u542f\u7528：HAL_Delay()\u5931\u6548
    \n<\/h4>\n

    \n \u73b0\u8c61：\u8c03\u7528<\/p>\n

    HAL_Delay(1000)<\/p>\n

    \u540e\u7a0b\u5e8f\u5361\u6b7b\u3002<\/p>\n

    \u6839\u6e90：\u56fa\u4ef6\u5e93\u672c\u8eab\u4e0d\u63d0\u4f9b<\/p>\n

    HAL_Delay()<\/p>\n

    ，\u6b64\u4e3aHAL\u5e93\u51fd\u6570\u3002\u82e5\u5728SPL\u5de5\u7a0b\u4e2d\u8bef\u7528，\u56e0<\/p>\n

    SysTick_Config()<\/p>\n

    \u672a\u88ab\u8c03\u7528\u4e14<\/p>\n

    SysTick_Handler()<\/p>\n

    \u672a\u5b9e\u73b0，\u5bfc\u81f4\u65e0\u9650\u7b49\u5f85\u3002<\/p>\n

    \u89c4\u907f：SPL\u5de5\u7a0b\u4e2d\u5e94\u4f7f\u7528<\/p>\n

    SysTick_Config(SystemCoreClock \/ 1000)<\/p>\n

    \u624b\u52a8\u914d\u7f6eSysTick，\u5e76\u5728<\/p>\n

    stm32f10x_it.c<\/p>\n

    \u4e2d\u5b9e\u73b0<\/p>\n

    void SysTick_Handler(void)<\/p>\n

    ，\u914d\u5408\u5168\u5c40\u53d8\u91cf\u8ba1\u6570\u5b9e\u73b0\u5ef6\u65f6\u3002\n<\/p>\n

    \n 6.5 \u5916\u8bbe\u65f6\u949f\u4f7f\u80fd\u987a\u5e8f\u9519\u8bef：ADC\u6821\u51c6\u5931\u8d25
    \n<\/h4>\n

    \n \u73b0\u8c61：<\/p>\n

    ADC_ResetCalibration()<\/p>\n

    \u8fd4\u56de<\/p>\n

    SET<\/p>\n

    ，\u4f46<\/p>\n

    ADC_GetResetCalibrationStatus()<\/p>\n

    \u59cb\u7ec8\u4e3a<\/p>\n

    SET<\/p>\n

    ，\u6821\u51c6\u65e0\u6cd5\u5b8c\u6210\u3002<\/p>\n

    \u6839\u6e90：ADC\u6821\u51c6\u9700\u5728ADC\u65f6\u949f\u4f7f\u80fd\u540e\u3001ADC\u4f7f\u80fd\u524d\u6267\u884c\u3002\u82e5\u987a\u5e8f\u4e3a<\/p>\n

    ADC_Cmd(ENABLE)<\/p>\n

    \u2192<\/p>\n

    ADC_ResetCalibration()<\/p>\n

    ，\u56e0ADC\u5df2\u8fd0\u884c，\u6821\u51c6\u5bc4\u5b58\u5668\u88ab\u9501\u5b9a\u3002<\/p>\n

    \u89c4\u907f：\u4e25\u683c\u9075\u5faa\u65f6\u5e8f：<\/p>\n

    RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1, ENABLE)<\/p>\n

    \u2192<\/p>\n

    ADC_DeInit(ADC1)<\/p>\n

    \u2192<\/p>\n

    ADC_ResetCalibration()<\/p>\n

    \u2192\u7b49\u5f85\u5b8c\u6210\u2192<\/p>\n

    ADC_StartCalibration()<\/p>\n

    \u2192\u7b49\u5f85\u5b8c\u6210\u2192<\/p>\n

    ADC_Cmd(ENABLE)<\/p>\n

    \u3002\n<\/p>\n

    \n 6.6 \u7f16\u8bd1\u5668\u4f18\u5316\u7b49\u7ea7\u8bef\u7528：volatile\u7f3a\u5931\u5bfc\u81f4\u6b7b\u5faa\u73af
    \n<\/h4>\n

    \n \u73b0\u8c61：<\/p>\n

    while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET);<\/p>\n

    \u9677\u5165\u6b7b\u5faa\u73af，\u5373\u4f7fTXE\u6807\u5fd7\u5df2\u7f6e\u4f4d\u3002<\/p>\n

    \u6839\u6e90：\u7f16\u8bd1\u5668\u4f18\u5316（\u5982-O2）\u5c06<\/p>\n

    USART_GetFlagStatus()<\/p>\n

    \u7684\u8fd4\u56de\u503c\u7f13\u5b58\u4e8e\u5bc4\u5b58\u5668，\u672a\u91cd\u65b0\u8bfb\u53d6<\/p>\n

    USART1->SR<\/p>\n

    \u5bc4\u5b58\u5668\u3002\u56e0<\/p>\n

    SR<\/p>\n

    \u5bc4\u5b58\u5668\u4e3avolatile\u7c7b\u578b，\u5176\u8bfb\u53d6\u5fc5\u987b\u5f3a\u5236\u8bbf\u95ee\u5185\u5b58\u3002<\/p>\n

    \u89c4\u907f：\u786e\u4fdd<\/p>\n

    stm32f10x_usart.h<\/p>\n

    \u4e2d<\/p>\n

    USART_GetFlagStatus()<\/p>\n

    \u539f\u578b\u6b63\u786e（\u8fd4\u56de\u503c\u4e3a<\/p>\n

    FlagStatus<\/p>\n

    ，\u5185\u90e8\u901a\u8fc7<\/p>\n

    __IO uint32_t<\/p>\n

    \u8bbf\u95ee），\u4e14\u7f16\u8bd1\u5668\u672a\u7981\u7528volatile\u8bed\u4e49\u3002\u82e5\u4ecd\u5f02\u5e38，\u53ef\u6dfb\u52a0<\/p>\n

    __DSB()<\/p>\n

    \u5185\u5b58\u5c4f\u969c\u6307\u4ee4\u3002\n<\/p>\n

    \n 7. \u4ece\u56fa\u4ef6\u5e93\u5230\u771f\u5b9e\u9879\u76ee：\u6784\u5efa\u53ef\u7ef4\u62a4\u7684\u5de5\u7a0b\u6846\u67b6
    \n<\/h3>\n

    \n \u56fa\u4ef6\u5e93\u7684\u4ef7\u503c\u6700\u7ec8\u4f53\u73b0\u5728\u53ef\u7ef4\u62a4\u7684\u5de5\u7a0b\u9879\u76ee\u4e2d\u3002\u4e00\u4e2a\u5065\u58ee\u7684F103\u5de5\u7a0b\u4e0d\u5e94\u662f\u793a\u4f8b\u4ee3\u7801\u7684\u7b80\u5355\u62fc\u63a5，\u800c\u5e94\u5177\u5907\u6e05\u6670\u7684\u5206\u5c42\u4e0e\u4e25\u683c\u7684\u7ea6\u675f\u3002\n<\/p>\n

    \n 7.1 \u5de5\u7a0b\u76ee\u5f55\u7ed3\u6784\u6807\u51c6\u5316
    \n<\/h4>\n

    \n \u63a8\u8350\u91c7\u7528\u4ee5\u4e0b\u7269\u7406\u76ee\u5f55\u7ed3\u6784，\u4e0e\u56fa\u4ef6\u5e93\u903b\u8f91\u89e3\u8026：\n<\/p>\n

    MyProject\/
    \n\u251c\u2500\u2500 Core\/ # \u7528\u6237\u6838\u5fc3\u4ee3\u7801
    \n\u2502 \u251c\u2500\u2500 main.c # \u7cfb\u7edf\u5165\u53e3
    \n\u2502 \u251c\u2500\u2500 app_usart.c # \u5e94\u7528\u5c42\u4e32\u53e3\u9a71\u52a8
    \n\u2502 \u2514\u2500\u2500 app_adc.c # \u5e94\u7528\u5c42ADC\u9a71\u52a8
    \n\u251c\u2500\u2500 Drivers\/ # \u56fa\u4ef6\u5e93\u9a71\u52a8（\u53ea\u8bfb\u526f\u672c）
    \n\u2502 \u251c\u2500\u2500 CMSIS\/ # \u4ece\u56fa\u4ef6\u5e93\u62f7\u8d1d
    \n\u2502 \u2514\u2500\u2500 StdPeriph\/ # \u4ece\u56fa\u4ef6\u5e93\u62f7\u8d1d
    \n\u251c\u2500\u2500 Config\/ # \u786c\u4ef6\u914d\u7f6e\u4e2d\u5fc3
    \n\u2502 \u251c\u2500\u2500 stm32f10x_conf.h # \u5916\u8bbe\u5934\u6587\u4ef6\u5f00\u5173
    \n\u2502 \u2514\u2500\u2500 board_config.h # \u677f\u7ea7\u5f15\u811a\u5b9a\u4e49
    \n\u2514\u2500\u2500 Output\/ # \u7f16\u8bd1\u8f93\u51fa<\/p>\n

    \n \u5173\u952e\u7ea6\u675f：<\/p>\n

    Drivers\/<\/p>\n

    \u76ee\u5f55\u4e3a\u53ea\u8bfb，\u7981\u6b62\u4fee\u6539\u4efb\u4f55<\/p>\n

    .c\/.h<\/p>\n

    \u6587\u4ef6\u3002\u6240\u6709\u5b9a\u5236\u5316\u914d\u7f6e（\u5982<\/p>\n

    RCC_PLLMul_9<\/p>\n

    ）\u5e94\u5728<\/p>\n

    Config\/<\/p>\n

    \u76ee\u5f55\u4e0b\u901a\u8fc7\u5b8f\u5b9a\u4e49\u5b9e\u73b0，\u786e\u4fdd\u56fa\u4ef6\u5e93\u539f\u59cb\u6027\u4e0e\u53ef\u5347\u7ea7\u6027\u3002\n<\/p>\n

    \n 7.2 \u677f\u7ea7\u914d\u7f6e\u4e2d\u5fc3：board_config.h\u7684\u8bbe\u8ba1\u54f2\u5b66
    \n<\/h4>\n

    Config\/board_config.h<\/p>\n

    \u662f\u5de5\u7a0b\u4e0e\u786c\u4ef6\u7684\u552f\u4e00\u63a5\u53e3，\u5176\u5185\u5bb9\u5e94\u4ec5\u5305\u542b：\n<\/p>\n

    #ifndef __BOARD_CONFIG_H
    \n#define __BOARD_CONFIG_H<\/p>\n

    \/* LED Configuration *\/
    \n#define LED_GPIO_PORT GPIOC
    \n#define LED_GPIO_CLK RCC_APB2PERIPH_GPIOC
    \n#define LED_GPIO_PIN GPIO_Pin_13
    \n#define LED_ON() GPIO_ResetBits(LED_GPIO_PORT, LED_GPIO_PIN)
    \n#define LED_OFF() GPIO_SetBits(LED_GPIO_PORT, LED_GPIO_PIN)<\/p>\n

    \/* USART1 Configuration *\/
    \n#define DEBUG_USARTx USART1
    \n#define DEBUG_USARTx_CLK RCC_APB2PERIPH_USART1
    \n#define DEBUG_USARTx_GPIO_PORT GPIOA
    \n#define DEBUG_USARTx_GPIO_CLK RCC_APB2PERIPH_GPIOA
    \n#define DEBUG_USARTx_GPIO_PIN_TX GPIO_Pin_9
    \n#define DEBUG_USARTx_GPIO_PIN_RX GPIO_Pin_10<\/p>\n

    #endif \/* __BOARD_CONFIG_H *\/<\/p>\n

    \n \u6b64\u8bbe\u8ba1\u5c06\u786c\u4ef6\u7ec6\u8282（\u5982LED\u63a5PC13）\u4e0e\u8f6f\u4ef6\u903b\u8f91（<\/p>\n

    LED_ON()<\/p>\n

    ）\u5f7b\u5e95\u5206\u79bb\u3002\u5f53\u66f4\u6362\u5f00\u53d1\u677f\u65f6，\u4ec5\u9700\u4fee\u6539<\/p>\n

    board_config.h<\/p>\n

    ，<\/p>\n

    app_usart.c<\/p>\n

    \u7b49\u4e0a\u5c42\u4ee3\u7801\u65e0\u9700\u4efb\u4f55\u6539\u52a8，\u771f\u6b63\u5b9e\u73b0\u201c\u786c\u4ef6\u65e0\u5173\u201d\u3002\n<\/p>\n

    \n 7.3 \u521d\u59cb\u5316\u6d41\u7a0b\u7684\u786e\u5b9a\u6027\u4fdd\u969c
    \n<\/h4>\n

    \n \u56fa\u4ef6\u5e93\u672a\u89c4\u5b9a\u521d\u59cb\u5316\u987a\u5e8f，\u4f46F10x\u786c\u4ef6\u6709\u4e25\u683c\u4f9d\u8d56：<\/p>\n

    1.<\/p>\n

    \u7cfb\u7edf\u65f6\u949f<\/p>\n

    ：<\/p>\n

    SystemInit()<\/p>\n

    \u5fc5\u987b\u5728<\/p>\n

    main()<\/p>\n

    \u5f00\u5934\u7acb\u5373\u6267\u884c<\/p>\n

    2.<\/p>\n

    \u5916\u8bbe\u65f6\u949f<\/p>\n

    ：<\/p>\n

    RCC_APBxPeriphClockCmd()<\/p>\n

    \u5728\u5bf9\u5e94\u5916\u8bbe\u521d\u59cb\u5316\u524d\u8c03\u7528<\/p>\n

    3.<\/p>\n

    GPIO<\/p>\n

    ：\u5148\u914d\u7f6e\u65f6\u949f，\u518d<\/p>\n

    GPIO_Init()<\/p>\n

    ，\u6700\u540e<\/p>\n

    GPIO_SetBits()<\/p>\n

    \u8bbe\u7f6e\u521d\u59cb\u7535\u5e73<\/p>\n

    4.<\/p>\n

    \u4e2d\u65ad<\/p>\n

    ：<\/p>\n

    NVIC_Init()<\/p>\n

    \u5728<\/p>\n

    EXTI_Init()<\/p>\n

    \u7b49\u5916\u8bbe\u4e2d\u65ad\u4f7f\u80fd\u524d\u8c03\u7528\n<\/p>\n

    \n \u5efa\u8bae\u5728<\/p>\n

    main.c<\/p>\n

    \u4e2d\u6784\u5efa\u786e\u5b9a\u6027\u521d\u59cb\u5316\u5e8f\u5217：\n<\/p>\n

    int main(void) {
    \n \/* 1. System Clock Initialization *\/
    \n SystemInit(); \/\/ From system_stm32f10x.c<\/p>\n

    \/* 2. Peripheral Clocks *\/
    \n RCC_Configuration(); \/\/ Custom function enabling all needed clocks<\/p>\n

    \/* 3. GPIO *\/
    \n GPIO_Configuration(); \/\/ Custom function initializing all GPIO<\/p>\n

    \/* 4. NVIC *\/
    \n NVIC_Configuration(); \/\/ Custom function setting priority groups<\/p>\n

    \/* 5. Peripherals *\/
    \n USART_Configuration(); \/\/ Custom function for USART1
    \n ADC_Configuration(); \/\/ Custom function for ADC1<\/p>\n

    \/* 6. Application Start *\/
    \n while(1) {
    \n \/\/ Main loop
    \n }
    \n}<\/p>\n

    \n \u6b64\u7ed3\u6784\u5c06\u521d\u59cb\u5316\u8d23\u4efb\u660e\u786e\u5212\u5206，\u907f\u514d\u56e0\u987a\u5e8f\u9519\u8bef\u5bfc\u81f4\u7684\u5076\u53d1\u6027\u6545\u969c\u3002\n<\/p>\n

    \n \u6211\u5728\u5b9e\u9645\u9879\u76ee\u4e2d\u66fe\u56e0<\/p>\n

    ADC_Configuration()<\/p>\n

    \u7f6e\u4e8e<\/p>\n

    NVIC_Configuration()<\/p>\n

    \u4e4b\u524d，\u5bfc\u81f4ADC\u8f6c\u6362\u5b8c\u6210\u4e2d\u65ad\u65e0\u6cd5\u89e6\u53d1\u2014\u2014\u56e0\u4e3aNVIC\u5206\u7ec4\u672a\u914d\u7f6e，<\/p>\n

    ADC1_IRQn<\/p>\n

    \u5411\u91cf\u88ab\u5206\u914d\u5230\u9519\u8bef\u7684\u4f18\u5148\u7ea7\u7ec4\u3002\u6b64\u540e\u6240\u6709\u65b0\u9879\u76ee\u5747\u5f3a\u5236\u91c7\u7528\u4e0a\u8ff0\u516d\u6b65\u521d\u59cb\u5316\u6a21\u677f，\u4e09\u5e74\u6765\u672a\u518d\u51fa\u73b0\u6b64\u7c7b\u4f4e\u7ea7\u9519\u8bef\u3002\u56fa\u4ef6\u5e93\u7684\u5a01\u529b\u4e0d\u5728\u4e8e\u5176API\u6570\u91cf，\u800c\u5728\u4e8e\u5f00\u53d1\u8005\u80fd\u5426\u5c06\u5176\u5185\u5728\u903b\u8f91\u8f6c\u5316\u4e3a\u53ef\u9884\u6d4b\u3001\u53ef\u9a8c\u8bc1\u3001\u53ef\u4f20\u627f\u7684\u5de5\u7a0b\u5b9e\u8df5\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"

    1. \u56fa\u4ef6\u5e93\u7684\u672c\u8d28\u4e0e\u5de5\u7a0b\u5b9a\u4f4d\u56fa\u4ef6\u5e93（Standard Peripheral Library，SPL）\u4e0d\u662f\u4e00\u5957\u9ed1\u76d2\u5de5\u5177\u96c6，\u800c\u662fST\u5b98\u65b9\u4e3aSTM32\u7cfb\u5217\u5fae\u63a7\u5236\u5668\u63d0\u4f9b\u7684\u3001\u4ecb\u4e8e\u786c\u4ef6\u5bc4\u5b58\u5668\u64cd\u4f5c\u4e0e\u9ad8\u7ea7\u62bd\u8c61\u6846\u67b6\u4e4b\u95f4\u7684\u4e2d\u95f4\u5c42\u8f6f\u4ef6\u7ec4\u4ef6\u3002\u5b83\u65e2\u4e0d\u7b49\u540c\u4e8eCMSIS\u5185\u6838\u5c42\u7684\u6807\u51c6\u5316\u63a5\u53e3，\u4e5f\u4e0d\u5177\u5907HAL\u5e93\u7684\u8de8\u7cfb\u5217\u517c\u5bb9\u6027\u8bbe\u8ba1，\u5176\u6838\u5fc3\u4ef7\u503c\u5728\u4e8e：\u4ee5C\u8bed\u8a00\u7ed3\u6784\u4f53\u548c\u51fd\u6570\u5c01\u88c5\u7684\u65b9\u5f0f，\u5c06F10x\u7cfb\u5217\u82af\u7247\u5916\u8bbe\u5bc4<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[8817,8818,8816],"topic":[],"class_list":["post-79205","post","type-post","status-publish","format-standard","hentry","category-server","tag-spl","tag-stm32f10x","tag-8816"],"yoast_head":"\nSTM32\u56fa\u4ef6\u5e93\uff08SPL\uff09\u6df1\u5ea6\u89e3\u6790\uff1a\u4ece\u5bc4\u5b58\u5668\u6620\u5c04\u5230\u5de5\u7a0b\u5b9e\u8df5 - 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