| \n 0x00018000<\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n \n \u6b64\u5904\u9700\u7279\u522b\u5f3a\u8c03\u4e00\u4e2a\u5173\u952e\u7ec6\u8282：<\/p>\n APB1\u7684\u57fa\u5730\u5740<\/p>\n 0x40000000<\/p>\n ，\u5373\u662f\u6574\u4e2a\u5916\u8bbeBlock 2\u7684\u8d77\u59cb\u5730\u5740，\u56e0\u6b64\u5b83\u4e5f\u88ab\u79f0\u4f5c\u201c\u5916\u8bbe\u57fa\u5730\u5740\u201d（Peripheral Base Address）<\/p>\n \u3002\u8fd9\u610f\u5473\u7740，\u6240\u6709\u5916\u8bbe\u7684\u7edd\u5bf9\u5730\u5740，\u90fd\u53ef\u4ee5\u7edf\u4e00\u8868\u793a\u4e3a\u201c\u5916\u8bbe\u57fa\u5730\u5740 + \u603b\u7ebf\u504f\u79fb + \u5916\u8bbe\u504f\u79fb\u201d\u3002\u4f8b\u5982，APB2\u7684\u57fa\u5730\u5740<\/p>\n 0x40010000<\/p>\n ，\u53ef\u4ee5\u88ab\u770b\u4f5c\u662f<\/p>\n 0x40000000 + 0x00010000<\/p>\n ；\u540c\u7406，AHB\u7684\u57fa\u5730\u5740<\/p>\n 0x40018000<\/p>\n ，\u5219\u662f<\/p>\n 0x40000000 + 0x00018000<\/p>\n \u3002\u8fd9\u79cd\u8868\u8fbe\u65b9\u5f0f，\u4e3a\u540e\u7eed\u7684C\u8bed\u8a00\u5b8f\u5b9a\u4e49\u63d0\u4f9b\u4e86\u6e05\u6670\u7684\u6570\u5b66\u57fa\u7840\u3002\n<\/p>\n \n \u4ee5GPIO\u7aef\u53e3\u4e3a\u4f8b，\u5176\u5728\u53c2\u8003\u624b\u518c\u7684\u201cPeripheral memory map\u201d\u8868\u683c\u4e2d\u88ab\u660e\u786e\u5217\u51fa\u3002GPIOA\u7684\u57fa\u5730\u5740\u4e3a<\/p>\n 0x40010800<\/p>\n ，GPIOB\u4e3a<\/p>\n 0x40010C00<\/p>\n ，GPIOC\u4e3a<\/p>\n 0x40011000<\/p>\n ，GPIOD\u4e3a<\/p>\n 0x40011400<\/p>\n ，GPIOE\u4e3a<\/p>\n 0x40011800<\/p>\n \u3002\u89c2\u5bdf\u8fd9\u4e9b\u5730\u5740，\u53ef\u4ee5\u53d1\u73b0\u4e00\u4e2a\u4e25\u683c\u7684\u89c4\u5f8b：\u5b83\u4eec\u5747\u4f4d\u4e8eAPB2\u603b\u7ebf\u4e0a（\u56e0\u4e3a<\/p>\n 0x40010800<\/p>\n ><\/p>\n 0x40010000<\/p>\n \u4e14 <<\/p>\n 0x40018000<\/p>\n ），\u5e76\u4e14\u76f8\u90bb\u7aef\u53e3\u4e4b\u95f4\u76f8\u5dee<\/p>\n 0x00000400<\/p>\n （\u53731024\u5b57\u8282）\u3002\u8fd9\u5370\u8bc1\u4e86\u624b\u518c\u4e2d\u5173\u4e8e\u201cAPB2\u603b\u7ebf\u6302\u8f7dGPIOA-E\u201d\u7684\u63cf\u8ff0\u3002\u8fdb\u4e00\u6b65\u8ba1\u7b97\u5176\u76f8\u5bf9\u4e8eAPB2\u57fa\u5730\u5740<\/p>\n 0x40010000<\/p>\n \u7684\u504f\u79fb\u91cf：<\/p>\n – GPIOA:<\/p>\n 0x40010800 – 0x40010000 = 0x00000800<\/p>\n – GPIOB:<\/p>\n 0x40010C00 – 0x40010000 = 0x00000C00<\/p>\n – GPIOC:<\/p>\n 0x40011000 – 0x40010000 = 0x00001000<\/p>\n \n \u8fd9\u4e2a<\/p>\n 0x00000800<\/p>\n \u3001<\/p>\n 0x00000C00<\/p>\n \u7b49\u6570\u503c，\u5c31\u662fGPIO\u5916\u8bbe\u5728APB2\u603b\u7ebf\u4e0a\u7684\u201c\u5916\u8bbe\u504f\u79fb\u91cf\u201d\u3002\u5b83\u4e0e\u603b\u7ebf\u504f\u79fb\u91cf<\/p>\n 0x00010000<\/p>\n \u76f8\u52a0，\u4fbf\u5f97\u5230\u4e86GPIOA\/B\/C\u7684\u7edd\u5bf9\u5730\u5740\u3002\u8fd9\u79cd\u5206\u5c42\u8ba1\u7b97\u6cd5，\u662f\u6784\u5efa\u53ef\u7ef4\u62a4\u3001\u53ef\u6269\u5c55\u5bc4\u5b58\u5668\u6620\u5c04\u4f53\u7cfb\u7684\u5173\u952e\u3002\u5728C\u8bed\u8a00\u4e2d，\u6211\u4eec\u5c06\u5176\u89c4\u8303\u5316\u4e3a\u4e00\u7cfb\u5217\u5b8f\u5b9a\u4e49：\n<\/p>\n \/* \u5b9a\u4e49\u5916\u8bbe\u57fa\u5730\u5740 *\/
\n#define PERIPH_BASE ((uint32_t)0x40000000)<\/p>\n \/* \u5b9a\u4e49\u5404\u603b\u7ebf\u57fa\u5730\u5740（\u76f8\u5bf9\u4e8ePERIPH_BASE\u7684\u504f\u79fb） *\/
\n#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000)
\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
\n#define AHBPERIPH_BASE (PERIPH_BASE + 0x00018000)<\/p>\n \/* \u5b9a\u4e49GPIO\u5916\u8bbe\u57fa\u5730\u5740（\u76f8\u5bf9\u4e8eAPB2PERIPH_BASE\u7684\u504f\u79fb） *\/
\n#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800)
\n#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00)
\n#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000)
\n#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400)
\n#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800)<\/p>\n \n \u4e0a\u8ff0\u5b8f\u5b9a\u4e49\u7684\u7cbe\u5999\u4e4b\u5904\u5728\u4e8e，\u5b83\u5b8c\u5168\u590d\u73b0\u4e86\u786c\u4ef6\u5730\u5740\u7a7a\u95f4\u7684\u7269\u7406\u7ed3\u6784\u3002<\/p>\n GPIOB_BASE<\/p>\n \u7684\u8ba1\u7b97\u8fc7\u7a0b<\/p>\n 0x40000000 + 0x00010000 + 0x00000C00 = 0x40010C00<\/p>\n ，\u4e0e\u624b\u518c\u4e2d\u7ed9\u51fa\u7684\u5730\u5740\u4e25\u4e1d\u5408\u7f1d\u3002\u8fd9\u79cd\u201c\u6240\u89c1\u5373\u6240\u5f97\u201d\u7684\u5b9a\u4e49\u65b9\u5f0f，\u4f7f\u5f97\u4ee3\u7801\u5177\u5907\u4e86\u6781\u5f3a\u7684\u81ea\u89e3\u91ca\u6027\u3002\u5f53\u4e00\u4e2a\u5de5\u7a0b\u5e08\u770b\u5230<\/p>\n GPIOB_BASE<\/p>\n \u65f6，\u65e0\u9700\u67e5\u9605\u4efb\u4f55\u6587\u6863，\u4ec5\u51ed\u5b8f\u540d\u5373\u53ef\u63a8\u65ad\u51fa\u5176\u7269\u7406\u4f4d\u7f6e\u548c\u6240\u5c5e\u603b\u7ebf，\u8fd9\u662f\u9ad8\u8d28\u91cf\u5d4c\u5165\u5f0f\u4ee3\u7801\u7684\u91cd\u8981\u6807\u5fd7\u3002\n<\/p>\n \n 3. \u5bc4\u5b58\u5668\u7ed3\u6784\u4f53\u5c01\u88c5：\u4ece\u5730\u5740\u5230\u53ef\u8bfb\u4ee3\u7801\u7684\u8303\u5f0f\u8dc3\u8fc1
\n<\/h3>\n\n \u4ec5\u4ec5\u5b9a\u4e49\u5916\u8bbe\u7684\u57fa\u5730\u5740，\u8ddd\u79bb\u7f16\u5199\u53ef\u7ef4\u62a4\u7684\u9a71\u52a8\u4ee3\u7801\u4ecd\u6709\u5de8\u5927\u9e3f\u6c9f\u3002\u8bbe\u60f3\u4e00\u4e0b，\u82e5\u8981\u914d\u7f6eGPIOB\u7684\u7b2c10\u5f15\u811a\u4e3a\u63a8\u633d\u8f93\u51fa\u6a21\u5f0f，\u6211\u4eec\u9700\u8981\u5411\u5176\u201c\u7aef\u53e3\u914d\u7f6e\u4f4e\u5bc4\u5b58\u5668\u201d（CRL）\u5199\u5165\u7279\u5b9a\u503c\u3002\u6839\u636e\u624b\u518c，CRL\u7684\u504f\u79fb\u5730\u5740\u4e3a<\/p>\n 0x00<\/p>\n ，\u5176\u7edd\u5bf9\u5730\u5740\u5373\u4e3a<\/p>\n GPIOB_BASE + 0x00 = 0x40010C00<\/p>\n \u3002\u6700\u539f\u59cb\u7684\u5199\u6cd5\u662f：\n<\/p>\n *(volatile uint32_t*)(0x40010C00) = 0x00000003; \/\/ \u914d\u7f6ePB10\u4e3a\u63a8\u633d\u8f93\u51fa<\/p>\n \n \u8fd9\u79cd\u65b9\u5f0f\u867d\u80fd\u5de5\u4f5c，\u4f46\u5176\u7f3a\u9677\u663e\u800c\u6613\u89c1：<\/p>\n \u5730\u5740\u6570\u5b57\u6beb\u65e0\u8bed\u4e49，\u65e0\u6cd5\u4f53\u73b0\u529f\u80fd\u610f\u56fe，\u4e14\u6781\u6613\u56e0\u7b14\u8bef\u5bfc\u81f4\u707e\u96be\u6027\u9519\u8bef<\/p>\n \u3002\u5bc4\u5b58\u5668\u6620\u5c04\u7684\u7b2c\u4e8c\u9636\u6bb5，\u4fbf\u662f\u5f15\u5165C\u8bed\u8a00\u7684\u7ed3\u6784\u4f53（struct）\u673a\u5236，\u5c06\u4e00\u7ec4\u5177\u6709\u903b\u8f91\u5173\u8054\u7684\u5bc4\u5b58\u5668，\u5c01\u88c5\u6210\u4e00\u4e2a\u5177\u6709\u660e\u786e\u6210\u5458\u540d\u79f0\u7684\u590d\u5408\u6570\u636e\u7c7b\u578b\u3002\u8fd9\u4e0d\u4ec5\u662f\u8bed\u6cd5\u7cd6，\u66f4\u662f\u4e00\u79cd\u5de5\u7a0b\u8303\u5f0f\u7684\u5347\u7ea7，\u5b83\u5c06\u201c\u64cd\u4f5c\u5185\u5b58\u5730\u5740\u201d\u7684\u5e95\u5c42\u884c\u4e3a，\u62bd\u8c61\u4e3a\u201c\u64cd\u4f5c\u7ed3\u6784\u4f53\u6210\u5458\u201d\u7684\u9ad8\u5c42\u8bed\u4e49\u3002\n<\/p>\n \n STM32\u7684\u6bcf\u4e2aGPIO\u7aef\u53e3，\u5176\u5bc4\u5b58\u5668\u5217\u8868\u5728\u624b\u518c\u4e2d\u88ab\u6e05\u6670\u5730\u5b9a\u4e49\u4e3a\u4e00\u4e2a\u8fde\u7eed\u7684\u3001\u56fa\u5b9a\u5927\u5c0f\u7684\u7ed3\u6784\u3002\u4ee5GPIOB\u4e3a\u4f8b，\u5176\u6838\u5fc3\u5bc4\u5b58\u5668\u6309\u987a\u5e8f\u6392\u5217\u5982\u4e0b（\u5747\u4e3a32\u4f4d）：<\/p>\n 1.<\/p>\n CRL<\/p>\n (Port Configuration Register Low): \u504f\u79fb<\/p>\n 0x00<\/p>\n 2.<\/p>\n CRH<\/p>\n (Port Configuration Register High): \u504f\u79fb<\/p>\n 0x04<\/p>\n 3.<\/p>\n IDR<\/p>\n (Port Input Data Register): \u504f\u79fb<\/p>\n 0x08<\/p>\n 4.<\/p>\n ODR<\/p>\n (Port Output Data Register): \u504f\u79fb<\/p>\n 0x0C<\/p>\n 5.<\/p>\n BSRR<\/p>\n (Port Bit Set\/Reset Register): \u504f\u79fb<\/p>\n 0x10<\/p>\n 6.<\/p>\n BRR<\/p>\n (Port Bit Reset Register): \u504f\u79fb<\/p>\n 0x14<\/p>\n 7.<\/p>\n LCKR<\/p>\n (Port Configuration Lock Register): \u504f\u79fb<\/p>\n 0x18<\/p>\n \n \u8fd9\u4e9b\u5bc4\u5b58\u5668\u5728\u5185\u5b58\u4e2d\u5360\u636e<\/p>\n 0x00<\/p>\n \u5230<\/p>\n 0x1C<\/p>\n \u517128\u5b57\u8282（7\u4e2a\u5bc4\u5b58\u5668 \u00d7 4\u5b57\u8282），\u6784\u6210\u4e00\u4e2a\u5b8c\u7f8e\u7684\u3001\u7d27\u51d1\u7684\u7ed3\u6784\u4f53\u5e03\u5c40\u3002\u6211\u4eec\u53ef\u4ee5\u636e\u6b64\u5b9a\u4e49\u4e00\u4e2a\u540d\u4e3a<\/p>\n GPIO_TypeDef<\/p>\n \u7684\u7ed3\u6784\u4f53：\n<\/p>\n typedef struct {
\n __IO uint32_t CRL; \/*!< Port configuration register low, Address offset: 0x00 *\/
\n __IO uint32_t CRH; \/*!< Port configuration register high, Address offset: 0x04 *\/
\n __IO uint32_t IDR; \/*!< Port input data register, Address offset: 0x08 *\/
\n __IO uint32_t ODR; \/*!< Port output data register, Address offset: 0x0C *\/
\n __IO uint32_t BSRR; \/*!< Port bit set\/reset register, Address offset: 0x10 *\/
\n __IO uint32_t BRR; \/*!< Port bit reset register, Address offset: 0x14 *\/
\n __IO uint32_t LCKR; \/*!< Port configuration lock register, Address offset: 0x18 *\/
\n} GPIO_TypeDef;<\/p>\n \n \u6b64\u5904<\/p>\n __IO<\/p>\n \u662f\u4e00\u4e2a\u7531CMSIS\u6807\u51c6\u5b9a\u4e49\u7684\u5b8f，\u5c55\u5f00\u540e\u4e3a<\/p>\n volatile<\/p>\n \u5173\u952e\u5b57，\u5176\u4f5c\u7528\u81f3\u5173\u91cd\u8981：\u5b83\u544a\u8bc9\u7f16\u8bd1\u5668，\u8be5\u53d8\u91cf\u6240\u6307\u5411\u7684\u5185\u5b58\u5185\u5bb9\u53ef\u80fd\u88ab\u786c\u4ef6（\u800c\u975e\u4ec5\u7531\u8f6f\u4ef6）\u968f\u65f6\u4fee\u6539，\u56e0\u6b64\u7981\u6b62\u7f16\u8bd1\u5668\u5bf9\u8be5\u53d8\u91cf\u8fdb\u884c\u4efb\u4f55\u4f18\u5316（\u5982\u7f13\u5b58\u5230\u5bc4\u5b58\u5668\u3001\u5220\u9664\u5197\u4f59\u8bfb\u53d6\u7b49），\u786e\u4fdd\u6bcf\u6b21\u8bbf\u95ee\u90fd\u662f\u771f\u5b9e\u7684\u5185\u5b58\u8bfb\u5199\u3002\n<\/p>\n \n \u7ed3\u6784\u4f53\u5b9a\u4e49\u5b8c\u6210\u540e，\u5bc4\u5b58\u5668\u6620\u5c04\u7684\u6700\u540e\u4e00\u6b65，\u4fbf\u662f\u5c06\u5916\u8bbe\u7684\u57fa\u5730\u5740（\u4e00\u4e2a\u7eaf\u6570\u5b57）\u5f3a\u5236\u8f6c\u6362\u4e3a\u8be5\u7ed3\u6784\u4f53\u7c7b\u578b\u7684\u6307\u9488\u3002\u8fd9\u5229\u7528\u4e86C\u8bed\u8a00\u6307\u9488\u7684\u201c\u5730\u5740\u91cd\u89e3\u91ca\u201d\u80fd\u529b：\n<\/p>\n #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)<\/p>\n \n \u8fd9\u6761\u5b8f\u5b9a\u4e49\u7684\u542b\u4e49\u662f：\u5c06<\/p>\n GPIOB_BASE<\/p>\n （\u5373<\/p>\n 0x40010C00<\/p>\n ）\u8fd9\u4e2a32\u4f4d\u65e0\u7b26\u53f7\u6574\u6570，\u89c6\u4e3a\u4e00\u4e2a<\/p>\n GPIO_TypeDef<\/p>\n \u7ed3\u6784\u4f53\u7684\u9996\u5730\u5740，\u5e76\u521b\u5efa\u4e00\u4e2a\u6307\u5411\u5b83\u7684\u6307\u9488\u3002\u81ea\u6b64，<\/p>\n GPIOB<\/p>\n \u4e0d\u518d\u662f\u4e00\u4e2a\u51b0\u51b7\u7684\u6570\u5b57，\u800c\u662f\u4e00\u4e2a\u62e5\u67097\u4e2a\u5177\u540d\u6210\u5458\u7684\u3001\u53ef\u88ab\u76f4\u63a5\u64cd\u4f5c\u7684\u5bf9\u8c61\u3002\u914d\u7f6ePB10\u7684\u64cd\u4f5c，\u4fbf\u4ece\u6666\u6da9\u7684\u5730\u5740\u64cd\u4f5c，\u8f6c\u53d8\u4e3a\u76f4\u89c2\u7684\u7ed3\u6784\u4f53\u6210\u5458\u8bbf\u95ee：\n<\/p>\n GPIOB->CRL &= ~(0xFU << (10 * 4)); \/\/ \u6e05\u9664PB10\u76844\u4f4d\u914d\u7f6e\u4f4d
\nGPIOB->CRL |= (0x3U << (10 * 4)); \/\/ \u8bbe\u7f6ePB10\u4e3a\u63a8\u633d\u8f93\u51fa\u6a21\u5f0f（0x03）<\/p>\n \n \u8fd9\u6bb5\u4ee3\u7801\u7684\u53ef\u8bfb\u6027\u4e0e\u5065\u58ee\u6027，\u8fdc\u8d85\u539f\u59cb\u7684<\/p>\n *(uint32_t*)0x40010C00 = …<\/p>\n \u3002\u5b83\u660e\u786e\u8868\u8fbe\u4e86\u64cd\u4f5c\u610f\u56fe（\u914d\u7f6eCRL\u5bc4\u5b58\u5668）\u3001\u64cd\u4f5c\u5bf9\u8c61（PB10）\u548c\u64cd\u4f5c\u7ed3\u679c（\u63a8\u633d\u8f93\u51fa）\u3002\u66f4\u91cd\u8981\u7684\u662f，\u5b83\u5c06\u786c\u4ef6\u7ec6\u8282（\u5730\u5740\u8ba1\u7b97）\u4e0e\u4e1a\u52a1\u903b\u8f91（\u914d\u7f6e\u5f15\u811a）\u5f7b\u5e95\u89e3\u8026\u3002\u5f53\u9700\u8981\u914d\u7f6e\u5176\u4ed6\u5f15\u811a\u65f6，\u53ea\u9700\u6539\u53d8\u4f4d\u79fb\u91cf<\/p>\n (n * 4)<\/p>\n ，\u800c\u65e0\u9700\u91cd\u65b0\u8ba1\u7b97\u4efb\u4f55\u5730\u5740\u3002\u8fd9\u79cd\u5c01\u88c5，\u662f\u5d4c\u5165\u5f0f\u8f6f\u4ef6\u5de5\u7a0b\u5316\u3001\u6a21\u5757\u5316\u7684\u6838\u5fc3\u5b9e\u8df5\u3002\n<\/p>\n \n 4. \u5bc4\u5b58\u5668\u4f4d\u64cd\u4f5c：\u539f\u5b50\u6027\u3001\u5b89\u5168\u6027\u7684\u5de5\u7a0b\u5b9e\u73b0
\n<\/h3>\n\n \u5728\u5b8c\u6210\u4e86\u5bc4\u5b58\u5668\u7684\u7ed3\u6784\u4f53\u5c01\u88c5\u540e，\u5bf9\u5355\u4e2a\u5bc4\u5b58\u5668\u4f4d\u7684\u7cbe\u786e\u63a7\u5236，\u6210\u4e3a\u9a71\u52a8\u5f00\u53d1\u4e2d\u6700\u4e3a\u9891\u7e41\u4e5f\u6700\u4e3a\u5173\u952e\u7684\u64cd\u4f5c\u3002STM32\u7684\u8bb8\u591a\u5bc4\u5b58\u5668（\u5982<\/p>\n ODR<\/p>\n \u3001<\/p>\n BSRR<\/p>\n \u3001<\/p>\n BRR<\/p>\n ）\u7684\u8bbe\u8ba1\u54f2\u5b66，\u662f\u652f\u6301\u5bf9\u4efb\u610f\u4e00\u4f4d\u6216\u591a\u4f4d\u8fdb\u884c\u201c\u7f6e\u4f4d\u201d（Set）\u6216\u201c\u6e05\u96f6\u201d（Reset），\u540c\u65f6\u4fdd\u8bc1\u5176\u4ed6\u4f4d\u7684\u72b6\u6001\u4e0d\u53d7\u5f71\u54cd\u3002\u8fd9\u5e76\u975e\u4e00\u4e2a\u7b80\u5355\u7684\u8d4b\u503c\u95ee\u9898，\u800c\u662f\u4e00\u4e2a\u6d89\u53ca\u5e76\u53d1\u5b89\u5168\u3001\u786c\u4ef6\u7279\u6027\u548cC\u8bed\u8a00\u4f4d\u8fd0\u7b97\u6280\u5de7\u7684\u7efc\u5408\u5de5\u7a0b\u8bfe\u9898\u3002\n<\/p>\n \n \u6700\u76f4\u89c2\u7684\u9519\u8bef\u505a\u6cd5，\u662f\u76f4\u63a5\u5bf9\u6574\u4e2a\u5bc4\u5b58\u5668\u8fdb\u884c\u8d4b\u503c\u3002\u4f8b\u5982，\u8981\u5c06GPIOB\u7684\u7b2c10\u4f4d（PB10）\u8bbe\u7f6e\u4e3a\u9ad8\u7535\u5e73，\u6709\u4eba\u4f1a\u5199\u51fa：\n<\/p>\n GPIOB->ODR = 1U << 10; \/\/ \u9519\u8bef！\u4f1a\u5c06ODR\u5176\u4ed615\u4f4d\u5168\u90e8\u6e05\u96f6<\/p>\n \n \u6b64\u64cd\u4f5c\u7684\u95ee\u9898\u5728\u4e8e，<\/p>\n ODR<\/p>\n （Output Data Register）\u662f\u4e00\u4e2a16\u4f4d\u5bc4\u5b58\u5668，\u5176\u6bcf\u4e00\u4f4d\u5bf9\u5e94\u4e00\u4e2aGPIO\u5f15\u811a\u7684\u8f93\u51fa\u7535\u5e73\u3002<\/p>\n 1U << 10<\/p>\n \u7684\u7ed3\u679c\u662f<\/p>\n 0x0400<\/p>\n ，\u5373\u53ea\u6709\u7b2c10\u4f4d\u4e3a1，\u5176\u4f59\u4f4d\u5168\u4e3a0\u3002\u6267\u884c\u6b64\u8d4b\u503c\u540e，<\/p>\n ODR<\/p>\n \u7684\u503c\u53d8\u4e3a<\/p>\n 0x0400<\/p>\n ，\u8fd9\u610f\u5473\u7740PB0-PB9\u548cPB11-PB15\u7684\u8f93\u51fa\u72b6\u6001\u5168\u90e8\u88ab\u5f3a\u5236\u62c9\u4f4e\u3002\u8fd9\u5728\u591a\u5f15\u811a\u534f\u540c\u5de5\u4f5c\u7684\u7cfb\u7edf\u4e2d\u662f\u4e0d\u53ef\u63a5\u53d7\u7684，\u56e0\u4e3a\u5b83\u7834\u574f\u4e86\u5176\u4ed6\u5f15\u811a\u7684\u5f53\u524d\u72b6\u6001，\u5c5e\u4e8e\u5178\u578b\u7684\u201c\u526f\u4f5c\u7528\u201d\u3002\n<\/p>\n \n \u6b63\u786e\u7684\u505a\u6cd5，\u662f\u5229\u7528C\u8bed\u8a00\u7684\u4f4d\u8fd0\u7b97\u7b26，\u5b9e\u73b0\u5bf9\u76ee\u6807\u4f4d\u7684\u201c\u8bfb-\u4fee\u6539-\u5199\u201d（Read-Modify-Write）\u539f\u5b50\u64cd\u4f5c\u3002\u5176\u6838\u5fc3\u601d\u60f3\u662f：<\/p>\n \u5148\u8bfb\u53d6\u5bc4\u5b58\u5668\u7684\u5f53\u524d\u503c，\u7136\u540e\u5728\u5185\u5b58\u4e2d\u5bf9\u5176\u8fdb\u884c\u4f4d\u8fd0\u7b97\u4fee\u6539，\u6700\u540e\u5c06\u65b0\u503c\u5199\u56de\u5bc4\u5b58\u5668<\/p>\n \u3002\u5bf9\u4e8e\u201c\u7f6e\u4f4d\u201d\u64cd\u4f5c，\u4f7f\u7528\u6309\u4f4d\u6216（<\/p>\n |<\/p>\n ）：\n<\/p>\n GPIOB->ODR |= (1U << 10); \/\/ \u6b63\u786e：\u4ec5\u5c06PB10\u7f6e1，\u5176\u4ed6\u4f4d\u4fdd\u6301\u4e0d\u53d8<\/p>\n \n \u5bf9\u4e8e\u201c\u6e05\u96f6\u201d\u64cd\u4f5c，\u4f7f\u7528\u6309\u4f4d\u4e0e（<\/p>\n &<\/p>\n ）\u914d\u5408\u53d6\u53cd（<\/p>\n ~<\/p>\n ）：\n<\/p>\n GPIOB->ODR &= ~(1U << 10); \/\/ \u6b63\u786e：\u4ec5\u5c06PB10\u6e05\u96f6，\u5176\u4ed6\u4f4d\u4fdd\u6301\u4e0d\u53d8<\/p>\n \n \u8fd9\u4e24\u6761\u8bed\u53e5\u7684\u6c47\u7f16\u5b9e\u73b0，\u901a\u5e38\u4f1a\u88ab\u7f16\u8bd1\u5668\u4f18\u5316\u4e3a\u4e00\u6761<\/p>\n OR<\/p>\n \u6216<\/p>\n AND<\/p>\n \u6307\u4ee4，\u5176\u6548\u7387\u6781\u9ad8\u3002\u7136\u800c，\u5728\u67d0\u4e9b\u5bf9\u5b9e\u65f6\u6027\u8981\u6c42\u6781\u9ad8\u7684\u573a\u666f\u4e0b，\u6216\u8005\u5f53\u5bc4\u5b58\u5668\u672c\u8eab\u4e0d\u652f\u6301\u539f\u5b50\u8bfb-\u4fee\u6539-\u5199\u65f6（\u5982\u67d0\u4e9b\u72b6\u6001\u5bc4\u5b58\u5668），\u8fd9\u79cd\u4e09\u6b65\u64cd\u4f5c\u4ecd\u53ef\u80fd\u5b58\u5728\u7ade\u6001\u98ce\u9669\u3002STM32F103\u4e3a\u6b64\u63d0\u4f9b\u4e86\u786c\u4ef6\u7ea7\u7684\u89e3\u51b3\u65b9\u6848\u2014\u2014<\/p>\n BSRR<\/p>\n （Bit Set\/Reset Register）\u5bc4\u5b58\u5668\u3002<\/p>\n BSRR<\/p>\n \u662f\u4e00\u4e2a32\u4f4d\u5bc4\u5b58\u5668，\u5176\u9ad816\u4f4d（bit[31:16]）\u7528\u4e8e\u201c\u7f6e\u4f4d\u201d，\u4f4e16\u4f4d（bit[15:0]）\u7528\u4e8e\u201c\u6e05\u96f6\u201d\u3002\u5411<\/p>\n BSRR<\/p>\n \u7684\u67d0\u4e00\u4f4d\u5199\u51651，\u5c06\u7acb\u5373\u89e6\u53d1\u5bf9\u5e94GPIO\u5f15\u811a\u7684\u7f6e\u4f4d\u6216\u6e05\u96f6\u52a8\u4f5c，\u4e14\u8be5\u64cd\u4f5c\u662f\u786c\u4ef6\u539f\u5b50\u7684，\u4e0d\u4f1a\u5f71\u54cd\u5176\u4ed6\u4f4d，\u4e5f\u65e0\u9700\u8bfb\u53d6\u539f\u503c\u3002\n<\/p>\n \/\/ \u4f7f\u7528BSRR\u5b9e\u73b0\u539f\u5b50\u7f6e\u4f4d\u548c\u6e05\u96f6（\u63a8\u8350\u7528\u4e8e\u5173\u952e\u8def\u5f84）
\nGPIOB->BSRR = (1U << 10); \/\/ \u7f6e\u4f4dPB10（\u5199\u5165\u4f4e16\u4f4d）
\nGPIOB->BSRR = (1U << (10 + 16)); \/\/ \u6e05\u96f6PB10（\u5199\u5165\u9ad816\u4f4d）<\/p>\n BSRR<\/p>\n \u7684\u5de7\u5999\u4e4b\u5904\u5728\u4e8e，\u5b83\u5c06\u201c\u7f6e\u4f4d\u201d\u548c\u201c\u6e05\u96f6\u201d\u8fd9\u4e24\u4e2a\u4e92\u65a5\u7684\u64cd\u4f5c，\u901a\u8fc7\u5730\u5740\u7a7a\u95f4\u7684\u540c\u4e00\u5bc4\u5b58\u5668\u7684\u4e0d\u540c\u4f4d\u57df\u6765\u5206\u79bb，\u4ece\u800c\u89c4\u907f\u4e86\u8f6f\u4ef6\u5c42\u9762\u7684\u8bfb-\u4fee\u6539-\u5199\u7ade\u4e89\u3002\u5728\u5b9e\u9645\u9879\u76ee\u4e2d，\u6211\u66fe\u5728\u4e00\u4e2a\u7535\u673a\u9a71\u52a8\u677f\u4e0a\u9047\u5230\u8fc7\u56e0<\/p>\n ODR<\/p>\n \u76f4\u63a5\u8d4b\u503c\u5bfc\u81f4\u7684PWM\u6ce2\u5f62\u6296\u52a8\u95ee\u9898\u3002\u5c06\u6240\u6709\u5f15\u811a\u63a7\u5236\u903b\u8f91\u5207\u6362\u81f3<\/p>\n BSRR<\/p>\n \u540e，\u6296\u52a8\u5b8c\u5168\u6d88\u5931，\u7cfb\u7edf\u7a33\u5b9a\u6027\u5f97\u5230\u663e\u8457\u63d0\u5347\u3002\u8fd9\u5370\u8bc1\u4e86\u4e00\u4e2a\u7ecf\u9a8c：<\/p>\n \u5728\u5e95\u5c42\u9a71\u52a8\u4e2d，\u4f18\u5148\u9009\u62e9\u786c\u4ef6\u63d0\u4f9b\u7684\u539f\u5b50\u64cd\u4f5c\u539f\u8bed，\u800c\u975e\u4f9d\u8d56\u8f6f\u4ef6\u6a21\u62df，\u662f\u4fdd\u969c\u7cfb\u7edf\u9c81\u68d2\u6027\u7684\u9ec4\u91d1\u6cd5\u5219<\/p>\n \u3002\n<\/p>\n \n 5. \u4ece\u7406\u8bba\u5230\u5b9e\u8df5：\u624b\u5199\u5bc4\u5b58\u5668\u6620\u5c04\u7684\u5b8c\u6574\u4ee3\u7801\u793a\u4f8b
\n<\/h3>\n\n \u7406\u8bba\u7684\u6700\u7ec8\u4ef7\u503c，\u5728\u4e8e\u6307\u5bfc\u5b9e\u8df5\u3002\u4e0b\u9762，\u6211\u4eec\u5c06\u524d\u8ff0\u6240\u6709\u539f\u7406，\u6574\u5408\u4e3a\u4e00\u4efd\u5b8c\u6574\u7684\u3001\u53ef\u76f4\u63a5\u7f16\u8bd1\u8fd0\u884c\u7684\u5bc4\u5b58\u5668\u6620\u5c04\u5934\u6587\u4ef6（<\/p>\n stm32f103xx.h<\/p>\n \u7684\u7b80\u5316\u7248）\u3002\u8fd9\u4efd\u4ee3\u7801\u5e76\u975e\u4e3a\u4e86\u66ff\u4ee3\u5b98\u65b9\u56fa\u4ef6\u5e93，\u800c\u662f\u4e3a\u4e86\u63ed\u793a\u5176\u5185\u90e8\u6784\u9020，\u8ba9\u5f00\u53d1\u8005\u771f\u6b63\u7406\u89e3\u201c\u4e3a\u4ec0\u4e48\u8fd9\u6837\u5199\u201d\u3002\n<\/p>\n #ifndef __STM32F103XX_H
\n#define __STM32F103XX_H<\/p>\n #include <stdint.h><\/p>\n \/* \u5b9a\u4e49volatile\u5173\u952e\u5b57，\u786e\u4fdd\u5185\u5b58\u8bbf\u95ee\u4e0d\u88ab\u4f18\u5316 *\/
\n#ifndef __IO
\n#define __IO volatile
\n#endif<\/p>\n \/* \u5b9a\u4e49\u5916\u8bbe\u57fa\u5730\u5740 *\/
\n#define PERIPH_BASE ((uint32_t)0x40000000)<\/p>\n \/* \u5b9a\u4e49\u5404\u603b\u7ebf\u57fa\u5730\u5740 *\/
\n#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000)
\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
\n#define AHBPERIPH_BASE (PERIPH_BASE + 0x00018000)<\/p>\n \/* \u5b9a\u4e49GPIO\u5916\u8bbe\u57fa\u5730\u5740 *\/
\n#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800)
\n#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00)
\n#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000)
\n#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400)
\n#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800)<\/p>\n \/* \u5b9a\u4e49GPIO\u5bc4\u5b58\u5668\u7ed3\u6784\u4f53 *\/
\ntypedef struct {
\n __IO uint32_t CRL; \/*!< Port configuration register low, Address offset: 0x00 *\/
\n __IO uint32_t CRH; \/*!< Port configuration register high, Address offset: 0x04 *\/
\n __IO uint32_t IDR; \/*!< Port input data register, Address offset: 0x08 *\/
\n __IO uint32_t ODR; \/*!< Port output data register, Address offset: 0x0C *\/
\n __IO uint32_t BSRR; \/*!< Port bit set\/reset register, Address offset: 0x10 *\/
\n __IO uint32_t BRR; \/*!< Port bit reset register, Address offset: 0x14 *\/
\n __IO uint32_t LCKR; \/*!< Port configuration lock register, Address offset: 0x18 *\/
\n} GPIO_TypeDef;<\/p>\n \/* \u5b9a\u4e49GPIO\u7aef\u53e3\u6307\u9488 *\/
\n#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
\n#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
\n#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
\n#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
\n#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)<\/p>\n \/* \u5b9a\u4e49RCC（Reset and Clock Control）\u5916\u8bbe\u57fa\u5730\u5740\u53ca\u7ed3\u6784\u4f53（\u4f5c\u4e3a\u5ef6\u4f38\u793a\u4f8b） *\/
\n#define RCC_BASE (APB2PERIPH_BASE + 0x00001000)<\/p>\n typedef struct {
\n __IO uint32_t CR; \/*!< RCC clock control register, Address offset: 0x00 *\/
\n __IO uint32_t CFGR; \/*!< RCC clock configuration register, Address offset: 0x04 *\/
\n __IO uint32_t CIR; \/*!< RCC clock interrupt register, Address offset: 0x08 *\/
\n __IO uint32_t APB2RSTR; \/*!< RCC APB2 peripheral reset register, Address offset: 0x0C *\/
\n __IO uint32_t APB1RSTR; \/*!< RCC APB1 peripheral reset register, Address offset: 0x10 *\/
\n __IO uint32_t AHBENR; \/*!< RCC AHB peripheral clock enable register, Address offset: 0x14 *\/
\n __IO uint32_t APB2ENR; \/*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 *\/
\n __IO uint32_t APB1ENR; \/*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C *\/
\n __IO uint32_t BDCR; \/*!< RCC Backup domain control register, Address offset: 0x20 *\/
\n __IO uint32_t CSR; \/*!< RCC clock control & status register, Address offset: 0x24 *\/
\n} RCC_TypeDef;<\/p>\n #define RCC ((RCC_TypeDef *) RCC_BASE)<\/p>\n \/* \u51fd\u6570\u58f0\u660e：\u4e00\u4e2a\u7b80\u5355\u7684GPIO\u521d\u59cb\u5316\u51fd\u6570 *\/
\nvoid GPIO_Init(void);<\/p>\n #endif \/* __STM32F103XX_H *\/<\/p>\n \n \u8fd9\u662f\u4e00\u4e2a\u7eaf\u7cb9\u7684\u5934\u6587\u4ef6，\u5b83\u4e0d\u5305\u542b\u4efb\u4f55<\/p>\n .c<\/p>\n \u5b9e\u73b0，\u5176\u5168\u90e8\u5185\u5bb9\u90fd\u662f\u5b8f\u5b9a\u4e49\u548c\u7c7b\u578b\u58f0\u660e\u3002\u5c06\u6b64\u6587\u4ef6\u5305\u542b\u5230\u4f60\u7684\u4e3b\u7a0b\u5e8f\u4e2d，\u4f60\u5c31\u53ef\u4ee5\u50cf\u5b98\u65b9\u5e93\u4e00\u6837，\u4f7f\u7528<\/p>\n GPIOB->ODR |= (1U << 10);<\/p>\n \u8fd9\u6837\u7684\u8bed\u53e5\u3002\u800c<\/p>\n GPIO_Init()<\/p>\n \u51fd\u6570\u7684\u5b9e\u73b0，\u5219\u53ef\u4ee5\u653e\u5728\u4e00\u4e2a<\/p>\n .c<\/p>\n \u6587\u4ef6\u4e2d，\u5b83\u5c06\u8d1f\u8d23\u4f7f\u80fdGPIOB\u7684\u65f6\u949f（\u901a\u8fc7\u64cd\u4f5c<\/p>\n RCC->APB2ENR<\/p>\n \u5bc4\u5b58\u5668）\u3001\u914d\u7f6ePB10\u7684\u6a21\u5f0f（\u901a\u8fc7\u64cd\u4f5c<\/p>\n GPIOB->CRL<\/p>\n \u5bc4\u5b58\u5668）\u7b49\u3002\n<\/p>\n \n \u8fd9\u4efd\u4ee3\u7801\u7684\u6bcf\u4e00\u4e2a\u5b57\u7b26，\u90fd\u5bf9\u5e94\u7740\u82af\u7247\u624b\u518c\u4e2d\u7684\u4e00\u884c\u63cf\u8ff0\u3002\u5f53\u4f60\u4eb2\u624b\u6572\u4e0b<\/p>\n #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00)<\/p>\n \u65f6，\u4f60\u4e0d\u662f\u5728\u5199\u4ee3\u7801，\u800c\u662f\u5728\u4e0e\u7845\u7247\u5bf9\u8bdd；\u5f53\u4f60\u5199\u4e0b<\/p>\n GPIOB->BSRR = (1U << 10);<\/p>\n \u65f6，\u4f60\u4e0d\u662f\u5728\u8c03\u7528\u51fd\u6570，\u800c\u662f\u5728\u5411\u786c\u4ef6\u53d1\u51fa\u4e00\u9053\u7cbe\u786e\u7684\u6307\u4ee4\u3002\u8fd9\u79cd\u201c\u77e5\u5176\u7136，\u66f4\u77e5\u5176\u6240\u4ee5\u7136\u201d\u7684\u638c\u63a7\u611f，\u662f\u5d4c\u5165\u5f0f\u5de5\u7a0b\u5e08\u6700\u5b9d\u8d35\u7684\u804c\u4e1a\u7d20\u517b\u3002\u5728\u6211\u5e26\u8fc7\u7684\u51e0\u4e2a\u65b0\u4eba\u4e2d，\u51e1\u662f\u575a\u6301\u4ece\u8fd9\u4efd\u624b\u5199\u6620\u5c04\u5f00\u59cb\u5b66\u4e60\u7684，\u4e09\u4e2a\u6708\u540e\u90fd\u80fd\u72ec\u7acb\u5b8c\u6210\u590d\u6742\u7684\u5916\u8bbe\u9a71\u52a8\u5f00\u53d1；\u800c\u90a3\u4e9b\u53ea\u6ee1\u8db3\u4e8e\u8c03\u7528HAL\u5e93API\u7684，\u5f80\u5f80\u5728\u9047\u5230\u65f6\u949f\u914d\u7f6e\u9519\u8bef\u6216\u4e2d\u65ad\u5931\u6548\u65f6，\u4fbf\u675f\u624b\u65e0\u7b56\u3002\u8fd9\u5e76\u975e\u6280\u672f\u96be\u5ea6\u7684\u5dee\u5f02，\u800c\u662f\u5de5\u7a0b\u601d\u7ef4\u6df1\u5ea6\u7684\u6839\u672c\u533a\u522b\u3002<\/p>\n","protected":false},"excerpt":{"rendered":" 1. \u5bc4\u5b58\u5668\u6620\u5c04\u7684\u672c\u8d28：\u4ece\u5185\u5b58\u5730\u5740\u5230\u53ef\u7f16\u7a0b\u5916\u8bbe\u7684\u5de5\u7a0b\u6865\u6881\u5728\u5d4c\u5165\u5f0f\u7cfb\u7edf\u5f00\u53d1\u4e2d，\u201c\u5bc4\u5b58\u5668\u201d\u4e00\u8bcd\u5e38\u88ab\u521d\u5b66\u8005\u8bef\u89e3\u4e3a\u67d0\u79cd\u795e\u79d8\u7684\u786c\u4ef6\u5f00\u5173\u6216\u62bd\u8c61\u6982\u5ff5\u3002\u5b9e\u9645\u4e0a，\u5bc4\u5b58\u5668\u662f\u5fae\u63a7\u5236\u5668\u4e2d\u6700\u57fa\u7840\u3001\u6700\u771f\u5b9e\u7684\u7269\u7406\u5b58\u5728\u2014\u2014\u5b83\u662f\u4e00\u5757\u4f4d\u4e8e\u7279\u5b9a\u5185\u5b58\u5730\u5740\u4e0a\u7684\u3001\u53ef\u88abCPU\u76f4\u63a5\u8bfb\u5199\u768432\u4f4d（\u621616\/8\u4f4d）\u5b58\u50a8\u5355\u5143\u3002\u5bf9STM32\u800c\u8a00，\u5bc4\u5b58\u5668\u5e76\u975e\u60ac\u6d6e\u4e8e\u7a7a\u4e2d\u7684\u903b\u8f91\u7b26\u53f7，\u800c\u662f\u4e25\u683c\u6620\u5c04\u5728\u7247\u4e0a\u5730\u5740\u7a7a\u95f4\u4e2d\u7684\u4e00\u7ec4\u8fde\u7eed\u5185\u5b58\u4f4d\u7f6e\u3002\u7406\u89e3\u5bc4\u5b58\u5668\u6620<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[8348,8349,217],"topic":[],"class_list":["post-76854","post","type-post","status-publish","format-standard","hentry","category-server","tag-8348","tag-8349","tag-stm32"],"yoast_head":"\n STM32\u5bc4\u5b58\u5668\u6620\u5c04\u539f\u7406\u4e0e\u7ed3\u6784\u4f53\u5c01\u88c5\u5b9e\u8df5 - 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