{"id":72101,"date":"2026-02-04T22:18:16","date_gmt":"2026-02-04T14:18:16","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/72101.html"},"modified":"2026-02-04T22:18:16","modified_gmt":"2026-02-04T14:18:16","slug":"stm32-dma%e6%95%b0%e6%8d%ae%e8%bd%ac%e6%8d%a2%e3%80%81dmaad%e5%a4%9a%e9%80%9a%e9%81%93%ef%bc%88%e5%8d%81%e4%ba%94%ef%bc%89","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/72101.html","title":{"rendered":"STM32\u2014\u2014DMA\u6570\u636e\u8f6c\u6362\u3001DMA+AD\u591a\u901a\u9053\uff08\u5341\u4e94\uff09"},"content":{"rendered":"

\u4e00\u3001\u5e93\u51fd\u6570<\/h3>\n

1\u3001void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u914d\u7f6e DMA \u901a\u9053\u7684\u4e2d\u65ad\u4f7f\u80fd \/ \u5931\u80fd（\u5f00\u542f\u6216\u5173\u95ed\u67d0\u4e2a DMA \u4e2d\u65ad\u7c7b\u578b）\u3002<\/p>\n

2\u3001void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u8bbe\u7f6e DMA \u901a\u9053\u7684\u5f53\u524d\u5269\u4f59\u4f20\u8f93\u6570\u636e\u4e2a\u6570（DMA \u7684\u6838\u5fc3\u8ba1\u6570\u5668，\u4f20\u8f93 1 \u4e2a\u6570\u636e，\u8ba1\u6570\u5668\u81ea\u52a8\u51cf 1）\u3002<\/p>\n

3\u3001uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u83b7\u53d6 DMA \u901a\u9053\u7684\u5f53\u524d\u5269\u4f59\u4f20\u8f93\u6570\u636e\u4e2a\u6570（\u8bfb\u53d6\u8ba1\u6570\u5668\u7684\u5b9e\u65f6\u503c），\u8fd4\u56de\u503c\u4e3a\u5269\u4f59\u4e2a\u6570\u3002<\/p>\n

4\u3001FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u67e5\u8be2 DMA \u7684\u72b6\u6001\u6807\u5fd7\u4f4d\u662f\u5426\u7f6e 1（\u5373\u67d0\u4e2a\u4e8b\u4ef6\u662f\u5426\u53d1\u751f，\u5982\u4f20\u8f93\u5b8c\u6210\u3001\u534a\u4f20\u8f93\u3001\u9519\u8bef），\u8fd4\u56de\u6807\u5fd7\u4f4d\u72b6\u6001\u3002<\/p>\n

5\u3001void DMA_ClearFlag(uint32_t DMAy_FLAG)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u624b\u52a8\u6e05\u9664 DMA \u7684\u72b6\u6001\u6807\u5fd7\u4f4d（\u5c06\u7f6e 1 \u7684\u6807\u5fd7\u4f4d\u6e05\u96f6）\u3002<\/p>\n

6\u3001ITStatus DMA_GetITStatus(uint32_t DMAy_IT)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u67e5\u8be2 DMA \u7684\u4e2d\u65ad\u6302\u8d77\u4f4d\u662f\u5426\u7f6e 1（\u5373\u67d0\u4e2a\u4e2d\u65ad\u4e8b\u4ef6\u662f\u5426\u53d1\u751f，\u4e14\u8be5\u4e2d\u65ad\u5df2\u5f00\u542f），\u8fd4\u56de\u4e2d\u65ad\u72b6\u6001\u3002<\/p>\n

7\u3001void DMA_ClearITPendingBit(uint32_t DMAy_IT)<\/p>\n

\u6838\u5fc3\u529f\u80fd：\u6e05\u9664 DMA \u7684\u4e2d\u65ad\u6302\u8d77\u4f4d（\u5c06\u7f6e 1 \u7684\u4e2d\u65ad\u6302\u8d77\u4f4d\u6e05\u96f6）\u3002<\/p>\n

\u4e8c\u3001\u6570\u636e\u8f6c\u6362<\/h3>\n

\u5c06\u6570\u7ec4A\u4e2d\u7684\u6570\u636e\u8f6c\u6362\u5230\u6570\u7ec4B\u4e2d<\/p>\n

uint8_t DataA[] = {0x01, 0x02, 0x03, 0x04};
\nuint8_t DataB[] = {0, 0, 0, 0};<\/p>\n

1\u3001\u521d\u59cb\u5316\u914d\u7f6e<\/h5>\n

void MyDMA_Init(uint32_t AddrA, uint32_t AddrB, uint16_t Size)
\n{
\nMyDMA_Size = Size;
\nRCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE);
\nDMA_InitTypeDef DMA_InitStructure;
\nDMA_InitStructure.DMA_PeripheralBaseAddr = AddrA;
\nDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
\nDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
\nDMA_InitStructure.DMA_MemoryBaseAddr = AddrB;
\nDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
\nDMA_InitStructure .DMA_MemoryInc = DMA_MemoryInc_Enable;
\nDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
\nDMA_InitStructure.DMA_BufferSize = Size;
\nDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
\nDMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
\nDMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
\nDMA_Init(DMA1_Channel1,&DMA_InitStructure);<\/p>\n

DMA_Cmd(DMA1_Channel1,DISABLE);
\n}<\/p>\n

\u7ad9\u70b9\u5730\u5740<\/p>\n

\u5c06\u8981\u8f6c\u6362\u6570\u7ec4\u7684\u5730\u5740\u548c\u6570\u636e\u4e2a\u6570\u4f20\u5165\u3002<\/p>\n

void MyDMA_Init(uint32_t AddrA, uint32_t AddrB, uint16_t Size)<\/p>\n

\u6253\u5f00DMA\u65f6\u949f<\/p>\n

\u00a0RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE);<\/p>\n

\u914d\u7f6e\u5916\u8bbe\u7ad9\u70b9<\/p>\n

\u914d\u7f6e\u5916\u8bbe\u7ad9\u70b9\u5730\u5740，\u6570\u636e\u5bbd\u5ea6：\u4ee5\u5b57\u8282\u4f20\u8f93，\u5730\u5740\u662f\u5426\u81ea\u589e：\u662f\u3002<\/p>\n

\u00a0DMA_InitStructure.DMA_PeripheralBaseAddr = AddrA;
\n\u00a0\u00a0 \u00a0DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
\n\u00a0\u00a0 \u00a0DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;<\/p>\n

\u914d\u7f6e\u5b58\u50a8\u5668\u7ad9\u70b9<\/p>\n

\u914d\u7f6e\u5b58\u50a8\u5668\u7ad9\u70b9\u5730\u5740，\u6570\u636e\u5bbd\u5ea6：\u4ee5\u5b57\u8282\u4f20\u8f93，\u5730\u5740\u662f\u5426\u81ea\u589e：\u662f\u3002<\/p>\n

DMA_InitStructure.DMA_MemoryBaseAddr = AddrB;
\n\u00a0\u00a0 \u00a0DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
\n\u00a0\u00a0 \u00a0DMA_InitStructure .DMA_MemoryInc = DMA_MemoryInc_Enable;<\/p>\n

\u914d\u7f6e\u4f20\u8f93\u65b9\u5411\u548c\u6570\u636e\u4e2a\u6570<\/p>\n

\u914d\u7f6e\u4e3a\u4ece\u5916\u90e8\u7ad9\u70b9\u4f20\u8f93\u5230\u5b58\u50a8\u5668\u7ad9\u70b9，\u6570\u636e\u4e2a\u6570Size\u3002<\/p>\n

DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
\n\u00a0\u00a0 \u00a0DMA_InitStructure.DMA_BufferSize = Size;<\/p>\n

\u914d\u7f6e\u91cd\u88c5，\u89e6\u53d1\u3001\u4f18\u5148\u7ea7<\/p>\n

\u914d\u7f6e\u4e3a\u4e0d\u91cd\u88c5，\u8f6f\u4ef6\u89e6\u53d1，\u4e2d\u7b49\u4f18\u5148\u7ea7（\u5728\u8fd9\u4e2a\u7a0b\u5e8f\u4e2d\u53ef\u4efb\u610f\u914d\u7f6e）<\/p>\n

DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
\n\u00a0\u00a0 \u00a0DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
\n\u00a0\u00a0 \u00a0DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;<\/p>\n

\u5173\u95edDMA1<\/p>\n

\u00a0\u00a0 \u00a0DMA_Cmd(DMA1_Channel1,DISABLE);<\/p>\n

2\u3001\u518d\u6b21\u542f\u52a8DMA<\/h5>\n

\u5f53\u6570\u7ec4A\u7684\u6570\u636e\u53d8\u5316\u540e，\u518d\u6b21\u542f\u52a8DMA\u8f6c\u6362\u6570\u636e\u5230\u6570\u7ec4B\u3002<\/p>\n

void MyDMA_Transfer(void)
\n{
\nDMA_Cmd(DMA1_Channel1,DISABLE);
\nDMA_SetCurrDataCounter(DMA1_Channel1,MyDMA_Size);
\nDMA_Cmd(DMA1_Channel1,ENABLE);<\/p>\n

while(DMA_GetFlagStatus(DMA1_FLAG_TC1) == RESET);
\nDMA_ClearFlag(DMA1_FLAG_TC1);
\n}<\/p>\n

\u518d\u6b21\u542f\u52a8DMA\u8981\u91cd\u88c5\u8ba1\u6570\u5668，\u91cd\u88c5\u8ba1\u6570\u5668\u8981\u5148\u5173\u95edDMA，MyDMA_Size\u5728\u524d\u9762Init \u4e2d\u6709\u88ab\u6267\u884cMyDMA_Size =\u00a0Size；<\/p>\n

DMA_Cmd(DMA1_Channel1,DISABLE);
\nDMA_SetCurrDataCounter(DMA1_Channel1,MyDMA_Size);
\nDMA_Cmd(DMA1_Channel1,ENABLE);<\/p>\n

\u7b49\u5f85DMA\u901a\u90531\u8f6c\u6362\u5b8c\u6210\u6807\u5fd7\u4f4d\u7f6e1，\u7136\u540e\u624b\u52a8\u6e05\u9664\u6807\u5fd7\u4f4d\u3002<\/p>\n

while(DMA_GetFlagStatus(DMA1_FLAG_TC1) == RESET);
\nDMA_ClearFlag(DMA1_FLAG_TC1);<\/p>\n

3\u3001\u8c03\u7528<\/h5>\n

\u8ba9\u6570\u7ec4A\u7684\u5143\u7d20++，\u663e\u793a\u4e24\u4e2a\u6570\u7ec4\u7684\u5143\u7d20\u503c，\u5ef6\u65f6\u4e00\u6bb5\u65f6\u95f4，\u7136\u540e\u5728\u663e\u793a\u66f4\u65b0\u540e\u7684\u503c\u3002<\/p>\n

int main(void)
\n{
\nOLED_Init();<\/p>\n

MyDMA_Init((uint32_t)DataA,(uint32_t)DataB,4);<\/p>\n

OLED_ShowString(1,1,"DataA");
\nOLED_ShowString(3,1,"DataB");
\nOLED_ShowHexNum(1,8,(uint32_t)DataA,8);
\nOLED_ShowHexNum(3,8,(uint32_t)DataB,8);<\/p>\n

OLED_ShowHexNum(2,1,DataA[0],2);
\nOLED_ShowHexNum(2,4,DataA[1],2);
\nOLED_ShowHexNum(2,7,DataA[2],2);
\nOLED_ShowHexNum(2,10,DataA[3],2);
\nOLED_ShowHexNum(4,1,DataB[0],2);
\nOLED_ShowHexNum(4,4,DataB[1],2);
\nOLED_ShowHexNum(4,7,DataB[2],2);
\nOLED_ShowHexNum(4,10,DataB[3],2);<\/p>\n

while(1)
\n{
\nDataA[0] ++;
\nDataA[1] ++;
\nDataA[2] ++;
\nDataA[3] ++;<\/p>\n

OLED_ShowHexNum(2,1,DataA[0],2);
\nOLED_ShowHexNum(2,4,DataA[1],2);
\nOLED_ShowHexNum(2,7,DataA[2],2);
\nOLED_ShowHexNum(2,10,DataA[3],2);
\nOLED_ShowHexNum(4,1,DataB[0],2);
\nOLED_ShowHexNum(4,4,DataB[1],2);
\nOLED_ShowHexNum(4,7,DataB[2],2);
\nOLED_ShowHexNum(4,10,DataB[3],2);<\/p>\n

Delay_ms(1000);<\/p>\n

MyDMA_Transfer();
\nOLED_ShowHexNum(2,1,DataA[0],2);
\nOLED_ShowHexNum(2,4,DataA[1],2);
\nOLED_ShowHexNum(2,7,DataA[2],2);
\nOLED_ShowHexNum(2,10,DataA[3],2);
\nOLED_ShowHexNum(4,1,DataB[0],2);
\nOLED_ShowHexNum(4,4,DataB[1],2);
\nOLED_ShowHexNum(4,7,DataB[2],2);
\nOLED_ShowHexNum(4,10,DataB[3],2);<\/p>\n

Delay_ms(1000);
\n}
\n}<\/p>\n

\u4e09\u3001DMA+AD\u591a\u901a\u9053<\/h3>\n

1\u3001\u63a5\u7ebf\u56fe<\/h5>\n

\"\"<\/p>\n

2\u3001\u521d\u59cb\u5316\u914d\u7f6e<\/h5>\n

\u914d\u7f6eADC：\u5355ADC\u5de5\u4f5c\u3001\u6570\u636e\u53f3\u5bf9\u9f50\u3001\u8f6f\u4ef6\u89e6\u53d1\u3001\u5173\u95ed\u8fde\u7eed\u8f6c\u6362\u3001\u626b\u63cf\u6a21\u5f0f\u3001\u626b\u63cf\u901a\u9053\u6570\u76ee4<\/p>\n

\u914d\u7f6eDMA：<\/p>\n

\u5916\u90e8\u7ad9\u70b9：\u5730\u5740\u662fADC1\u7684DR\u5bc4\u5b58\u5668（ADC\u8f6c\u5316\u7ed3\u679c\u5b58\u653e\u5728\u8fd9\u4e2a\u5bc4\u5b58\u5668）\u3001\u6570\u636e\u5e26\u5bbd16\u4f4d\u3001\u5730\u5740\u4e0d\u9012\u589e\u3002<\/p>\n

\u5b58\u50a8\u5668\u7ad9\u70b9：\u5730\u5740\u662f\u5168\u5c40\u6570\u7ec4AD_Value\u3001\u6570\u636e\u5e26\u5bbd16\u4f4d\u3001\u5730\u5740\u9012\u589e\u3002<\/p>\n

\u642c\u8fd0\u65b9\u5411\u5916\u8bbe\u2192\u5185\u5b58\u3001\u642c\u8fd0\u6b21\u65704\u6b21\u3001\u5355\u6b21\u642c\u8fd0\u3001ADC\u786c\u4ef6\u89e6\u53d1\u3001DMA\u4f18\u5148\u7ea7：\u4e2d\u7b49（\u65e0\u5176\u4ed6DMA\u65f6\u968f\u610f）<\/p>\n

void AD_Init(void)
\n{
\nRCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1,ENABLE);
\nRCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE);
\nRCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE);<\/p>\n

RCC_ADCCLKConfig(RCC_PCLK2_Div6);<\/p>\n

GPIO_InitTypeDef GPIO_Initstructure;
\nGPIO_Initstructure.GPIO_Mode = GPIO_Mode_AIN;\/\/\u6b64\u65f6GPIO\u53e3\u53ea\u53d7\u5230ADC\u7684\u63a7\u5236
\nGPIO_Initstructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1| GPIO_Pin_2 | GPIO_Pin_3;
\nGPIO_Initstructure.GPIO_Speed = GPIO_Speed_50MHz;
\nGPIO_Init(GPIOA,&GPIO_Initstructure);<\/p>\n

ADC_RegularChannelConfig(ADC1,ADC_Channel_0,1,ADC_SampleTime_55Cycles5);
\nADC_RegularChannelConfig(ADC1,ADC_Channel_1,2,ADC_SampleTime_55Cycles5);
\nADC_RegularChannelConfig(ADC1,ADC_Channel_2,3,ADC_SampleTime_55Cycles5);
\nADC_RegularChannelConfig(ADC1,ADC_Channel_3,4,ADC_SampleTime_55Cycles5);<\/p>\n

ADC_InitTypeDef ADC_InitStructure;
\nADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
\nADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
\nADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
\nADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
\nADC_InitStructure.ADC_ScanConvMode = ENABLE;
\nADC_InitStructure.ADC_NbrOfChannel = 4;
\nADC_Init(ADC1,&ADC_InitStructure);<\/p>\n

DMA_InitTypeDef DMA_InitStructure;
\nDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&ADC1->DR;
\nDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
\nDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
\nDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)AD_Value;
\nDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
\nDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
\nDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
\nDMA_InitStructure.DMA_BufferSize = 4;
\nDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
\nDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
\nDMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
\nDMA_Init(DMA1_Channel1,&DMA_InitStructure);<\/p>\n

DMA_Cmd(DMA1_Channel1,ENABLE);<\/p>\n

ADC_DMACmd(ADC1, ENABLE);
\nADC_Cmd(ADC1,ENABLE);<\/p>\n

ADC_ResetCalibration(ADC1);
\nwhile(ADC_GetResetCalibrationStatus(ADC1) == SET);
\nADC_StartCalibration(ADC1);
\nwhile(ADC_GetCalibrationStatus(ADC1) == SET);<\/p>\n

}<\/p>\n

\u6253\u5f00ADC\u548cDMA\u7684\u901a\u9053<\/p>\n

\u5f00\u542fADC1\u7684DMA\u8bf7\u6c42（ADC\u8f6c\u6362\u5b8c\u6210\u540e，\u4e3b\u52a8\u901a\u77e5DMA\u642c\u8fd0）<\/p>\n

ADC_DMACmd(ADC1, ENABLE);<\/p>\n

3\u3001\u518d\u542f\u52a8<\/h5>\n

\u9700\u8981\u91c7\u96c6\u6570\u636e\u65f6，\u5728\u4e3b\u51fd\u6570\u4e2d\u8c03\u7528\u4e00\u6b21\u5c31\u6267\u884c\u4e00\u6b21 4 \u901a\u9053\u626b\u63cf，\u91c7\u96c6\u5b8c\u6210\u540e\u7ed3\u679c\u81ea\u52a8\u5b58\u5165AD_Value\u6570\u7ec4<\/p>\n

void AD_GetValue(void)
\n{
\nDMA_Cmd(DMA1_Channel1,DISABLE);
\nDMA_SetCurrDataCounter(DMA1_Channel1,4);
\nDMA_Cmd(DMA1_Channel1,ENABLE);<\/p>\n

ADC_SoftwareStartConvCmd(ADC1,ENABLE);
\nwhile(DMA_GetFlagStatus(DMA1_FLAG_TC1) == RESET);
\nDMA_ClearFlag(DMA1_FLAG_TC1);
\n}<\/p>\n

4\u3001\u8c03\u7528<\/h5>\n

int main(void)
\n{
\nOLED_Init();
\nAD_Init();<\/p>\n

OLED_ShowString(1,1,"AD0:");
\nOLED_ShowString(2,1,"AD1:");
\nOLED_ShowString(3,1,"AD2:");
\nOLED_ShowString(4,1,"AD3:");<\/p>\n

while(1)
\n{
\nAD_GetValue();<\/p>\n

OLED_ShowNum(1,5,AD_Value[0],4);
\nOLED_ShowNum(2,5,AD_Value[1],4);
\nOLED_ShowNum(3,5,AD_Value[2],4);
\nOLED_ShowNum(4,5,AD_Value[3],4);<\/p>\n

Delay_ms(100);<\/p>\n

}
\n}<\/p>\n","protected":false},"excerpt":{"rendered":"

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