{"id":69982,"date":"2026-02-01T09:41:35","date_gmt":"2026-02-01T01:41:35","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/69982.html"},"modified":"2026-02-01T09:41:35","modified_gmt":"2026-02-01T01:41:35","slug":"%e7%ac%ac-3-%e7%ab%a0-%e5%9f%ba%e4%ba%8e-vs-code-%e7%9a%84-hdl-%e5%bc%80%e5%8f%91%e7%8e%af%e5%a2%83%e6%90%ad%e5%bb%ba%e4%b8%8e%e6%8f%92%e4%bb%b6%e5%ba%94%e7%94%a8","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/69982.html","title":{"rendered":"\u7b2c 3 \u7ae0 \u57fa\u4e8e VS Code \u7684 HDL \u5f00\u53d1\u73af\u5883\u642d\u5efa\u4e0e\u63d2\u4ef6\u5e94\u7528"},"content":{"rendered":"<h2>\u7ae0\u8282\u5bfc\u8bba<\/h2>\n<p>\u786c\u4ef6\u63cf\u8ff0\u8bed\u8a00&#xff08;HDL&#xff09;\u7684\u9ad8\u6548\u5f00\u53d1\u79bb\u4e0d\u5f00\u9002\u914d\u7684\u5de5\u5177\u94fe\u652f\u6491&#xff0c;VS Code \u4f5c\u4e3a\u8f7b\u91cf\u4e14\u53ef\u9ad8\u5ea6\u5b9a\u5236\u7684\u4ee3\u7801\u7f16\u8f91\u5668&#xff0c;\u901a\u8fc7\u5b89\u88c5\u4e13\u7528 HDL \u63d2\u4ef6\u53ef\u5feb\u901f\u642d\u5efa\u4f4e\u6210\u672c\u3001\u9ad8\u6548\u7387\u7684 HDL \u5f00\u53d1\u73af\u5883\u3002\u672c\u7ae0\u805a\u7126 VS Code \u4e0b HDL \u5f00\u53d1\u73af\u5883\u7684\u6838\u5fc3\u914d\u7f6e\u6d41\u7a0b&#xff0c;\u91cd\u70b9\u8bb2\u89e3\u5173\u952e\u63d2\u4ef6&#xff08;Digital IDE\u3001Verilog-HDL-Format&#xff09;\u7684\u5b89\u88c5\u3001\u6838\u5fc3\u529f\u80fd\u4e0e\u4f7f\u7528\u89c4\u8303&#xff0c;\u540c\u65f6\u68b3\u7406\u73af\u5883\u914d\u7f6e\u4e2d\u7684\u524d\u63d0\u6761\u4ef6\u548c\u5e38\u89c1\u95ee\u9898&#xff0c;\u5e2e\u52a9\u5f00\u53d1\u8005\u901a\u8fc7\u63d2\u4ef6\u8d4b\u80fd&#xff0c;\u89e3\u51b3 HDL \u5f00\u53d1\u4e2d\u8bed\u6cd5\u7ea0\u9519\u3001\u4ee3\u7801\u590d\u7528\u3001\u4eff\u771f\u8c03\u8bd5\u7b49\u6548\u7387\u75db\u70b9&#xff0c;\u5b9e\u73b0 Verilog\/SV\/VHDL \u4ee3\u7801\u7684\u6807\u51c6\u5316\u3001\u9ad8\u6548\u5316\u5f00\u53d1\u3002<\/p>\n<h2>3.1 \u73af\u5883\u642d\u5efa\u524d\u63d0\u6761\u4ef6<\/h2>\n<p>\u642d\u5efa VS Code HDL \u5f00\u53d1\u73af\u5883\u9700\u5148\u5b8c\u6210\u5e95\u5c42\u5de5\u5177\u90e8\u7f72&#xff08;\u5982&#xff1a; Icarus Verilog&#xff09;&#xff0c;\u786e\u4fdd\u63d2\u4ef6\u529f\u80fd\u53ef\u6b63\u5e38\u8c03\u7528&#xff1a;<\/p>\n<ul>\n<li>\u5b89\u88c5 Icarus Verilog&#xff1a;\u4f5c\u4e3a\u57fa\u7840\u7684 Verilog \u7f16\u8bd1\u3001\u4eff\u771f\u5de5\u5177&#xff0c;\u662f Digital IDE \u7b49\u63d2\u4ef6\u5b9e\u73b0\u8bed\u6cd5\u8bca\u65ad\u3001\u5feb\u901f\u4eff\u771f\u7684\u6838\u5fc3\u4f9d\u8d56\n<ul>\n<li>\u3010Icarus Verilog \u5b89\u88c5\u6559\u7a0b\u53c2\u8003\u7b2c\u4e8c\u7ae0\u3011&#xff1b;<\/li>\n<li>\u5b98\u7f51\u4e0b\u8f7d\u5730\u5740&#xff1a;https:\/\/bleyer.org\/icarus\/<\/li>\n<li>\u5b98\u7f51\u4e0b\u8f7d\u5730\u5740&#xff1a;https:\/\/code.visualstudio.com\/Download<\/li>\n<\/ul>\n<\/li>\n<li>\u914d\u7f6e\u73af\u5883\u53d8\u91cf&#xff1a;\u5c06 Icarus Verilog \u7684\u5b89\u88c5\u8def\u5f84\u6dfb\u52a0\u81f3\u7cfb\u7edf\u73af\u5883\u53d8\u91cf&#xff0c;\u786e\u4fdd VS Code \u63d2\u4ef6\u53ef\u5168\u5c40\u8c03\u7528 iverilog \u7b49\u547d\u4ee4\u3002<\/li>\n<\/ul>\n<h2>3.2 VS Code \u6838\u5fc3\u63d2\u4ef6\u5b89\u88c5<\/h2>\n<h3>3.2.1 \u5b89\u88c5\u63d2\u4ef6\u7684\u4e3b\u8981\u76ee\u7684&#xff1a;\u63d0\u9ad8\u5f00\u53d1\u6548\u7387<\/h3>\n<ul>\n<li>\u8bed\u6cd5\u9ad8\u4eae<\/li>\n<li>\u4ee3\u7801\u8865\u5168<\/li>\n<li>\u5b9e\u65f6\u7ea0\u9519<\/li>\n<li>\u4e00\u952e\u542f\u52a8\u3010\u7f16\u8bd1&#043;\u4eff\u771f\u3011<\/li>\n<li>\u4ee3\u7801\u683c\u5f0f\u5316<\/li>\n<li>\u5b9a\u4e49\u8df3\u8f6c<\/li>\n<li>\u4e00\u952e\u4f8b\u5316\u7b49<\/li>\n<\/ul>\n<h3>3.2.2 \u63d2\u4ef6\u5b89\u88c5\u901a\u7528\u6d41\u7a0b<\/h3>\n<ul>\n<li>\u6253\u5f00 VS Code&#xff0c;\u8fdb\u5165\u5de6\u4fa7 \u201c\u6269\u5c55\u201d \u9762\u677f&#xff08;\u5feb\u6377\u952e Ctrl&#043;Shift&#043;X&#xff09;&#xff1b;<\/li>\n<li>\u5728\u641c\u7d22\u6846\u8f93\u5165\u63d2\u4ef6\u540d\u79f0&#xff0c;\u70b9\u51fb \u201c\u5b89\u88c5\u201d \u6309\u94ae&#xff1b;<\/li>\n<li>\u63d2\u4ef6\u5b89\u88c5\u5b8c\u6210\u540e\u91cd\u542f VS Code&#xff0c;\u4f7f\u529f\u80fd\u751f\u6548\u3002<\/li>\n<\/ul>\n<h3>3.2.3 \u6838\u5fc3\u63d2\u4ef6\u5217\u8868<\/h3>\n<p>1. Digital IDE<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014132-697eaf4ca3283.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n<ul>\n<li>Digital IDE \u5b98\u65b9\u7f51\u5740&#xff1a;https:\/\/nc-ai.cn\/article\/cxnqr517\/<\/li>\n<li>\u5b89\u88c5&#xff1a;\u5728 Vscode \u63d2\u4ef6\u5546\u5e97\u4e2d\u641c\u7d22 \u201cDigital IDE\u201d &#xff0c;\u70b9\u51fb\u4e0b\u8f7d\u5373\u53ef\u3002<\/li>\n<li>\u529f\u80fd\u4ecb\u7ecd&#xff1a;\n<ul>\n<li>\u8bed\u8a00\u9ad8\u4eae\u3010\u5b89\u88c5\u63d2\u4ef6\u5c31\u53ef\u7528\u3011\n<ul>\n<li>\u652f\u6301\u9ad8\u4eae\u7684\u8bed\u6cd5\u5982\u4e0b\u56fe\u6240\u793a&#xff1a;<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014132-697eaf4cb2862.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<\/li>\n<li>\u8bed\u6cd5\u8bca\u65ad\u3010\u9700\u8981\u914d\u7f6e\u4e4b\u540e\u624d\u53ef\u7528\u3011&#xff1a;\u8bed\u6cd5\u8bca\u65ad\u53ef\u4ee5\u5728\u5f00\u53d1\u4e2d\u63d0\u524d\u5e2e\u52a9\u5f00\u53d1\u8005\u4e86\u89e3\u5230\u4ee3\u7801\u4e2d\u9690\u85cf\u7684\u8bed\u6cd5\u9519\u8bef&#xff0c;\u5728\u7f16\u8bd1\u6216\u8005\u8fd0\u884c\u524d\u63d0\u524d\u89c4\u907f\u90e8\u5206\u9519\u8bef&#xff0c;\u63d0\u9ad8\u5f00\u53d1\u6548\u7387\n<ul>\n<li>\u4fdd\u5b58\u6587\u4ef6\u540e&#xff0c;\u624d\u4f1a\u68c0\u67e5\u8bed\u6cd5\u9519\u8bef&#xff0c;\u6709\u90e8\u5206\u8bed\u6cd5\u9519\u8bef\u65e0\u6cd5\u68c0\u6d4b<\/li>\n<li>\u652f\u6301\u7684\u8bca\u65ad\u5de5\u5177\u5982\u4e0b\u56fe\u6240\u793a&#xff1a;<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014132-697eaf4cc1766.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<li>\u66f4\u6362\u8bca\u65ad\u5668\u548c\u8bca\u65ad\u7ea7\u522b\u548c\u8bca\u65ad\u6a21\u5f0f\n<ul>\n<li>\u4fee\u6539\u914d\u7f6e\u4e2d\u641c linter \u5982\u4e0b\u56fe<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014132-697eaf4cd1039.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<li>\u8bca\u65ad\u7ea7\u522b\n<ul>\n<li>error: \u53ea\u663e\u793a\u9519\u8bef<\/li>\n<li>warning: \u663e\u793a\u9519\u8bef\u548c\u8b66\u544a<\/li>\n<\/ul>\n<\/li>\n<li>\u8bca\u65ad\u6a21\u5f0f\n<ul>\n<li>Full: \u5c06\u6240\u6709\u8bbe\u8ba1\u6e90\u76f4\u63a5\u8fdb\u884c\u8bca\u65ad&#xff0c;\u5e76\u62a5\u9519&#xff0c;\u65e0\u8bba\u6587\u4ef6\u662f\u5426\u6253\u5f00\u3002<\/li>\n<li>Common: \u5355\u6587\u4ef6\u5173\u95ed\u65f6&#xff0c;\u5bf9\u5e94\u62a5\u9519\u53bb\u9664&#xff0c;\u6253\u5f00\u54ea\u4e2a\u6587\u4ef6\u5c31\u5bf9\u54ea\u4e2a\u6587\u4ef6\u8fdb\u884c\u8bca\u65ad\u3002<\/li>\n<li>Shutdown: \u5168\u5c40\u5173\u95ed&#xff0c;\u5373\u6574\u4e2a\u5de5\u7a0b\u90fd\u4e0d\u8fdb\u884c\u5de5\u7a0b\u62a5\u9519\u3002&#xff08;\u4e13\u5fc3code&#xff09;<\/li>\n<\/ul>\n<\/li>\n<li>\u8bca\u65ad\u5668\u3010\u4f9d\u8d56\u8bca\u65ad\u5668\u7684\u73af\u5883\u53d8\u91cf\u3011\n<ul>\n<li>iverilog&#xff1a;\u53ea\u652f\u6301verilog \u8bed\u6cd5\u68c0\u6d4b<\/li>\n<li>modelsim&#xff1a;\u652f\u6301 verilog\u3001SV\u3001VHDL \u8bed\u6cd5\u68c0\u6d4b<\/li>\n<li>vivado(xvlog)&#xff1a;\u652f\u6301 verilog\u3001SV\u3001VHDL \u8bed\u6cd5\u68c0\u6d4b<\/li>\n<li>verible&#xff1a;\u652f\u6301 verilog\u3001SV \u8bed\u6cd5\u68c0\u6d4b&#xff0c;\u4e0d\u652f\u6301 VHDL \u8bed\u6cd5\u68c0\u6d4b<\/li>\n<li>verilator&#xff1a;\u652f\u6301 verilog\u3001SV \u8bed\u6cd5\u68c0\u6d4b&#xff0c;\u4e0d\u652f\u6301 VHDL \u8bed\u6cd5\u68c0\u6d4b<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014133-697eaf4d23551.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<li>\u60ac\u505c\u63d0\u793a\u3010\u5b89\u88c5\u63d2\u4ef6\u5c31\u53ef\u7528\u3011&#xff1a;\u628a\u9f20\u6807\u5149\u6807\u79fb\u52a8\u5230\u4e00\u4e2a\u53d8\u91cf\u4e0a\u65f6&#xff0c;IDE \u4f1a\u8d1f\u8d23\u5c06\u8fd9\u4e2a\u53d8\u91cf\u7684\u4e0a\u4e0b\u6587\u4fe1\u606f\u663e\u793a\u5728\u5149\u6807\u7684\u65c1\u8fb9<\/li>\n<li>\u81ea\u52a8\u8865\u5168\u3010\u5b89\u88c5\u63d2\u4ef6\u5c31\u53ef\u7528\u3011\n<ul>\n<li>\u4ee3\u7801\u7247\u6bb5\u81ea\u52a8\u8865\u5168<\/li>\n<li>\u5173\u952e\u8bcd\u81ea\u52a8\u8865\u5168&#xff08;\u5173\u952e\u8bcd&#xff0c;\u7cfb\u7edf\u51fd\u6570&#xff0c;\u5b8f&#xff09;<\/li>\n<li>\u81ea\u52a8\u4f8b\u5316<\/li>\n<li>\u539f\u8bed\u4f8b\u5316<\/li>\n<\/ul>\n<\/li>\n<li>\u5b9a\u4e49\u8df3\u8f6c \u3010\u5b89\u88c5\u63d2\u4ef6\u5c31\u53ef\u7528\u3011&#xff1a;\u5141\u8bb8\u7528\u6237\u5feb\u901f\u5728\u7f16\u8f91\u5668\u4e2d\u8df3\u8f6c\u5230\u5bf9\u5e94\u53d8\u91cf\u7684\u5b9a\u4e49\u7684\u4f4d\u7f6e\u4e0a&#xff0c;\u6309Ctrl&#043;\u9f20\u6807\u5de6\u952e\u70b9\u51fb<\/li>\n<li>\u4ee3\u7801\u683c\u5f0f\u5316\u3010\u5b89\u88c5\u63d2\u4ef6\u5c31\u53ef\u7528\u3011&#xff1a;\u9009\u4e2d\u9700\u8981\u683c\u5f0f\u5316\u7684\u4ee3\u7801&#xff0c;\u6309\u5feb\u6377\u952e shift &#043; alt &#043; f<\/li>\n<li>\u91cd\u542fvs code<\/li>\n<\/ul>\n<\/li>\n<li>\u5feb\u901f\u4eff\u771f\u3010\u4f9d\u8d56\u8bca\u65ad\u5668&#xff08;\u4f8b\u5982&#xff1a;Icarus Verilog&#xff09; \u7684\u73af\u5883\u53d8\u91cf\u3011<\/li>\n<\/ul>\n<p>Digital IDE \u5bf9 include\u505a\u4e86\u4e13\u95e8\u7684\u8bbe\u8ba1&#xff0c;\u6fc0\u52b1\u5757\u65e0\u8bba\u5199\u4e0d\u5199 include \u90fd\u80fd\u6b63\u5e38\u4eff\u771f&#xff0c;\u4f46\u6211\u4eec\u5f3a\u70c8\u4e0d\u5efa\u8bae\u5199include&#xff0c;include\u672c\u8eab\u7684\u8bbe\u8ba1\u4f1a\u5bfc\u81f4\u66f4\u9ad8\u7684\u590d\u6742\u5ea6&#xff0c;\u5bfc\u81f4\u8fd0\u884c\u7684\u4e0d\u7a33\u5b9a\u6027<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014133-697eaf4d3033f.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n<ul>\n<li>\u6dfb\u52a0\u4fe1\u53f7\u751f\u6210\u6ce2\u5f62<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014133-697eaf4d6a1fd.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014133-697eaf4dab5e8.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<li>Verilog-HDL-Format&#xff1a;\u63d0\u5347 Verilog\u3001VHDL\u3001systemverilog \u4ee3\u7801\u8d28\u91cf\u7684 VSCode \u63d2\u4ef6<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014133-697eaf4ded0d2.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<ul>\n<li>\u63d2\u4ef6\u652f\u6301\u7684\u529f\u80fd\u5982\u4e0b&#xff1a;<\/li>\n<li>\u5b98\u65b9\u7f51\u5740&#xff1a;https:\/\/1391074994.github.io\/Verilog-Hdl-Format\/#\/.\/README\n<ul>\n<li>\u4ee3\u7801\u683c\u5f0f\u5316: \u81ea\u52a8\u5bf9\u9f50 Verilog \u4ee3\u7801\u7684\u53d8\u91cf\u3001\u9017\u53f7\u548c\u62ec\u53f7&#xff0c;\u4f7f\u4ee3\u7801\u66f4\u6613\u8bfb\u3002<\/li>\n<li>\u6587\u4ef6\u6811\u663e\u793a: \u4ee5\u6811\u72b6\u7ed3\u6784\u6e05\u6670\u5730\u5c55\u793a Verilog\/VHDL\/SystemVerilog \u6587\u4ef6\u7684\u5c42\u6b21\u5173\u7cfb&#xff0c;\u65b9\u4fbf\u4ee3\u7801\u5bfc\u822a\u3002<\/li>\n<li>\u4e00\u952e\u4f8b\u5316\u3010\u4e3b\u8981\u7528\u5230\u8fd9\u4e2a\u529f\u80fd\u3011: \u5feb\u901f\u751f\u6210 Verilog \u6a21\u5757\u4f8b\u5316\u4ee3\u7801&#xff0c;\u5e76\u81ea\u52a8\u590d\u5236\u5230\u526a\u8d34\u677f&#xff0c;\u544a\u522b\u7e41\u7410\u7684\u624b\u52a8\u7f16\u5199\u3002\n<ul>\n<li>&#x1f535; \u3010\u4e00\u952e\u4f8b\u5316\u3011 \u547d\u4ee4: Convert_instance \u5feb\u6377\u952e: \u65e0<\/li>\n<li>&#x1f535; \u3010\u4e00\u952e TB\u3011 \u547d\u4ee4: Convert_testbench \u5feb\u6377\u952e: \u65e0&#xff0c;\u751f\u6210\u7684\u4ee3\u7801\u81ea\u52a8\u590d\u5236\u5728\u526a\u5207\u677f\u3010\u53ea\u80fd\u751f\u6210\u7b80\u5355\u7684 \u6fc0\u52b1\u5757\u4ee3\u7801&#xff0c;\u7ec6\u8282\u9700\u8981\u4f18\u5316\u3011<\/li>\n<li>\u6309 Ctrl &#043; Shift &#043; P \u8f93\u5165 Convert_testbench<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014134-697eaf4e1058d.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<li>\u81ea\u52a8\u751f\u6210\u7684\u57fa\u7840\u6fc0\u52b1\u5757&#xff08;\u57fa\u7840\u6d4b\u8bd5\u53f0&#xff09;\u4ee3\u7801\u590d\u5236\u6210\u529f\u63d0\u793a<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014134-697eaf4e5bb5e.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<\/li>\n<li>\u8bed\u6cd5\u9ad8\u4eae: \u652f\u6301 ucf, xdc, do, tcl, Verilog, SystemVerilog, VHDL \u548c\u9ad8\u4e91 .cst \u8bed\u6cd5\u9ad8\u4eae\u663e\u793a&#xff0c;\u63d0\u5347\u4ee3\u7801\u53ef\u8bfb\u6027\u3002<\/li>\n<li>\u8bed\u6cd5\u8df3\u8f6c: \u5feb\u901f\u8df3\u8f6c\u5230\u6a21\u5757\u5b9a\u4e49\u3001\u5f15\u811a\u5b9a\u4e49\u548c\u53d8\u91cf\u5b9a\u4e49&#xff0c;\u63d0\u9ad8\u4ee3\u7801\u9605\u8bfb\u548c\u8c03\u8bd5\u6548\u7387 (\u96c6\u6210 CTAGS)\u3002<\/li>\n<li>\u4ee3\u7801\u8865\u5168: \u63d0\u4f9b\u667a\u80fd\u7684 Verilog \u4ee3\u7801\u8865\u5168\u5efa\u8bae&#xff0c;\u51cf\u5c11\u4ee3\u7801\u8f93\u5165\u91cf\u3002<\/li>\n<li>\u5b9a\u4e49\u60ac\u505c: \u9f20\u6807\u60ac\u505c\u5728\u53d8\u91cf\u6216\u6a21\u5757\u540d\u4e0a\u5373\u53ef\u67e5\u770b\u5176\u5b9a\u4e49\u4fe1\u606f (\u96c6\u6210 CTAGS)\u3002<\/li>\n<li>\u8bed\u6cd5\u68c0\u67e5: \u4f7f\u7528 xvlog \u8fdb\u884c Verilog \u8bed\u6cd5\u9519\u8bef\u68c0\u67e5&#xff0c;\u53ca\u65e9\u53d1\u73b0\u5e76\u4fee\u590d\u6f5c\u5728\u95ee\u9898\u3002<\/li>\n<li>VIVADO \u8054\u5408\u4eff\u771f: \u7b80\u5316\u5728 VSCode \u4e2d\u8fdb\u884c VIVADO \u8054\u5408\u4eff\u771f\u7684\u6d41\u7a0b (Modelsim\/QuestaSim)\u3002<\/li>\n<li>VIVADO \u7a0b\u5e8f\u5907\u4efd\u548c\u81ea\u52a8\u4e0b\u8f7d: \u5907\u4efd VIVADO \u5de5\u7a0b\u7684 bit \u6587\u4ef6&#xff0c;\u5e76\u63d0\u4f9b\u81ea\u52a8\u4e0b\u8f7d\u811a\u672c&#xff0c;\u4fdd\u969c\u9879\u76ee\u5b89\u5168\u3002<\/li>\n<li>Vivado \u4eff\u771f\u6587\u4ef6\u5feb\u901f\u8f6c\u6362: \u8f6c\u6362 Vivado \u4eff\u771f\u6587\u4ef6\u683c\u5f0f&#xff0c;\u65b9\u4fbf\u4e0d\u540c\u5de5\u5177\u4e4b\u95f4\u7684\u5207\u6362\u3002<\/li>\n<li>FTP \u529f\u80fd: \u65b9\u4fbf\u5730\u5c06 bit \u6587\u4ef6\u4e0a\u4f20\u5230 FTP \u670d\u52a1\u5668&#xff0c;\u5b9e\u73b0\u8fdc\u7a0b\u90e8\u7f72\u3002<\/li>\n<li>UCF \u8f6c XDC \u6587\u4ef6: \u5c06 UCF \u6587\u4ef6\u8f6c\u6362\u4e3a XDC \u6587\u4ef6&#xff0c;\u65b9\u4fbf\u8fdb\u884c\u7ea6\u675f\u6587\u4ef6\u7684\u8fc1\u79fb\u3002<\/li>\n<li>\u6570\u5b57\u9012\u589e\/\u9012\u51cf: \u5feb\u901f\u9012\u589e\u6216\u9012\u51cf\u9009\u4e2d\u7684\u6570\u5b57&#xff0c;\u63d0\u9ad8\u7f16\u8f91\u6548\u7387\u3002<\/li>\n<li>\u989c\u8272\u4e3b\u9898: \u63d0\u4f9b\u81ea\u5b9a\u4e49\u7684 Verilog \u989c\u8272\u4e3b\u9898 (\u201cjiang percy verilog themes\u201d)&#xff0c;\u4e2a\u6027\u5316\u4f60\u7684\u5f00\u53d1\u73af\u5883\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h2>3.3 \u5e38\u89c1\u95ee\u9898<\/h2>\n<li>error Unknown module type: seq_0101 Digital IDE: iverilog<br \/>\n\u539f\u56e0&#xff1a;\u6839\u76ee\u5f55\u4e0b\u6709\u540c\u540d\u6587\u4ef6\u5bfc\u81f4\u7684\u9519\u8bef<\/li>\n<li>\u8def\u5f84\u95ee\u9898&#xff1a;\u6587\u4ef6\u7edd\u5bf9\u8def\u5f84\u5b58\u5728\u7279\u6b8a\u5b57\u7b26&#xff08;\u4f8b\u5982&#xff1a;\u7a7a\u683c&#xff09;<br \/>\n<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/02\/20260201014134-697eaf4ea1b4e.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<h2>3.4 \u9644\u4ef6<\/h2>\n<h3>3.4.1 \u8bbe\u8ba1\u5757\u4ee3\u7801<\/h3>\n<p><span class=\"token comment\">\/\/ \u9632\u6b62seq_0101\u6a21\u5757\u88ab\u91cd\u590d\u5b9a\u4e49<\/span><br \/>\n&#096;ifndef SEQ_0101_V       <span class=\"token comment\">\/\/ \u68c0\u67e5SEQ_0101_V\u662f\u5426\u672a\u5b9a\u4e49<\/span><br \/>\n&#096;define SEQ_0101_V       <span class=\"token comment\">\/\/ \u7b2c\u4e00\u6b21\u5305\u542b\u65f6\u5b9a\u4e49\u8be5\u6807\u8bc6\u7b26<\/span><\/p>\n<p>&#096;timescale <span class=\"token number\">1<\/span>ns<span class=\"token operator\">\/<\/span><span class=\"token number\">1<\/span>ps       <span class=\"token comment\">\/\/ \u65f6\u5e8f\u57fa\u51c6&#xff08;\u4e0e\u6fc0\u52b1\u5757\u7edf\u4e00&#xff09;<\/span><br \/>\nmodule <span class=\"token function\">seq_0101<\/span><span class=\"token punctuation\">(<\/span><br \/>\n    input         clk<span class=\"token punctuation\">,<\/span>      <span class=\"token comment\">\/\/ \u7cfb\u7edf\u65f6\u949f&#xff08;5ns\u5468\u671f&#xff09;<\/span><br \/>\n    input         rst_n<span class=\"token punctuation\">,<\/span>    <span class=\"token comment\">\/\/ \u4f4e\u7535\u5e73\u6709\u6548\u540c\u6b65\u590d\u4f4d<\/span><br \/>\n    output        seq_out   <span class=\"token comment\">\/\/ 0101&#8230;\u4ea4\u66ff\u5e8f\u5217\u8f93\u51fa<\/span><br \/>\n<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">;<\/span><\/p>\n<p><span class=\"token comment\">\/\/ \u5bc4\u5b58\u5668\u8d4b\u521d\u59cb\u503c&#xff08;\u907f\u514d\u4eff\u771f\u521d\u59cbx&#xff09;<\/span><\/p>\n<p><span class=\"token comment\">\/\/  <\/span><\/p>\n<p>reg seq_reg <span class=\"token operator\">&#061;<\/span> <span class=\"token number\">1<\/span>&#039;b0<span class=\"token punctuation\">;<\/span> <\/p>\n<p><span class=\"token comment\">\/\/ \u65f6\u5e8f\u903b\u8f91&#xff1a;\u9010\u65f6\u949f\u7ffb\u8f6c&#xff0c;\u6301\u7eed\u8f93\u51fa0101&#8230;<\/span><br \/>\nalways &#064;<span class=\"token punctuation\">(<\/span>posedge clk<span class=\"token punctuation\">)<\/span> begin<br \/>\n    <span class=\"token keyword\">if<\/span><span class=\"token punctuation\">(<\/span><span class=\"token operator\">!<\/span>rst_n<span class=\"token punctuation\">)<\/span> begin<br \/>\n        seq_reg <span class=\"token operator\">&lt;&#061;<\/span> <span class=\"token number\">1<\/span>&#039;b0<span class=\"token punctuation\">;<\/span>  <span class=\"token comment\">\/\/ \u590d\u4f4d&#xff1a;\u56de\u5230\u521d\u59cb\u503c0<\/span><br \/>\n    end <span class=\"token keyword\">else<\/span> begin<br \/>\n        seq_reg <span class=\"token operator\">&lt;&#061;<\/span> <span class=\"token operator\">~<\/span>seq_reg<span class=\"token punctuation\">;<\/span>  <span class=\"token comment\">\/\/ \u6bcf\u65f6\u949f\u7ffb\u8f6c&#xff08;0\u21921\u21920\u21921&#8230;&#xff09;<\/span><br \/>\n    end<br \/>\nend<\/p>\n<p><span class=\"token comment\">\/\/ \u5e8f\u5217\u8f93\u51fa\u8d4b\u503c<\/span><br \/>\nassign seq_out <span class=\"token operator\">&#061;<\/span> seq_reg<span class=\"token punctuation\">;<\/span><\/p>\n<p>endmodule<\/p>\n<p>&#096;endif  <span class=\"token comment\">\/\/ SEQ_0101_V \u4fdd\u62a4\u5757\u7ed3\u675f<\/span><\/p>\n<h3>3.4.2 \u6fc0\u52b1\u5757\u4ee3\u7801<\/h3>\n<p><span class=\"token comment\">\/\/ \u9632\u6b62tb_seq_0101\u6a21\u5757\u88ab\u91cd\u590d\u5b9a\u4e49<\/span><br \/>\n&#096;ifndef TB_SEQ_0101_V     <span class=\"token comment\">\/\/ \u68c0\u67e5TB_SEQ_0101_V\u662f\u5426\u672a\u5b9a\u4e49<\/span><br \/>\n&#096;define TB_SEQ_0101_V     <span class=\"token comment\">\/\/ \u7b2c\u4e00\u6b21\u5305\u542b\u65f6\u5b9a\u4e49\u8be5\u6807\u8bc6\u7b26<\/span><\/p>\n<p><span class=\"token comment\">\/\/ \u5305\u542b\u8bbe\u8ba1\u5757&#xff08;\u5373\u4f7f\u591a\u6b21\u5305\u542b&#xff0c;seq_0101.v\u7684\u4fdd\u62a4\u5757\u4f1a\u907f\u514d\u91cd\u590d&#xff09;<\/span><br \/>\n<span class=\"token comment\">\/\/ &#096;include &#034;.\/seq_0101.v&#034;<\/span><\/p>\n<p>&#096;timescale <span class=\"token number\">1<\/span>ns<span class=\"token operator\">\/<\/span><span class=\"token number\">1<\/span>ps<br \/>\nmodule tb_seq_0101<span class=\"token punctuation\">;<\/span><\/p>\n<p><span class=\"token comment\">\/\/ 1. \u6fc0\u52b1\u4fe1\u53f7\u5b9a\u4e49<\/span><br \/>\nreg         clk <span class=\"token operator\">&#061;<\/span> <span class=\"token number\">1<\/span>&#039;b0<span class=\"token punctuation\">;<\/span><br \/>\nreg         rst_n <span class=\"token operator\">&#061;<\/span> <span class=\"token number\">1<\/span>&#039;b0<span class=\"token punctuation\">;<\/span><br \/>\nwire        seq_out<span class=\"token punctuation\">;<\/span><\/p>\n<p><span class=\"token comment\">\/\/ error Unknown module type: seq_0101 Digital IDE: iverilog \u6839\u76ee\u5f55\u4e0b\u6709\u540c\u540d\u6587\u4ef6\u5bfc\u81f4\u7684\u9519\u8bef<\/span><br \/>\n<span class=\"token comment\">\/\/ 2. \u4f8b\u5316\u8bbe\u8ba1\u5757<\/span><br \/>\nseq_0101 <span class=\"token function\">u_seq_0101<\/span><span class=\"token punctuation\">(<\/span><br \/>\n    <span class=\"token punctuation\">.<\/span><span class=\"token function\">clk<\/span>     <span class=\"token punctuation\">(<\/span>clk<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">,<\/span><br \/>\n    <span class=\"token punctuation\">.<\/span><span class=\"token function\">rst_n<\/span>   <span class=\"token punctuation\">(<\/span>rst_n<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">,<\/span><br \/>\n    <span class=\"token punctuation\">.<\/span><span class=\"token function\">seq_out<\/span> <span class=\"token punctuation\">(<\/span>seq_out<span class=\"token punctuation\">)<\/span><br \/>\n<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">;<\/span><\/p>\n<p><span class=\"token comment\">\/\/ 3. \u751f\u6210\u65f6\u949f&#xff08;5ns\u7ffb\u8f6c&#xff0c;10ns\u5468\u671f&#xff09;<\/span><br \/>\nalways #<span class=\"token number\">5<\/span> clk <span class=\"token operator\">&#061;<\/span> <span class=\"token operator\">~<\/span>clk<span class=\"token punctuation\">;<\/span><\/p>\n<p><span class=\"token comment\">\/\/ 4. \u4eff\u771f\u903b\u8f91<\/span><br \/>\ninitial begin<br \/>\n    <span class=\"token comment\">\/\/ \u6ce2\u5f62\u6587\u4ef6\u751f\u6210<\/span><br \/>\n    $<span class=\"token function\">dumpfile<\/span><span class=\"token punctuation\">(<\/span><span class=\"token string\">&#034;tb_seq_0101.vcd&#034;<\/span><span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">;<\/span><br \/>\n    $<span class=\"token function\">dumpvars<\/span><span class=\"token punctuation\">(<\/span><span class=\"token number\">0<\/span><span class=\"token punctuation\">,<\/span> tb_seq_0101<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">;<\/span>  <span class=\"token comment\">\/\/ \u4fdd\u5b58\u6240\u6709\u5c42\u7ea7\u4fe1\u53f7<\/span><\/p>\n<p>    <span class=\"token comment\">\/\/ \u63a7\u5236\u53f0\u8f93\u51fa&#xff08;ps\u5355\u4f4d&#xff0c;\u65f6\u95f4\u51c6\u786e&#xff09;<\/span><br \/>\n    $<span class=\"token function\">monitor<\/span><span class=\"token punctuation\">(<\/span><span class=\"token string\">&#034;Time&#061;%0t ps: seq_out&#061;%b&#034;<\/span><span class=\"token punctuation\">,<\/span> $time<span class=\"token punctuation\">,<\/span> seq_out<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">;<\/span><\/p>\n<p>    <span class=\"token comment\">\/\/ \u6fc0\u52b1\u6d41\u7a0b&#xff1a;\u590d\u4f4d20ns \u2192 \u6301\u7eed\u8f93\u51fa0101&#8230;<\/span><br \/>\n    rst_n <span class=\"token operator\">&#061;<\/span> <span class=\"token number\">1<\/span>&#039;b0<span class=\"token punctuation\">;<\/span><br \/>\n    #<span class=\"token number\">20<\/span><span class=\"token punctuation\">;<\/span>           <span class=\"token comment\">\/\/ \u590d\u4f4d20ns&#xff08;20000ps&#xff09;<\/span><br \/>\n    rst_n <span class=\"token operator\">&#061;<\/span> <span class=\"token number\">1<\/span>&#039;b1<span class=\"token punctuation\">;<\/span><br \/>\n    #<span class=\"token number\">180<\/span><span class=\"token punctuation\">;<\/span>          <span class=\"token comment\">\/\/ \u8fd0\u884c180ns&#xff08;\u603b200ns&#061;200000ps&#xff09;<\/span><br \/>\n    $finish<span class=\"token punctuation\">;<\/span><br \/>\nend<\/p>\n<p>endmodule<\/p>\n<p>&#096;endif  <span class=\"token comment\">\/\/ TB_SEQ_0101_V \u4fdd\u62a4\u5757\u7ed3\u675f<\/span><\/p>\n<h2>\u7ae0\u8282\u5c0f\u7ed3<\/h2>\n<li>\u6838\u5fc3\u76ee\u6807&#xff1a;VS Code\u642d\u5efaHDL\u5f00\u53d1\u73af\u5883\u7684\u6838\u5fc3\u662f\u901a\u8fc7Digital IDE\u3001Verilog-HDL-Format\u7b49\u63d2\u4ef6&#xff0c;\u5b9e\u73b0\u8bed\u6cd5\u9ad8\u4eae\u3001\u81ea\u52a8\u8865\u5168\u3001\u4e00\u952e\u4f8b\u5316\u3001\u5feb\u901f\u4eff\u771f\u7b49\u529f\u80fd&#xff0c;\u6838\u5fc3\u76ee\u7684\u662f\u63d0\u5347HDL\u5f00\u53d1\u6548\u7387&#xff1b;<\/li>\n<li>\u5173\u952e\u524d\u63d0&#xff1a;\u5fc5\u987b\u5148\u5b89\u88c5Icarus Verilog\u5e76\u914d\u7f6e\u73af\u5883\u53d8\u91cf&#xff0c;\u5426\u5219\u63d2\u4ef6\u7684\u4eff\u771f\u3001\u8bed\u6cd5\u8bca\u65ad\u7b49\u6838\u5fc3\u529f\u80fd\u65e0\u6cd5\u751f\u6548&#xff1b;<\/li>\n<li>\u4f7f\u7528\u89c4\u8303&#xff1a;Digital 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