{"id":67220,"date":"2026-01-28T14:16:56","date_gmt":"2026-01-28T06:16:56","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/67220.html"},"modified":"2026-01-28T14:16:56","modified_gmt":"2026-01-28T06:16:56","slug":"fpga%e5%ae%9e%e7%8e%b0uart%e4%b8%b2%e5%8f%a3%e9%80%9a%e4%bf%a1","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/67220.html","title":{"rendered":"FPGA\u5b9e\u73b0UART\u4e32\u53e3\u901a\u4fe1"},"content":{"rendered":"<h2>FPGA\u5b9e\u73b0UART\u4e32\u53e3\u901a\u4fe1&#xff08;\u539f\u7406&#043;\u5b8c\u6574\u4ee3\u7801\u5b9e\u4f8b&#xff0c;\u65b0\u624b\u53ef\u76f4\u63a5\u590d\u7528&#xff09;<\/h2>\n<p>UART\u4e32\u53e3\u901a\u4fe1\u662fFPGA\u5165\u95e8\u9636\u6bb5\u6700\u7ecf\u5178\u3001\u6700\u5b9e\u7528\u7684\u5f02\u6b65\u901a\u4fe1\u6848\u4f8b&#xff0c;\u65e0\u8bba\u662fFPGA\u4e0e\u5355\u7247\u673a\u3001\u7535\u8111\u7684\u4ea4\u4e92&#xff0c;\u8fd8\u662f\u9879\u76ee\u4e2d\u7684\u7b80\u5355\u6570\u636e\u4f20\u8f93&#xff0c;UART\u90fd\u80fd\u53d1\u6325\u4f5c\u7528\u3002\u672c\u6587\u5c06\u4ece\u6838\u5fc3\u539f\u7406\u3001\u5173\u952e\u53c2\u6570&#xff08;\u91cd\u70b9\u8bb2\u6ce2\u7279\u7387&#xff09;\u3001Verilog\u5b8c\u6574\u4ee3\u7801&#xff0c;\u5230\u4eff\u771f\/\u786c\u4ef6\u9a8c\u8bc1&#xff0c;\u4e00\u6b65\u6b65\u62c6\u89e3&#xff0c;\u65b0\u624b\u770b\u5b8c\u4e5f\u80fd\u5feb\u901f\u4e0a\u624b&#xff0c;\u4ee3\u7801\u53ef\u76f4\u63a5\u9002\u914dAltera\u3001Xilinx\u7b49\u4e3b\u6d41FPGA\u5f00\u53d1\u677f\u3002<\/p>\n<h3>\u4e00\u3001UART\u4e32\u53e3\u901a\u4fe1\u6838\u5fc3\u539f\u7406<\/h3>\n<p>UART&#xff08;\u901a\u7528\u5f02\u6b65\u6536\u53d1\u4f20\u8f93\u5668&#xff09;&#xff0c;\u6838\u5fc3\u5173\u952e\u8bcd\u662f\u201c\u5f02\u6b65\u201d\u2014\u2014\u65e0\u9700\u4e13\u95e8\u7684\u65f6\u949f\u540c\u6b65\u7ebf&#xff0c;\u6536\u53d1\u53cc\u65b9\u53ea\u9700\u7ea6\u5b9a\u597d\u76f8\u540c\u7684\u901a\u4fe1\u53c2\u6570&#xff0c;\u5c31\u80fd\u5b9e\u73b0\u6570\u636e\u7684\u53ef\u9760\u4f20\u8f93\u3002\u4e0d\u540c\u4e8eSPI\u3001I2C\u7684\u540c\u6b65\u901a\u4fe1&#xff0c;UART\u7684\u4f18\u52bf\u7684\u662f\u63a5\u7ebf\u7b80\u5355&#xff08;\u4ec5\u9700TX\u53d1\u9001\u7ebf\u3001RX\u63a5\u6536\u7ebf&#xff0c;\u5171\u5730\u5373\u53ef&#xff09;&#xff0c;\u6210\u672c\u4f4e\u3001\u5b9e\u7528\u6027\u5f3a\u3002<\/p>\n<h4>1. \u6838\u5fc3\u901a\u4fe1\u53c2\u6570&#xff08;\u65b0\u624b\u5fc5\u8bb0&#xff0c;\u6700\u5e38\u7528\u914d\u7f6e&#xff09;<\/h4>\n<p>UART\u7684\u901a\u4fe1\u7a33\u5b9a\u6027&#xff0c;\u5b8c\u5168\u4f9d\u8d56\u4e8e\u6536\u53d1\u53cc\u65b9\u53c2\u6570\u4e00\u81f4&#xff0c;\u5176\u4e2d\u6700\u5173\u952e\u76845\u4e2a\u53c2\u6570\u5982\u4e0b&#xff0c;\u65b0\u624b\u5efa\u8bae\u5148\u638c\u63e1\u9ed8\u8ba4\u914d\u7f6e&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u6ce2\u7279\u7387&#xff1a;\u4e0b\u6587\u91cd\u70b9\u8be6\u89e3&#xff0c;\u6838\u5fc3\u662f\u201c\u6bcf\u79d2\u4f20\u8f93\u7684\u4e8c\u8fdb\u5236\u4f4d\u6570\u201d&#xff0c;\u51b3\u5b9a\u901a\u4fe1\u901f\u5ea6&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u6570\u636e\u4f4d&#xff1a;\u901a\u5e38\u8bbe\u4e3a8\u4f4d&#xff0c;\u5373\u6bcf\u6b21\u4f20\u8f931\u4e2a\u5b57\u8282&#xff08;0~255\u7684\u6570\u503c&#xff09;&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u505c\u6b62\u4f4d&#xff1a;\u901a\u5e38\u8bbe\u4e3a1\u4f4d&#xff0c;\u7528\u4e8e\u6807\u8bc6\u4e00\u4e2a\u5b57\u8282\u7684\u6570\u636e\u4f20\u8f93\u7ed3\u675f&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u6821\u9a8c\u4f4d&#xff1a;\u65b0\u624b\u5efa\u8bae\u8bbe\u4e3a\u201c\u65e0\u6821\u9a8c\u201d&#xff0c;\u7b80\u5316\u8bbe\u8ba1&#xff08;\u6821\u9a8c\u4f4d\u7528\u4e8e\u68c0\u6d4b\u4f20\u8f93\u9519\u8bef&#xff0c;\u5b9e\u9645\u9879\u76ee\u53ef\u6839\u636e\u9700\u6c42\u6dfb\u52a0&#xff09;&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u5e27\u7ed3\u6784&#xff1a;\u4e00\u4e2a\u5b8c\u6574\u7684UART\u6570\u636e\u5e27 &#061; 1\u4f4d\u8d77\u59cb\u4f4d&#xff08;\u4f4e\u7535\u5e730&#xff09; &#043; 8\u4f4d\u6570\u636e\u4f4d&#xff08;\u4f4e\u4f4d\u5148\u884c&#xff09; &#043; 1\u4f4d\u505c\u6b62\u4f4d&#xff08;\u9ad8\u7535\u5e731&#xff09;&#xff0c;\u517110\u4f4d\/\u5b57\u8282\u3002<\/p>\n<\/li>\n<\/ul>\n<h4>2. \u6ce2\u7279\u7387\u8be6\u89e3&#xff08;\u65b0\u624b\u6700\u6613\u56f0\u60d1&#xff0c;\u91cd\u70b9\u7a81\u7834&#xff09;<\/h4>\n<p>\u5f88\u591a\u65b0\u624b\u7b2c\u4e00\u6b21\u63a5\u89e6UART&#xff0c;\u90fd\u4f1a\u88ab\u201c\u6ce2\u7279\u7387\u201d\u641e\u61f5&#xff0c;\u5176\u5b9e\u4e00\u53e5\u8bdd\u5c31\u80fd\u770b\u61c2&#xff0c;\u7ed3\u5408\u5b9e\u4f8b\u62c6\u89e3\u66f4\u6613\u7406\u89e3&#xff1a;<\/p>\n<h5>&#xff08;1&#xff09;\u6ce2\u7279\u7387\u7684\u6838\u5fc3\u5b9a\u4e49<\/h5>\n<p>\u6ce2\u7279\u7387&#xff08;Baud Rate&#xff09;\u7684\u672c\u8d28\u662f&#xff1a;\u4e32\u53e3\u901a\u4fe1\u4e2d\u6bcf\u79d2\u4f20\u8f93\u7684\u4e8c\u8fdb\u5236\u4f4d\u6570&#xff08;bit\/s&#xff09;&#xff0c;\u5355\u4f4d\u662fbps&#xff08;bits per second&#xff09;\u3002\u7b80\u5355\u6765\u8bf4&#xff0c;\u5b83\u5c31\u662f\u4e32\u53e3\u4f20\u8f93\u201c0\u201d\u548c\u201c1\u201d\u8fd9\u4e9b\u7535\u4fe1\u53f7\u7684\u201c\u901f\u5ea6\u201d&#xff0c;\u548c\u6211\u4eec\u4e0b\u8f7d\u6587\u4ef6\u7684\u201c1MB\/s\u201d\u903b\u8f91\u4e00\u81f4&#xff0c;\u53ea\u662f\u5355\u4f4d\u4e0d\u540c&#xff08;\u4e00\u4e2a\u662fbit&#xff0c;\u4e00\u4e2a\u662fByte&#xff09;\u3002<\/p>\n<h5>&#xff08;2&#xff09;\u76f4\u89c2\u5b9e\u4f8b&#xff0c;\u4e00\u770b\u5c31\u61c2<\/h5>\n<p>\u7ed3\u5408\u6211\u4eec\u5e38\u7528\u7684\u6ce2\u7279\u7387\u548cUART\u5e27\u7ed3\u6784&#xff08;10\u4f4d\/\u5b57\u8282&#xff09;&#xff0c;\u4e3e\u4e24\u4e2a\u6700\u5e38\u89c1\u7684\u4f8b\u5b50&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u6ce2\u7279\u7387&#061;9600 \u2192 \u6bcf\u79d2\u4f20\u8f939600\u4e2a\u4e8c\u8fdb\u5236\u4f4d \u2192 \u6bcf\u79d2\u53ef\u4f20\u8f93 9600\u00f710&#061;960 \u4e2a\u5b57\u8282&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u6ce2\u7279\u7387&#061;115200 \u2192 \u6bcf\u79d2\u4f20\u8f93115200\u4e2a\u4e8c\u8fdb\u5236\u4f4d \u2192 \u6bcf\u79d2\u53ef\u4f20\u8f93 115200\u00f710&#061;11520 \u4e2a\u5b57\u8282&#xff1b;<\/p>\n<\/li>\n<\/ul>\n<p>\u5f88\u660e\u663e&#xff0c;\u6ce2\u7279\u7387\u8d8a\u9ad8&#xff0c;\u901a\u4fe1\u901f\u5ea6\u8d8a\u5feb&#xff0c;\u4f46\u540c\u65f6\u5bf9FPGA\u7684\u65f6\u949f\u7cbe\u5ea6\u3001\u786c\u4ef6\u63a5\u7ebf\u7684\u6297\u5e72\u6270\u80fd\u529b\u8981\u6c42\u4e5f\u8d8a\u9ad8\u3002\u65b0\u624b\u5165\u95e8\u5efa\u8bae\u5148\u4ece9600\u6ce2\u7279\u7387\u5f00\u59cb&#xff0c;\u7a33\u5b9a\u6027\u6700\u597d&#xff0c;\u4e0d\u6613\u51fa\u9519\u3002<\/p>\n<h5>&#xff08;3&#xff09;\u6ce2\u7279\u7387\u7684\u6838\u5fc3\u4f5c\u7528&#xff1a;\u4fdd\u8bc1\u6536\u53d1\u540c\u6b65<\/h5>\n<p>\u524d\u9762\u8bf4\u8fc7&#xff0c;UART\u662f\u201c\u5f02\u6b65\u901a\u4fe1\u201d&#xff0c;\u6ca1\u6709\u4e13\u95e8\u7684\u65f6\u949f\u7ebf\u6765\u540c\u6b65\u6536\u53d1\u53cc\u65b9\u7684\u8282\u594f&#xff0c;\u90a3\u600e\u4e48\u4fdd\u8bc1\u63a5\u6536\u7aef\u80fd\u6b63\u786e\u8bc6\u522b\u53d1\u9001\u7aef\u7684\u6570\u636e\u5462&#xff1f;\u7b54\u6848\u5c31\u662f\u201c\u7ea6\u5b9a\u6ce2\u7279\u7387\u201d\u3002<\/p>\n<ul>\n<li>\n<p>\u53d1\u9001\u7aef&#xff1a;\u6309\u7167\u7ea6\u5b9a\u7684\u6ce2\u7279\u7387&#xff0c;\u6bcf\u53d1\u90011\u4e2abit&#xff0c;\u5c31\u7b49\u5f85\u56fa\u5b9a\u7684\u65f6\u95f4&#xff08;\u6bd4\u59829600\u6ce2\u7279\u7387\u4e0b&#xff0c;\u6bcf\u4e2abit\u5360\u7528 1\u00f79600\u2248104\u03bcs&#xff09;&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u63a5\u6536\u7aef&#xff1a;\u540c\u6837\u6309\u7167\u7ea6\u5b9a\u7684\u6ce2\u7279\u7387&#xff0c;\u6bcf\u9694\u56fa\u5b9a\u65f6\u95f4\u53bb\u91c7\u6837\u4e00\u6b21\u63a5\u6536\u5f15\u811a\u7684\u7535\u5e73&#xff08;\u9ad8\u7535\u5e73&#061;1&#xff0c;\u4f4e\u7535\u5e73&#061;0&#xff09;&#xff0c;\u4ece\u800c\u89e3\u6790\u51fa\u6b63\u786e\u7684\u6570\u636e\u3002<\/p>\n<\/li>\n<\/ul>\n<p>\u91cd\u70b9\u63d0\u9192&#xff1a;\u6536\u53d1\u4e24\u7aef\u7684\u6ce2\u7279\u7387\u5fc5\u987b\u5b8c\u5168\u4e00\u81f4&#xff0c;\u5426\u5219\u4f1a\u51fa\u73b0\u201c\u91c7\u6837\u9519\u4f4d\u201d&#xff0c;\u6700\u7ec8\u89e3\u6790\u51fa\u9519\u8bef\u7684\u6570\u636e\u3002\u6bd4\u5982\u53d1\u9001\u7aef\u75289600\u6ce2\u7279\u7387&#xff0c;\u63a5\u6536\u7aef\u75284800\u6ce2\u7279\u7387&#xff0c;\u63a5\u6536\u7aef\u91c7\u6837\u7684\u65f6\u95f4\u4f1a\u8d8a\u6765\u8d8a\u504f&#xff0c;\u4f20\u8fc7\u6765\u7684\u201c0101\u201d\u53ef\u80fd\u4f1a\u88ab\u89e3\u6790\u6210\u201c0011\u201d&#xff0c;\u5bfc\u81f4\u901a\u4fe1\u5931\u8d25\u3002<\/p>\n<h5>&#xff08;4&#xff09;FPGA\u4e2d\u6ce2\u7279\u7387\u7684\u5177\u4f53\u5b9e\u73b0&#xff08;\u5bf9\u5e94\u540e\u7eed\u4ee3\u7801&#xff09;<\/h5>\n<p>FPGA\u7684\u7cfb\u7edf\u65f6\u949f\u901a\u5e38\u662f\u56fa\u5b9a\u7684&#xff08;\u6bd4\u598250MHz\u3001100MHz&#xff09;&#xff0c;\u800c\u6ce2\u7279\u7387\u662f\u6211\u4eec\u7ea6\u5b9a\u7684&#xff08;\u6bd4\u59829600&#xff09;&#xff0c;\u5982\u4f55\u7528FPGA\u7684\u9ad8\u9891\u65f6\u949f&#xff0c;\u6a21\u62df\u51fa\u6ce2\u7279\u7387\u5bf9\u5e94\u7684\u201cbit\u65f6\u95f4\u201d&#xff1f;\u6838\u5fc3\u5c31\u662f\u201c\u65f6\u949f\u5206\u9891\u201d\u3002<\/p>\n<p>\u5206\u9891\u7cfb\u6570\u8ba1\u7b97\u516c\u5f0f&#xff1a;\u5206\u9891\u7cfb\u6570 &#061; \u7cfb\u7edf\u65f6\u949f\u9891\u7387 \u00f7 \u6ce2\u7279\u7387<\/p>\n<p>\u4e3e\u4f8b&#xff08;\u540e\u7eed\u4ee3\u7801\u7528\u7684\u5c31\u662f\u8fd9\u4e2a\u914d\u7f6e&#xff09;&#xff1a;\u7cfb\u7edf\u65f6\u949f&#061;50MHz&#xff0c;\u6ce2\u7279\u7387&#061;9600&#xff0c;\u90a3\u4e48\u5206\u9891\u7cfb\u6570&#061;50_000_000 \u00f7 9600\u22485208\u3002\u4e5f\u5c31\u662f\u8bf4&#xff0c;FPGA\u6bcf\u8ba1\u65705208\u4e2a\u7cfb\u7edf\u65f6\u949f\u8109\u51b2&#xff0c;\u5c31\u5bf9\u5e94UART\u76841\u4e2abit\u4f4d&#xff0c;\u8fd9\u6837\u5c31\u80fd\u7cbe\u51c6\u5339\u914d\u6ce2\u7279\u7387\u7684\u901f\u5ea6\u3002<\/p>\n<h5>&#xff08;5&#xff09;\u5de5\u7a0b\u5e38\u7528\u6ce2\u7279\u7387&#xff08;\u6807\u51c6\u5316&#xff0c;\u522b\u81ea\u5b9a\u4e49&#xff09;<\/h5>\n<p>\u6ce2\u7279\u7387\u662f\u6807\u51c6\u5316\u7684\u53c2\u6570&#xff0c;\u5b9e\u9645\u9879\u76ee\u4e2d\u4e0d\u8981\u968f\u610f\u81ea\u5b9a\u4e49&#xff08;\u6bd4\u5982\u8bbe\u4e3a10000&#xff09;&#xff0c;\u5426\u5219\u5bb9\u6613\u51fa\u73b0\u517c\u5bb9\u6027\u95ee\u9898&#xff0c;\u5e38\u7528\u7684\u6807\u51c6\u5316\u6ce2\u7279\u7387\u5982\u4e0b&#xff0c;\u65b0\u624b\u4f18\u5148\u638c\u63e19600\u548c115200&#xff1a;<\/p>\n<table>\n<tr>\n<p>\u5e38\u7528\u6ce2\u7279\u7387<\/p>\n<p>\u6bcf\u4e2abit\u7684\u65f6\u95f4&#xff08;\u8fd1\u4f3c\u503c&#xff09;<\/p>\n<p>\u6bcf\u79d2\u4f20\u8f93\u5b57\u8282\u6570&#xff08;10\u4f4d\/\u5b57\u8282&#xff09;<\/p>\n<\/tr>\n<tbody>\n<tr>\n<td colspan=\"1\" rowspan=\"1\">\n<p>9600<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>104\u03bcs<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>960<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\">\n<p>19200<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>52\u03bcs<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>1920<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\">\n<p>38400<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>26\u03bcs<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>3840<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\">\n<p>115200<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>8.68\u03bcs<\/p>\n<\/td>\n<td colspan=\"1\" rowspan=\"1\">\n<p>11520<\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>3. FPGA\u5b9e\u73b0UART\u7684\u6838\u5fc3\u601d\u8def<\/h4>\n<p>FPGA\u5b9e\u73b0UART\u901a\u4fe1&#xff0c;\u4e0d\u9700\u8981\u590d\u6742\u7684IP\u6838&#xff08;\u65b0\u624b\u5efa\u8bae\u624b\u5199\u4ee3\u7801&#xff0c;\u7406\u89e3\u66f4\u900f\u5f7b&#xff09;&#xff0c;\u6838\u5fc3\u53ea\u9700\u8981\u4e24\u4e2a\u6a21\u5757&#xff0c;\u518d\u52a0\u4e0a\u4e00\u4e2a\u9876\u5c42\u6a21\u5757\u6574\u5408&#xff0c;\u5c31\u80fd\u5b8c\u6210\u5b8c\u6574\u7684\u6536\u53d1\u529f\u80fd&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u53d1\u9001\u6a21\u5757&#xff08;UART_TX&#xff09;&#xff1a;\u8d1f\u8d23\u5c06FPGA\u5185\u90e8\u7684\u5e76\u884c\u6570\u636e&#xff08;\u6bd4\u59828\u4f4d\u7684\u4e8c\u8fdb\u5236\u6570&#xff09;&#xff0c;\u8f6c\u6362\u6210UART\u4e32\u884c\u6570\u636e&#xff08;\u6309\u7167\u201c\u8d77\u59cb\u4f4d&#043;8\u4f4d\u6570\u636e&#043;\u505c\u6b62\u4f4d\u201d\u7684\u5e27\u7ed3\u6784&#xff09;&#xff0c;\u901a\u8fc7TX\u5f15\u811a\u53d1\u9001\u51fa\u53bb&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u63a5\u6536\u6a21\u5757&#xff08;UART_RX&#xff09;&#xff1a;\u8d1f\u8d23\u901a\u8fc7RX\u5f15\u811a\u63a5\u6536\u5916\u90e8\u7684UART\u4e32\u884c\u6570\u636e&#xff0c;\u8f6c\u6362\u6210FPGA\u5185\u90e8\u80fd\u76f4\u63a5\u4f7f\u7528\u7684\u5e76\u884c\u6570\u636e&#xff0c;\u540c\u65f6\u7ed9\u51fa\u201c\u63a5\u6536\u5b8c\u6210\u201d\u7684\u6807\u5fd7&#xff0c;\u65b9\u4fbf\u540e\u7eed\u903b\u8f91\u8c03\u7528&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u9876\u5c42\u6a21\u5757&#xff08;UART_TOP&#xff09;&#xff1a;\u5c06\u53d1\u9001\u6a21\u5757\u548c\u63a5\u6536\u6a21\u5757\u4f8b\u5316&#xff0c;\u7edf\u4e00\u63a5\u53e3&#xff08;\u65f6\u949f\u3001\u590d\u4f4d\u3001TX\/RX\u5f15\u811a\u3001\u6570\u636e\u63a5\u53e3\u7b49&#xff09;&#xff0c;\u65b9\u4fbf\u4e0b\u8f7d\u5230FPGA\u5f00\u53d1\u677f\u9a8c\u8bc1\u3002<\/p>\n<\/li>\n<\/ul>\n<p>\u6838\u5fc3\u903b\u8f91\u603b\u7ed3&#xff1a;\u7528\u65f6\u949f\u5206\u9891\u751f\u6210\u6ce2\u7279\u7387\u8282\u62cd&#xff0c;\u7528\u72b6\u6001\u673a\u63a7\u5236UART\u5e27\u7ed3\u6784\u7684\u6536\u53d1&#xff0c;\u7528\u5bc4\u5b58\u5668\u7f13\u5b58\u6570\u636e\u548c\u72b6\u6001&#xff0c;\u5b9e\u73b0\u5e76\u884c\u4e0e\u4e32\u884c\u6570\u636e\u7684\u8f6c\u6362\u3002<\/p>\n<h3>\u4e8c\u3001FPGA UART\u5b8c\u6574\u4ee3\u7801\u5b9e\u4f8b&#xff08;Verilog\u5b9e\u73b0&#xff0c;\u65b0\u624b\u53ef\u76f4\u63a5\u590d\u7528&#xff09;<\/h3>\n<p>\u4ee5\u4e0b\u4ee3\u7801\u57fa\u4e8e\u300c50MHz\u7cfb\u7edf\u65f6\u949f\u30019600\u6ce2\u7279\u7387\u30018\u4f4d\u6570\u636e\u4f4d\u30011\u4f4d\u505c\u6b62\u4f4d\u3001\u65e0\u6821\u9a8c\u300d\u7684\u9ed8\u8ba4\u914d\u7f6e&#xff0c;\u5305\u542b\u53d1\u9001\u6a21\u5757\u3001\u63a5\u6536\u6a21\u5757\u3001\u9876\u5c42\u6a21\u5757&#xff0c;\u6ce8\u91ca\u8be6\u7ec6&#xff0c;\u65b0\u624b\u80fd\u770b\u61c2\u6bcf\u4e00\u884c\u7684\u4f5c\u7528&#xff0c;\u4e0b\u8f7d\u5230FPGA\u5f00\u53d1\u677f\u540e&#xff0c;\u914d\u5408\u4e32\u53e3\u52a9\u624b\u5c31\u80fd\u5feb\u901f\u9a8c\u8bc1\u901a\u4fe1\u529f\u80fd\u3002<\/p>\n<h4>1. \u53d1\u9001\u6a21\u5757&#xff08;uart_tx.v&#xff09;<\/h4>\n<p>\u529f\u80fd&#xff1a;\u63a5\u6536FPGA\u5185\u90e8\u76848\u4f4d\u5e76\u884c\u6570\u636e&#xff0c;\u5f53\u68c0\u6d4b\u5230\u201c\u53d1\u9001\u4f7f\u80fd\u201d\u4fe1\u53f7\u540e&#xff0c;\u6309\u7167UART\u5e27\u7ed3\u6784&#xff0c;\u5c06\u5e76\u884c\u6570\u636e\u8f6c\u6362\u6210\u4e32\u884c\u6570\u636e&#xff0c;\u901a\u8fc7tx_pin\u5f15\u811a\u53d1\u9001\u51fa\u53bb&#xff0c;\u53d1\u9001\u5b8c\u6210\u540e\u7ed9\u51fa\u201c\u53d1\u9001\u5b8c\u6210\u201d\u6807\u5fd7\u3002<\/p>\n<p>module uart_tx #( parameter CLK_FREQ &#061; 50_000_000, \/\/ \u7cfb\u7edf\u65f6\u949f\u9891\u7387&#xff08;50MHz&#xff09; parameter BAUD_RATE &#061; 9600 \/\/ \u7ea6\u5b9a\u6ce2\u7279\u7387&#xff08;9600&#xff09; ) ( input clk, \/\/ \u7cfb\u7edf\u65f6\u949f&#xff08;\u8f93\u5165&#xff09; input rst_n, \/\/ \u4f4e\u7535\u5e73\u590d\u4f4d&#xff08;\u8f93\u5165&#xff0c;\u590d\u4f4d\u65f6\u505c\u6b62\u53d1\u9001&#xff09; input [7:0] tx_data, \/\/ \u5f85\u53d1\u9001\u76848\u4f4d\u5e76\u884c\u6570\u636e&#xff08;\u8f93\u5165&#xff09; input tx_en, \/\/ \u53d1\u9001\u4f7f\u80fd&#xff08;\u8f93\u5165&#xff0c;\u9ad8\u7535\u5e73\u6709\u6548&#xff0c;\u89e6\u53d1\u53d1\u9001&#xff09; output reg tx_done, \/\/ \u53d1\u9001\u5b8c\u6210\u6807\u5fd7&#xff08;\u8f93\u51fa&#xff0c;\u9ad8\u7535\u5e73\u8868\u793a\u53d1\u9001\u7ed3\u675f&#xff09; output reg tx_pin \/\/ UART\u53d1\u9001\u5f15\u811a&#xff08;\u8f93\u51fa&#xff0c;\u4e32\u884c\u6570\u636e&#xff09; ); \/\/ \u8ba1\u7b97\u6ce2\u7279\u7387\u5206\u9891\u7cfb\u6570&#xff08;\u6838\u5fc3&#xff1a;\u7528\u7cfb\u7edf\u65f6\u949f\u5206\u9891\u5339\u914d\u6ce2\u7279\u7387&#xff09; localparam BAUD_DIV &#061; CLK_FREQ \/ BAUD_RATE; \/\/ 50_000_000 \/ 9600 \u2248 5208 localparam BAUD_DIV_BIT &#061; $clog2(BAUD_DIV); \/\/ \u8ba1\u7b97\u5206\u9891\u7cfb\u6570\u6240\u9700\u7684\u5bc4\u5b58\u5668\u4f4d\u6570 \/\/ \u5185\u90e8\u5bc4\u5b58\u5668\u5b9a\u4e49 reg [BAUD_DIV_BIT-1:0] baud_cnt; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668&#xff08;\u8ba1\u6570\u5230BAUD_DIV&#xff0c;\u5bf9\u5e941\u4e2abit&#xff09; reg [3:0] bit_cnt; \/\/ \u6570\u636e\u4f4d\u8ba1\u6570\u5668&#xff08;0-9&#xff1a;\u8d77\u59cb\u4f4d&#043;8\u4f4d\u6570\u636e&#043;\u505c\u6b62\u4f4d&#xff09; reg [7:0] tx_data_reg; \/\/ \u6570\u636e\u7f13\u5b58\u5bc4\u5b58\u5668&#xff08;\u7f13\u5b58\u5f85\u53d1\u9001\u6570\u636e&#xff0c;\u9632\u6b62\u53d1\u9001\u4e2d\u6570\u636e\u53d8\u5316&#xff09; reg tx_state; \/\/ \u53d1\u9001\u72b6\u6001\u5bc4\u5b58\u5668&#xff08;0&#xff1a;\u7a7a\u95f2&#xff0c;1&#xff1a;\u53d1\u9001\u4e2d&#xff09; \/\/ \u72b6\u6001\u673a\u903b\u8f91&#xff08;\u6838\u5fc3&#xff1a;\u63a7\u5236UART\u5e27\u7ed3\u6784\u7684\u53d1\u9001\u987a\u5e8f&#xff09; always &#064;(posedge clk or negedge rst_n) begin if(!rst_n) begin \/\/ \u590d\u4f4d\u72b6\u6001&#xff1a;\u6240\u6709\u5bc4\u5b58\u5668\u6e05\u96f6&#xff0c;tx_pin\u7f6e\u9ad8&#xff08;\u7a7a\u95f2\u72b6\u6001&#xff09; tx_state &lt;&#061; 1&#039;b0; baud_cnt &lt;&#061; 0; bit_cnt &lt;&#061; 0; tx_pin &lt;&#061; 1&#039;b1; \/\/ UART\u7a7a\u95f2\u65f6&#xff0c;TX\u5f15\u811a\u4e3a\u9ad8\u7535\u5e73 tx_done &lt;&#061; 1&#039;b0; tx_data_reg &lt;&#061; 8&#039;d0; end else begin tx_done &lt;&#061; 1&#039;b0; \/\/ \u9ed8\u8ba4\u6e05\u96f6\u53d1\u9001\u5b8c\u6210\u6807\u5fd7&#xff08;\u907f\u514d\u6301\u7eed\u9ad8\u7535\u5e73&#xff09; case(tx_state) 1&#039;b0: begin \/\/ \u7a7a\u95f2\u72b6\u6001&#xff1a;\u7b49\u5f85\u53d1\u9001\u4f7f\u80fd\u4fe1\u53f7 tx_pin&lt;&#061; 1&#039;b1; \/\/ \u7a7a\u95f2\u65f6\u4fdd\u6301\u9ad8\u7535\u5e73 if(tx_en) begin \/\/ \u68c0\u6d4b\u5230\u53d1\u9001\u4f7f\u80fd&#xff0c;\u5f00\u59cb\u53d1\u9001 tx_state &lt;&#061; 1&#039;b1; \/\/ \u5207\u6362\u5230\u53d1\u9001\u72b6\u6001 tx_data_reg &lt;&#061; tx_data; \/\/ \u7f13\u5b58\u5f85\u53d1\u9001\u6570\u636e baud_cnt &lt;&#061; 0; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668\u6e05\u96f6 bit_cnt &lt;&#061; 0; \/\/ \u6570\u636e\u4f4d\u8ba1\u6570\u5668\u6e05\u96f6 end end 1&#039;b1: begin \/\/ \u53d1\u9001\u72b6\u6001&#xff1a;\u6309\u7167\u5e27\u7ed3\u6784\u53d1\u9001\u6570\u636e baud_cnt &lt;&#061; baud_cnt &#043; 1&#039;b1; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668\u7d2f\u52a0 if(baud_cnt &#061;&#061; BAUD_DIV &#8211; 1) begin \/\/ \u8ba1\u6570\u5230\u5206\u9891\u7cfb\u6570&#xff0c;\u5b8c\u62101\u4e2abit\u7684\u4f20\u8f93\u65f6\u95f4 baud_cnt &lt;&#061; 0; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668\u6e05\u96f6&#xff0c;\u51c6\u5907\u4e0b\u4e00\u4e2abit bit_cnt &lt;&#061; bit_cnt &#043; 1&#039;b1; \/\/ \u6570\u636e\u4f4d\u8ba1\u6570\u5668\u7d2f\u52a0 \/\/ \u6839\u636e\u8ba1\u6570\u5668\u503c&#xff0c;\u53d1\u9001\u5bf9\u5e94\u4f4d\u7684\u6570\u636e case(bit_cnt) 4&#039;d0: tx_pin &lt;&#061; 1&#039;b0; \/\/ \u53d1\u9001\u8d77\u59cb\u4f4d&#xff08;\u4f4e\u7535\u5e730&#xff09; 4&#039;d1: tx_pin &lt;&#061; tx_data_reg[0]; \/\/ \u53d1\u9001\u7b2c0\u4f4d&#xff08;\u6700\u4f4e\u4f4d&#xff0c;UART\u9ed8\u8ba4\u4f4e\u4f4d\u5148\u884c&#xff09; 4&#039;d2: tx_pin &lt;&#061; tx_data_reg[1]; 4&#039;d3: tx_pin &lt;&#061; tx_data_reg[2]; 4&#039;d4: tx_pin &lt;&#061; tx_data_reg[3]; 4&#039;d5: tx_pin &lt;&#061; tx_data_reg[4]; 4&#039;d6: tx_pin &lt;&#061; tx_data_reg[5]; 4&#039;d7: tx_pin &lt;&#061; tx_data_reg[6]; 4&#039;d8: tx_pin &lt;&#061; tx_data_reg[7]; \/\/ \u53d1\u9001\u7b2c7\u4f4d&#xff08;\u6700\u9ad8\u4f4d&#xff09; 4&#039;d9: tx_pin &lt;&#061; 1&#039;b1; \/\/ \u53d1\u9001\u505c\u6b62\u4f4d&#xff08;\u9ad8\u7535\u5e731&#xff09; default: begin \/\/ \u8ba1\u6570\u8d85\u51fa\u8303\u56f4&#xff0c;\u53d1\u9001\u5b8c\u6210 tx_state &lt;&#061; 1&#039;b0; \/\/ \u5207\u6362\u56de\u7a7a\u95f2\u72b6\u6001 tx_done &lt;&#061; 1&#039;b1; \/\/ \u7f6e\u4f4d\u53d1\u9001\u5b8c\u6210\u6807\u5fd7 end endcase end end endcase end end endmodule <\/p>\n<h4>2. \u63a5\u6536\u6a21\u5757&#xff08;uart_rx.v&#xff09;<\/h4>\n<p>\u529f\u80fd&#xff1a;\u901a\u8fc7rx_pin\u5f15\u811a\u63a5\u6536\u5916\u90e8\u7684UART\u4e32\u884c\u6570\u636e&#xff0c;\u6309\u7167\u7ea6\u5b9a\u7684\u6ce2\u7279\u7387\u548c\u5e27\u7ed3\u6784&#xff0c;\u5c06\u4e32\u884c\u6570\u636e\u8f6c\u6362\u62108\u4f4d\u5e76\u884c\u6570\u636e&#xff0c;\u63a5\u6536\u5b8c\u6210\u540e\u7ed9\u51fa\u201c\u63a5\u6536\u5b8c\u6210\u201d\u6807\u5fd7&#xff0c;\u540c\u65f6\u8f93\u51fa\u5e76\u884c\u6570\u636e\u4f9bFPGA\u5185\u90e8\u4f7f\u7528\u3002<\/p>\n<p>\u5173\u952e\u4f18\u5316&#xff1a;\u5bf9rx_pin\u5f15\u811a\u6253\u4e24\u62cd&#xff08;\u6d88\u6296&#043;\u540c\u6b65&#xff09;&#xff0c;\u89e3\u51b3\u5916\u90e8\u5f02\u6b65\u4fe1\u53f7\u7684\u4e9a\u7a33\u6001\u95ee\u9898&#xff1b;\u5728\u6bcf\u4e2abit\u7684\u4e2d\u95f4\u4f4d\u7f6e\u91c7\u6837&#xff0c;\u63d0\u9ad8\u91c7\u6837\u51c6\u786e\u6027&#xff0c;\u907f\u514d\u8fb9\u6cbf\u5e72\u6270\u3002<\/p>\n<p>module uart_rx #( parameter CLK_FREQ &#061; 50_000_000, \/\/ \u7cfb\u7edf\u65f6\u949f\u9891\u7387&#xff08;50MHz&#xff09; parameter BAUD_RATE &#061; 9600 \/\/ \u7ea6\u5b9a\u6ce2\u7279\u7387&#xff08;9600&#xff09; ) ( input clk, \/\/ \u7cfb\u7edf\u65f6\u949f&#xff08;\u8f93\u5165&#xff09; input rst_n, \/\/ \u4f4e\u7535\u5e73\u590d\u4f4d&#xff08;\u8f93\u5165&#xff0c;\u590d\u4f4d\u65f6\u505c\u6b62\u63a5\u6536&#xff09; input rx_pin, \/\/ UART\u63a5\u6536\u5f15\u811a&#xff08;\u8f93\u5165&#xff0c;\u4e32\u884c\u6570\u636e&#xff09; output reg [7:0] rx_data, \/\/ \u63a5\u6536\u5b8c\u6210\u76848\u4f4d\u5e76\u884c\u6570\u636e&#xff08;\u8f93\u51fa&#xff09; output reg rx_done \/\/ \u63a5\u6536\u5b8c\u6210\u6807\u5fd7&#xff08;\u8f93\u51fa&#xff0c;\u9ad8\u7535\u5e73\u8868\u793a\u63a5\u6536\u6709\u6548&#xff09; ); \/\/ \u6ce2\u7279\u7387\u76f8\u5173\u53c2\u6570\u8ba1\u7b97 localparam BAUD_DIV &#061; CLK_FREQ \/ BAUD_RATE; \/\/ \u5206\u9891\u7cfb\u6570&#xff0c;50_000_000 \/ 9600 \u2248 5208 localparam BAUD_DIV_BIT &#061; $clog2(BAUD_DIV); \/\/ \u5206\u9891\u7cfb\u6570\u6240\u9700\u5bc4\u5b58\u5668\u4f4d\u6570 localparam BAUD_MID &#061; BAUD_DIV \/ 2; \/\/ \u91c7\u6837\u70b9&#xff08;\u6bcf\u4e2abit\u7684\u4e2d\u95f4\u4f4d\u7f6e&#xff0c;\u63d0\u9ad8\u91c7\u6837\u51c6\u786e\u6027&#xff09; \/\/ \u5185\u90e8\u5bc4\u5b58\u5668\u5b9a\u4e49 reg [BAUD_DIV_BIT-1:0] baud_cnt; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668 reg [3:0] bit_cnt; \/\/ \u6570\u636e\u4f4d\u8ba1\u6570\u5668&#xff08;0-9&#xff1a;\u8d77\u59cb\u4f4d&#043;8\u4f4d\u6570\u636e&#043;\u505c\u6b62\u4f4d&#xff09; reg rx_state; \/\/ \u63a5\u6536\u72b6\u6001\u5bc4\u5b58\u5668&#xff08;0&#xff1a;\u7a7a\u95f2&#xff0c;1&#xff1a;\u63a5\u6536\u4e2d&#xff09; reg rx_pin_reg1, rx_pin_reg2; \/\/ \u8f93\u5165\u5f15\u811a\u6253\u4e24\u62cd&#xff08;\u540c\u6b65&#043;\u6d88\u6296&#xff0c;\u89e3\u51b3\u4e9a\u7a33\u6001&#xff09; wire rx_pin_sync; \/\/ \u540c\u6b65\u540e\u7684RX\u5f15\u811a\u4fe1\u53f7&#xff08;\u6d88\u9664\u4e9a\u7a33\u6001\u540e\u7684\u4fe1\u53f7&#xff09; \/\/ \u5f15\u811a\u540c\u6b65\u903b\u8f91&#xff08;\u89e3\u51b3\u5916\u90e8\u5f02\u6b65\u4fe1\u53f7\u7684\u4e9a\u7a33\u6001\u95ee\u9898&#xff0c;FPGA\u8bbe\u8ba1\u5fc5\u52a0&#xff09; always &#064;(posedge clk or negedge rst_n) begin if(!rst_n) begin rx_pin_reg1 &lt;&#061; 1&#039;b1; rx_pin_reg2 &lt;&#061; 1&#039;b1; end else begin rx_pin_reg1 &lt;&#061; rx_pin; \/\/ \u7b2c\u4e00\u62cd\u7f13\u5b58 rx_pin_reg2 &lt;&#061; rx_pin_reg1; \/\/ \u7b2c\u4e8c\u62cd\u7f13\u5b58&#xff0c;\u8f93\u51fa\u540c\u6b65\u540e\u7684\u4fe1\u53f7 end end assign rx_pin_sync &#061; rx_pin_reg2; \/\/ \u540c\u6b65\u540e\u7684RX\u4fe1\u53f7&#xff0c;\u7528\u4e8e\u540e\u7eed\u91c7\u6837 \/\/ \u72b6\u6001\u673a\u903b\u8f91&#xff08;\u6838\u5fc3&#xff1a;\u63a7\u5236UART\u5e27\u7ed3\u6784\u7684\u63a5\u6536\u548c\u91c7\u6837&#xff09; always &#064;(posedge clk or negedge rst_n) begin if(!rst_n) begin \/\/ \u590d\u4f4d\u72b6\u6001&#xff1a;\u6240\u6709\u5bc4\u5b58\u5668\u6e05\u96f6 rx_state &lt;&#061; 1&#039;b0; baud_cnt &lt;&#061; 0; bit_cnt &lt;&#061; 0; rx_data &lt;&#061; 8&#039;d0; rx_done &lt;&#061; 1&#039;b0; end else begin rx_done &lt;&#061; 1&#039;b0; \/\/ \u9ed8\u8ba4\u6e05\u96f6\u63a5\u6536\u5b8c\u6210\u6807\u5fd7 case(rx_state) 1&#039;b0: begin \/\/ \u7a7a\u95f2\u72b6\u6001&#xff1a;\u7b49\u5f85\u8d77\u59cb\u4f4d&#xff08;\u4f4e\u7535\u5e730&#xff09; baud_cnt &lt;&#061; 0; bit_cnt &lt;&#061; 0; if(rx_pin_sync &#061;&#061; 1&#039;b0) begin \/\/ \u68c0\u6d4b\u5230\u8d77\u59cb\u4f4d&#xff0c;\u5f00\u59cb\u63a5\u6536 rx_state &lt;&#061; 1&#039;b1; \/\/ \u5207\u6362\u5230\u63a5\u6536\u72b6\u6001 end end 1&#039;b1: begin \/\/ \u63a5\u6536\u72b6\u6001&#xff1a;\u91c7\u6837\u4e32\u884c\u6570\u636e&#xff0c;\u8f6c\u6362\u4e3a\u5e76\u884c\u6570\u636e baud_cnt &lt;&#061; baud_cnt &#043; 1&#039;b1; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668\u7d2f\u52a0 if(baud_cnt &#061;&#061; BAUD_DIV &#8211; 1) begin \/\/ \u8ba1\u6570\u5230\u5206\u9891\u7cfb\u6570&#xff0c;\u5b8c\u62101\u4e2abit\u7684\u63a5\u6536\u65f6\u95f4 baud_cnt&lt;&#061; 0; \/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668\u6e05\u96f6 bit_cnt &lt;&#061; bit_cnt &#043; 1&#039;b1; \/\/ \u6570\u636e\u4f4d\u8ba1\u6570\u5668\u7d2f\u52a0 end \/\/ \u5728\u6bcf\u4e2abit\u7684\u4e2d\u95f4\u4f4d\u7f6e\u91c7\u6837&#xff08;\u91cd\u70b9\u4f18\u5316&#xff0c;\u63d0\u9ad8\u91c7\u6837\u51c6\u786e\u6027&#xff09; if(baud_cnt &#061;&#061; BAUD_MID &#8211; 1) begin case(bit_cnt) 4&#039;d0: ; \/\/ \u8d77\u59cb\u4f4d&#xff0c;\u4e0d\u91c7\u6837&#xff08;\u4ec5\u7528\u4e8e\u540c\u6b65&#xff09; 4&#039;d1: rx_data[0] &lt;&#061; rx_pin_sync; \/\/ \u91c7\u6837\u7b2c0\u4f4d&#xff08;\u6700\u4f4e\u4f4d&#xff09; 4&#039;d2: rx_data[1] &lt;&#061; rx_pin_sync; 4&#039;d3: rx_data[2] &lt;&#061; rx_pin_sync; 4&#039;d4: rx_data[3] &lt;&#061; rx_pin_sync; 4&#039;d5: rx_data[4] &lt;&#061; rx_pin_sync; 4&#039;d6: rx_data[5] &lt;&#061; rx_pin_sync; 4&#039;d7: rx_data[6] &lt;&#061; rx_pin_sync; 4&#039;d8: rx_data[7] &lt;&#061; rx_pin_sync; \/\/ \u91c7\u6837\u7b2c7\u4f4d&#xff08;\u6700\u9ad8\u4f4d&#xff09; 4&#039;d9: begin \/\/ \u505c\u6b62\u4f4d&#xff0c;\u5224\u65ad\u63a5\u6536\u662f\u5426\u6709\u6548 rx_state &lt;&#061; 1&#039;b0; \/\/ \u5207\u6362\u56de\u7a7a\u95f2\u72b6\u6001 if(rx_pin_sync &#061;&#061; 1&#039;b1) begin \/\/ \u505c\u6b62\u4f4d\u4e3a\u9ad8\u7535\u5e73&#xff0c;\u8bf4\u660e\u63a5\u6536\u6709\u6548 rx_done &lt;&#061; 1&#039;b1; \/\/ \u7f6e\u4f4d\u63a5\u6536\u5b8c\u6210\u6807\u5fd7 end end endcase end end endcase end end endmodule <\/p>\n<h4>3. \u9876\u5c42\u6a21\u5757&#xff08;uart_top.v&#xff09;<\/h4>\n<p>\u529f\u80fd&#xff1a;\u5c06\u53d1\u9001\u6a21\u5757&#xff08;uart_tx&#xff09;\u548c\u63a5\u6536\u6a21\u5757&#xff08;uart_rx&#xff09;\u4f8b\u5316&#xff0c;\u7edf\u4e00\u6240\u6709\u63a5\u53e3&#xff0c;\u65b9\u4fbf\u4e0b\u8f7d\u5230FPGA\u5f00\u53d1\u677f\u4f7f\u7528\u3002\u9876\u5c42\u6a21\u5757\u7684\u63a5\u53e3\u53ef\u76f4\u63a5\u5bf9\u5e94FPGA\u7684\u5f15\u811a&#xff08;\u65f6\u949f\u3001\u590d\u4f4d\u3001TX\/RX\u5f15\u811a\u7b49&#xff09;&#xff0c;\u65e0\u9700\u4fee\u6539\u5185\u90e8\u903b\u8f91&#xff0c;\u4ec5\u9700\u6839\u636e\u5f00\u53d1\u677f\u4fee\u6539\u5f15\u811a\u7ea6\u675f\u5373\u53ef\u3002<\/p>\n<p>module uart_top #( parameter CLK_FREQ &#061; 50_000_000, \/\/ \u7cfb\u7edf\u65f6\u949f\u9891\u7387&#xff08;50MHz&#xff09; parameter BAUD_RATE &#061; 9600 \/\/ \u7ea6\u5b9a\u6ce2\u7279\u7387&#xff08;9600&#xff09; ) ( input clk, \/\/ \u7cfb\u7edf\u65f6\u949f&#xff08;\u8f93\u5165&#xff0c;50MHz&#xff09; input rst_n, \/\/ \u4f4e\u7535\u5e73\u590d\u4f4d&#xff08;\u8f93\u5165&#xff0c;\u5efa\u8bae\u63a5FPGA\u7684\u590d\u4f4d\u6309\u952e&#xff09; input rx_pin, \/\/ UART_RX\u5f15\u811a&#xff08;\u8f93\u5165&#xff0c;\u63a5CH340\u7684TX\u5f15\u811a&#xff09; output tx_pin, \/\/ UART_TX\u5f15\u811a&#xff08;\u8f93\u51fa&#xff0c;\u63a5CH340\u7684RX\u5f15\u811a&#xff09; input [7:0] tx_data_in, \/\/ \u5916\u90e8\u8f93\u5165\u5f85\u53d1\u9001\u6570\u636e&#xff08;\u8f93\u5165&#xff0c;\u53ef\u63a5\u62e8\u7801\u5f00\u5173\u3001\u6309\u952e\u7b49&#xff09; input tx_en_in, \/\/ \u5916\u90e8\u53d1\u9001\u4f7f\u80fd&#xff08;\u8f93\u5165&#xff0c;\u53ef\u63a5\u6309\u952e&#xff0c;\u6309\u4e0b\u89e6\u53d1\u53d1\u9001&#xff09; output tx_done_out,\/\/ \u53d1\u9001\u5b8c\u6210\u8f93\u51fa&#xff08;\u8f93\u51fa&#xff0c;\u53ef\u63a5LED&#xff0c;\u63d0\u793a\u53d1\u9001\u5b8c\u6210&#xff09; output [7:0] rx_data_out,\/\/ \u63a5\u6536\u6570\u636e\u8f93\u51fa&#xff08;\u8f93\u51fa&#xff0c;\u53ef\u63a5LED\u3001\u6570\u7801\u7ba1&#xff0c;\u663e\u793a\u63a5\u6536\u6570\u636e&#xff09; output rx_done_out \/\/ \u63a5\u6536\u5b8c\u6210\u8f93\u51fa&#xff08;\u8f93\u51fa&#xff0c;\u53ef\u63a5LED&#xff0c;\u63d0\u793a\u63a5\u6536\u5b8c\u6210&#xff09; ); \/\/ \u4f8b\u5316\u53d1\u9001\u6a21\u5757&#xff08;\u5c06\u53d1\u9001\u6a21\u5757\u63a5\u5165\u9876\u5c42&#xff0c;\u8fde\u63a5\u5bf9\u5e94\u63a5\u53e3&#xff09; uart_tx #( .CLK_FREQ(CLK_FREQ), .BAUD_RATE(BAUD_RATE) ) uart_tx_inst ( .clk(clk), .rst_n(rst_n), .tx_data(tx_data_in), .tx_en(tx_en_in), .tx_done(tx_done_out), .tx_pin(tx_pin) ); \/\/ \u4f8b\u5316\u63a5\u6536\u6a21\u5757&#xff08;\u5c06\u63a5\u6536\u6a21\u5757\u63a5\u5165\u9876\u5c42&#xff0c;\u8fde\u63a5\u5bf9\u5e94\u63a5\u53e3&#xff09; uart_rx #( .CLK_FREQ(CLK_FREQ), .BAUD_RATE(BAUD_RATE) ) uart_rx_inst ( .clk(clk), .rst_n(rst_n), .rx_pin(rx_pin), .rx_data(rx_data_out), .rx_done(rx_done_out) ); endmodule <\/p>\n<h3>\u4e09\u3001\u4ee3\u7801\u9a8c\u8bc1\u65b9\u6cd5&#xff08;\u65b0\u624b\u5fc5\u770b&#xff0c;\u5feb\u901f\u4e0a\u624b&#xff09;<\/h3>\n<p>\u4ee3\u7801\u5199\u597d\u540e&#xff0c;\u4e0d\u80fd\u76f4\u63a5\u4e0b\u8f7d\u5230FPGA&#xff0c;\u9700\u8981\u5148\u4eff\u771f\u9a8c\u8bc1\u903b\u8f91\u6b63\u786e\u6027&#xff0c;\u518d\u8fdb\u884c\u786c\u4ef6\u9a8c\u8bc1&#xff0c;\u4e24\u6b65\u90fd\u5f88\u7b80\u5355&#xff0c;\u65b0\u624b\u8ddf\u7740\u505a\u5c31\u80fd\u5b8c\u6210\u3002<\/p>\n<h4>1. \u4eff\u771f\u9a8c\u8bc1&#xff08;\u5173\u952e\u6b65\u9aa4&#xff0c;\u907f\u514d\u786c\u4ef6\u8c03\u8bd5\u8e29\u5751&#xff09;<\/h4>\n<p>\u4eff\u771f\u7684\u76ee\u7684\u662f\u9a8c\u8bc1&#xff1a;\u53d1\u9001\u6a21\u5757\u80fd\u6b63\u786e\u8f93\u51faUART\u5e27\u7ed3\u6784&#xff0c;\u63a5\u6536\u6a21\u5757\u80fd\u6b63\u786e\u89e3\u6790\u4e32\u884c\u6570\u636e&#xff0c;\u6838\u5fc3\u6b65\u9aa4\u5982\u4e0b&#xff08;\u4ee5ModelSim\u4e3a\u4f8b&#xff09;&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u65b0\u5efa\u4eff\u771f\u5de5\u7a0b&#xff0c;\u6dfb\u52a0uart_tx.v\u3001uart_rx.v\u3001uart_top.v\u4e09\u4e2a\u6587\u4ef6&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u7f16\u5199\u6d4b\u8bd5\u6fc0\u52b1&#xff08;testbench&#xff09;&#xff1a;\u7ed9\u9876\u5c42\u6a21\u5757\u8f93\u516550MHz\u65f6\u949f\u3001\u4f4e\u7535\u5e73\u590d\u4f4d&#xff08;\u590d\u4f4d100ns\u540e\u91ca\u653e&#xff09;&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u9a71\u52a8tx_en_in\u4e3a\u9ad8\u7535\u5e73&#xff0c;tx_data_in\u8d4b\u503c&#xff08;\u6bd4\u59828&#039;h55&#xff0c;\u5bf9\u5e94\u4e8c\u8fdb\u523601010101&#xff09;&#xff0c;\u89c2\u5bdftx_pin\u8f93\u51fa\u662f\u5426\u7b26\u5408\u201c1\u4f4d\u8d77\u59cb\u4f4d&#043;8\u4f4d\u6570\u636e&#043;1\u4f4d\u505c\u6b62\u4f4d\u201d\u7684\u5e27\u7ed3\u6784&#xff1b;<\/p>\n<\/li>\n<li>\n<p>\u5411rx_pin\u8f93\u5165\u6a21\u62df\u7684UART\u4e32\u884c\u6570\u636e&#xff08;\u6bd4\u59828&#039;hAA\u5bf9\u5e94\u7684\u4e32\u884c\u5e27&#xff09;&#xff0c;\u89c2\u5bdfrx_data_out\u662f\u5426\u80fd\u6b63\u786e\u89e3\u6790\u51fa8&#039;hAA&#xff0c;rx_done_out\u662f\u5426\u80fd\u6b63\u5e38\u7f6e\u4f4d\u3002<\/p>\n<\/li>\n<\/ul>\n<p>\u5c0f\u6280\u5de7&#xff1a;\u4eff\u771f\u65f6\u91cd\u70b9\u89c2\u5bdf\u201c\u6ce2\u7279\u7387\u8ba1\u6570\u5668\u201d\u548c\u201c\u6570\u636e\u4f4d\u8ba1\u6570\u5668\u201d&#xff0c;\u786e\u4fdd\u8ba1\u6570\u8282\u594f\u6b63\u786e&#xff0c;\u91c7\u6837\u4f4d\u7f6e\u5728\u6bcf\u4e2abit\u7684\u4e2d\u95f4\u3002<\/p>\n<h4>2. \u786c\u4ef6\u9a8c\u8bc1&#xff08;\u6700\u7ec8\u9a8c\u8bc1&#xff0c;\u770b\u5230\u5b9e\u9645\u6548\u679c&#xff09;<\/h4>\n<p>\u786c\u4ef6\u9a8c\u8bc1\u9700\u8981\u51c6\u5907&#xff1a;FPGA\u5f00\u53d1\u677f&#xff08;\u4efb\u610f\u578b\u53f7\u5747\u53ef&#xff09;\u3001CH340 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