San Jose, CA \u2013Dec 16, 2025 \u2013S2C, MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare's SIM-V virtual platform, S2C's Genesis Architectand\u00a0Prodigy FPGA Prototyping Systems, and Andes' high-performance AX46MPV RISC-V CPU core, providing a unified environment for hardware and software co-verification.<\/p>\n
As RISC-V designs move toward high-performance, multi-core, and highly customized architectures, pre-silicon software development and system validation have become more challenging. This co-emulation solution supports a \u201cshift-left\u201d verification approach, allowing hardware and software teams to work in parallel. The result is reduced development time and lower project risk.<\/p>\n<\/p>\n
MachineWare contributes its SIM-V full-system virtual platform, based on SystemC TLM-2.0, which offers high simulation speed and extensibility. SIM-V integrates with a broad range of third-party toolchains for debugging, testing, and coverage analysis.<\/p>\n
The key strengths of SIM-V lie in its exceptional simulation performance and comprehensive support for Andes RISC-V cores. The platform provides instruction-accurate reference models that fully implement the AndeStar V5 Instruction Set Architecture, including the RISC-V Vector (V) extension. Using the SIM-V Extension API, designers can model, validate, and debug proprietary processor enhancements within a complete system simulation, with full trace and introspection capabilities for detailed visibility. "Our customers need tools that accelerate development without compromising accuracy," said Lukas J\u00fcnger, CEO of MachineWare. "This co\u2011emulation solution gives them the ability to validate hardware and software in parallel, reduce integration risks, and bring products to market faster than ever before."<\/p>\n<\/p>\n
Andes Technology contributes its advanced CPU IP, including the high-performance AndesCore\u2122 AX46MPV multicore processor. AX46MPV is an 8-stage superscalar 64-bit RISC-V CPU that supports up to 16 cores with a multi-level cache structure, a powerful Vector Processing Unit (VPU) with up to 1024-bit VLEN and High-Bandwidth Vector Memory (HVM), and ISA customizations via Andes Custom Extension\u2122 (ACE).<\/p>\n
With full MMU support for Linux and versatile performance scaling, AX46MPV is well suited for data center AI computation elements, Linux-capable edge AI platforms, and high-performance MPUs in storage, networking, and other performance-critical domains.<\/p>\n
\u201cOur customers value our RISC-V IP for its performance, robustness, and ability to add custom extensions that accelerate their key applications.\u201d said Dr. Charlie Su, President and CTO of Andes Technology. \u201cBy collaborating with MachineWare and S2C on this co-emulation approach, we're giving them the ability to evaluate that impact and co-optimize their software stack and silicon architecture before committing to costly silicon tapeout."<\/p>\n<\/p>\n
S2C connects the SIM-V virtual platform to physical hardware through its Genesis Architect and Prodigy FPGA-based prototyping systems. In this hybrid setup, CPU models run in SIM-V while peripheral subsystems execute at high speed on FPGA, connected via a high-speed transactional bridge. This approach provides a realistic system context capable of running full software stacks\u2014from bootloader to application\u2014while retaining detailed debug visibility.<\/p>\n
\u00a0<\/p>\n
The joint solution supports multiple critical development stages:<\/p>\n
l\u00a0\u00a0Pre-silicon software development<\/p>\n
l\u00a0\u00a0Hardware\/software co-verification<\/p>\n
l\u00a0\u00a0System performance analysis and tuning<\/p>\n
l\u00a0\u00a0Custom ISA extension development and debug<\/p>\n
\u201cThrough co-emulation, our customers can accelerate time-to-market, reduce costs, and ensure software maturity\u2014while benefiting from both cycle-accurate debugging and high-speed execution,\u201d said Ying, VP of S2C. \u201cBut we can\u2019t achieve this alone. We will continue to build on the high-performance advantages of hardware-assisted verification and work closely with our partners to collaboratively deliver shift-left solutions across the ecosystem.\u201d<\/p>\n<\/p>\n
S2C, MachineWare, and Andes remain committed to advancing verification methodologies and providing scalable, efficient, and robust development tools for the RISC-V community. Together, the companies aim to strengthen the ecosystem for next-generation RISC-V chip design.<\/p>\n<\/p>\n
MachineWare GmbH, headquartered in Aachen, Germany, is a leading provider of high-speed virtual prototyping solutions for pre-silicon software validation and testing. Its flagship platform, SIM\u2011V, delivers industry-leading RISC\u2011V simulation performance and extensibility, enabling accurate modeling of complex SoCs and custom ISA extensions. The company serves diverse sectors including AI, automotive, and telecommunications.<\/p>\n<\/p>\n
As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533[1];\u00a0SIN: US03420C2089[2];\u00a0ISIN: US03420C1099[3]) is driving the global adoption of RISC-V. Andes\u2019 extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters.\u00a0With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware\/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices.\u00a0Over\u00a017 billion Andes-powered SoCs\u00a0are driving innovations globally.\u00a0Discover more at\u00a0www.andestech.com[4]\u00a0and connect with Andes on\u00a0LinkedIn[5],\u00a0X (formerly Twitter)[6]\u00a0,\u00a0YouTube[7]\u00a0and\u00a0Bilibili[8].<\/p>\n
S2Cis a leading global supplier of FPGA prototyping solutions for today's innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 11 of the world's top 25 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer's SoC and ASIC verification needs. S2C has offices and sales representatives in San Jose, Seoul, Tokyo, Shanghai, Hsinchu, India, Europe and ANZ.<\/p><\/p>\n","protected":false},"excerpt":{"rendered":"
San Jose, CA \u2013Dec 16, 2025 \u2013S2C, MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWares SIM-V v<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[6993,941,998,50],"topic":[],"class_list":["post-66159","post","type-post","status-publish","format-standard","hentry","category-server","tag-prototyping","tag-fpga","tag-risc-v","tag-50"],"yoast_head":"\n