AXI\u603b\u7ebf\u7cfb\u7edf\u5b66\u4e60，\u8fd9\u4e2a\u603b\u7ebf\u662f\u975e\u5e38\u91cd\u8981，\u5f88\u591a\u5730\u65b9\u90fd\u4f1a\u8981\u7528，\u7528\u5230\u7684\u8bdd\u4e00\u5b9a\u8981\u597d\u597d\u5b66\u4e60
\n\u767e\u5ea6\u7f51\u76d8\u94fe\u63a5：https:\/\/pan.baidu.com\/s\/1rDsLAXGj8WbX82teSkhuIw?pwd=1234 \u63d0\u53d6\u7801: 1234
\n\u5305\u542bFPGA\u7cfb\u7edf\u5b66\u4e60\u8d44\u6599，\u514d\u8d39\u5206\u4eab<\/p>\n
AXI（Advanced eXtensible Interface，\u9ad8\u7ea7\u53ef\u6269\u5c55\u63a5\u53e3）\u662fARM\u516c\u53f8\u5236\u5b9a\u7684AMBA\u603b\u7ebf\u534f\u8bae\u7c07\u4e2d\u7684\u6838\u5fc3\u6210\u5458，\u5c5e\u4e8e\u9ad8\u6027\u80fd\u7247\u4e0a\u4e92\u8054\u603b\u7ebf（On-Chip Bus），\u4e3b\u6d41\u7248\u672c\u4e3a AXI3 \u548c AXI4（\u76ee\u524dFPGA\/SoC\u4e2d99%\u4f7f\u7528AXI4），\u662f\u5f53\u524d\u82af\u7247\u5185\u3001\u5f02\u6784\u82af\u7247\u95f4\u6570\u636e\u4ea4\u4e92\u7684\u4e8b\u5b9e\u6807\u51c6\u3002<\/p>\n
AXI\u603b\u7ebf\u8bbe\u8ba1\u7684\u6838\u5fc3\u76ee\u6807：\u9ad8\u6027\u80fd\u3001\u9ad8\u5e26\u5bbd\u3001\u4f4e\u5ef6\u8fdf\u3001\u9ad8\u7075\u6d3b\u6027，\u4e13\u95e8\u89e3\u51b3\u7247\u5185\u591a\u6a21\u5757（CPU\u3001FPGA\u903b\u8f91\u3001DDR\u3001DMA\u3001\u5916\u8bbeIP）\u4e4b\u95f4\u7684\u9ad8\u901f\u6570\u636e\u4ea4\u4e92\u95ee\u9898，\u4e5f\u662fFPGA\u5f00\u53d1\u4e2d\u5fc5\u987b\u638c\u63e1\u7684\u6838\u5fc3\u534f\u8bae\u3002<\/p>\n
AXI\u80fd\u6210\u4e3a\u4e3b\u6d41，\u6838\u5fc3\u6e90\u4e8e\u5176\u8bbe\u8ba1\u4e0a\u7684\u4f18\u79c0\u7279\u6027，\u6240\u6709\u7279\u6027\u5747\u4e3a\u300c\u63d0\u5347\u4f20\u8f93\u6548\u7387\u3001\u964d\u4f4e\u8bbe\u8ba1\u590d\u6742\u5ea6\u300d\u670d\u52a1，\u4e5f\u662f\u533a\u522b\u4e8eAHB\/APB\u7b49\u4f20\u7edfAMBA\u603b\u7ebf\u7684\u5173\u952e：<\/p>\n
AXI\u7684\u6240\u6709\u6570\u636e\u4ea4\u4e92，\u672c\u8d28\u90fd\u662f\u8fd95\u4e2a\u5355\u5411\u901a\u9053\u7684\u7ec4\u5408\u4f20\u8f93，\u6240\u6709\u901a\u9053\u5747\u9075\u5faaREADY-VALID\u63e1\u624b\u673a\u5236，\u5199\u4e8b\u52a1\u7528\u52303\u4e2a\u901a\u9053，\u8bfb\u4e8b\u52a1\u7528\u52302\u4e2a\u901a\u9053，\u65e0\u4efb\u4f55\u4ea4\u53c9\u590d\u7528，\u8fd9\u662fAXI\u6700\u6838\u5fc3\u7684\u8bbe\u8ba1，\u5fc5\u987b\u7262\u8bb0：<\/p>\n
\u2705 \u6838\u5fc3\u539f\u5219：\u6240\u6709\u901a\u9053\u90fd\u662f\u300c\u5355\u5411\u300d\u7684，\u8981\u4e48\u662f\u300c\u4e3b\u673a\u2192\u4ece\u673a\u300d，\u8981\u4e48\u662f\u300c\u4ece\u673a\u2192\u4e3b\u673a\u300d，\u6ca1\u6709\u53cc\u5411\u4fe1\u53f7\u7ebf！<\/p>\n
\u4e3b\u673a\u5411\u4ece\u673a\u5199\u5165\u6570\u636e\u7684\u5b8c\u6574\u6d41\u7a0b，\u4f9d\u8d563\u4e2a\u72ec\u7acb\u901a\u9053\u7684\u534f\u540c，\u901a\u9053\u987a\u5e8f\u53ef\u7075\u6d3b，\u4e0d\u5f3a\u5236\u4e25\u683c\u5148\u540e：<\/p>\n
\u4e3b\u673a\u4ece\u4ece\u673a\u8bfb\u53d6\u6570\u636e\u7684\u5b8c\u6574\u6d41\u7a0b，\u4f9d\u8d562\u4e2a\u72ec\u7acb\u901a\u9053\u7684\u534f\u540c：<\/p>\n
\u5b8c\u6574\u7248AXI4\u534f\u8bae\u7684\u4fe1\u53f7\u7ebf\u8f83\u591a\u3001\u903b\u8f91\u590d\u6742，\u4f46ARM\u5728AXI4\u57fa\u7840\u4e0a，\u9488\u5bf9\u4e0d\u540c\u5e94\u7528\u573a\u666f\u88c1\u526a\u51fa\u4e86\u4e09\u4e2a\u6781\u7b80\u3001\u9ad8\u6548\u7684\u5b50\u96c6，\u8fd9\u4e09\u4e2a\u5b50\u96c6\u662f FPGA\u5f00\u53d1\u4e2d\u552f\u4e00\u4f1a\u7528\u5230\u7684AXI\u5f62\u5f0f（\u65e0\u4f8b\u5916），\u4e5f\u662fFPGA\u5382\u5546\u5b98\u65b9IP\u6838\u7684\u6807\u914d\u63a5\u53e3，99%\u7684FPGA\u5de5\u7a0b\u53ea\u7528\u5230\u8fd9\u4e09\u4e2a\u5b50\u96c6，\u4f18\u5148\u7ea7：AXI4-Lite \u2248 AXI4-Stream > AXI4，\u4e09\u8005\u7684\u5b9a\u4f4d\u3001\u7279\u6027\u3001\u5e94\u7528\u573a\u666f\u4e25\u683c\u533a\u5206，\u65e0\u517c\u5bb9\u5173\u7cfb，\u4f46\u8bbe\u8ba1\u601d\u60f3\u4e00\u81f4：<\/p>\n
\u2728 \u6838\u5fc3\u533a\u522b：AXI4-Stream \u65e0\u5730\u5740\u7ebf！\u65e0\u5730\u5740\u3001\u65e0\u63a7\u5236\u4fe1\u606f，\u53ea\u6709\u7eaf\u6570\u636e\u6d41，\u662f\u4e13\u95e8\u4e3a\u300c\u8fde\u7eed\u4e32\u884c\u6570\u636e\u4f20\u8f93\u300d\u8bbe\u8ba1\u7684\u603b\u7ebf\u3002<\/p>\n
\u5728FPGA\u4e2d，AXI\u603b\u7ebf\u7684\u89d2\u8272\u662f \u300c\u7247\u5185\u4e92\u8054\u6865\u6881\u300d：<\/p>\n
\u8fd9\u662fFPGA\u5b9e\u73b0AXI\u603b\u7ebf\u7684\u4e3b\u6d41\u65b9\u5f0f\u3001\u6700\u4f18\u65b9\u5f0f\u3001\u6700\u9ad8\u6548\u65b9\u5f0f，\u4e5f\u662f\u6240\u6709FPGA\u5de5\u7a0b\u5e08\u7684\u6807\u914d\u5f00\u53d1\u6d41\u7a0b\u3002\u5b98\u65b9AXI IP\u6838\u5df2\u7ecf\u7531\u5382\u5546\u505a\u4e86\u6781\u81f4\u4f18\u5316：<\/p>\n
FPGA\u5f00\u53d1AXI\u7684\u672c\u8d28：\u62fc\u79ef\u6728\u5f0f\u5f00\u53d1 \u2014\u2014 \u628a\u5b98\u65b9AXI IP\u6838\u5f53\u4f5c\u300c\u79ef\u6728\u300d，\u7528\u56fe\u5f62\u5316\u5de5\u5177\u628a\u8fd9\u4e9b\u79ef\u6728\u901a\u8fc7AXI\u603b\u7ebf\u8fde\u63a5\u8d77\u6765，\u4ec5\u9700\u7f16\u5199\u5c11\u91cf\u903b\u8f91\u5b8c\u6210\u300c\u6570\u636e\u8f6c\u53d1\/\u5bc4\u5b58\u5668\u914d\u7f6e\u300d，\u5373\u53ef\u5b9e\u73b0\u5b8c\u6574\u7684AXI\u603b\u7ebf\u529f\u80fd\u3002<\/p>\n
\u6839\u636e\u9700\u6c42\u9009\u62e9\u5bf9\u5e94\u7684AXI IP\u6838，\u6bd4\u5982：<\/p>\n
\u6240\u6709AXI IP\u6838\u90fd\u652f\u6301\u56fe\u5f62\u5316\u914d\u7f6e，\u6bd4\u5982：<\/p>\n
\u4e24\u5927\u5382\u5546\u5747\u63d0\u4f9b\u53ef\u89c6\u5316\u7684\u300c\u5757\u8bbe\u8ba1（Block Design）\u300d\u5de5\u5177：<\/p>\n
\u5de5\u5177\u4f1a\u6839\u636e\u56fe\u5f62\u5316\u7684\u4e92\u8054\u5173\u7cfb，\u81ea\u52a8\u751f\u6210\u5b8c\u6574\u7684HDL\u4ee3\u7801（Verilog\/VHDL），\u76f4\u63a5\u7f16\u8bd1\u5373\u53ef\u4e0b\u8f7d\u5230FPGA\u82af\u7247\u4e2d\u8fd0\u884c，\u5168\u7a0b\u96f6\u624b\u5199AXI\u534f\u8bae\u903b\u8f91\u3002<\/p>\n
\u9700\u6c42：\u901a\u8fc7AXI4-Lite\u63a7\u5236FPGA\u7684LED\u706f\u4eae\u706d<\/p>\n
\u2728 \u8fd9\u4e2a\u6848\u4f8b\u7684\u6838\u5fc3：\u4f60\u4e0d\u9700\u8981\u61c2\u4efb\u4f55AXI\u534f\u8bae\u7ec6\u8282，\u53ea\u9700\u8981\u62fcIP\u6838，\u5c31\u80fd\u5b9e\u73b0AXI\u603b\u7ebf\u7684\u5b8c\u6574\u529f\u80fd\u3002<\/p>\n
\u5f53\u5b98\u65b9IP\u6838\u65e0\u6cd5\u6ee1\u8db3\u5b9a\u5236\u5316\u9700\u6c42\u65f6，\u9700\u8981\u624b\u52a8\u7f16\u5199\u5c11\u91cfVerilog\/VHDL\u4ee3\u7801\u5b9e\u73b0AXI\u63a5\u53e3\u9002\u914d，\u6bd4\u5982：<\/p>\n
\u624b\u52a8\u7f16\u5199\u7684\u6838\u5fc3\u662f：\u53ea\u5199\u300cAXI\u63a5\u53e3\u9002\u914d\u5c42（Wrapper）\u300d，\u4e0d\u5199\u5b8c\u6574\u7684AXI\u534f\u8bae\u6808！<\/p>\n
\u9700\u6c42：FPGA\u5185\u90e8\u5b9e\u73b0\u4e00\u4e2a\u7b80\u5355\u7684AXI4-Lite\u4ece\u673a，\u5305\u542b2\u4e2a32\u4f4d\u5bc4\u5b58\u5668（\u5730\u57400x00：\u63a7\u5236\u5bc4\u5b58\u5668，\u5730\u57400x04：\u72b6\u6001\u5bc4\u5b58\u5668），\u4e3b\u673a\u53ef\u901a\u8fc7AXI4-Lite\u8bfb\u5199\u8fd9\u4e24\u4e2a\u5bc4\u5b58\u5668\u3002
\n\u6838\u5fc3\u903b\u8f91：AXI4-Lite\u53ea\u652f\u6301\u5355\u62cd\u4f20\u8f93，\u53ea\u9700\u5904\u7406AWADDR\/AWVALID\/AWREADY（\u5199\u5730\u5740）\u3001WVALID\/WREADY\/WDATA（\u5199\u6570\u636e）\u3001BVALID\/BREADY\/BRESP（\u5199\u54cd\u5e94）\u3001ARADDR\/ARVALID\/ARREADY（\u8bfb\u5730\u5740）\u3001RVALID\/RREADY\/RDATA\/RRESP（\u8bfb\u6570\u636e）\u7684\u63e1\u624b\u5373\u53ef，\u65e0\u7a81\u53d1\u903b\u8f91\u3002
\n\u6838\u5fc3Verilog\u4ee3\u7801\u6846\u67b6（\u5173\u952e\u903b\u8f91，\u7cbe\u7b80\u7248）<\/p>\n
\/\/ AXI4-Lite \u4ece\u673a\u6838\u5fc3\u903b\u8f91 (32\u4f4d\u5730\u5740\/\u6570\u636e)
\nmodule axi4_lite_slave(
\n input clk,
\n input rst_n,
\n \/\/ \u5199\u5730\u5740\u901a\u9053
\n input [31:0] s_axi_awaddr,
\n input s_axi_awvalid,
\n output reg s_axi_awready,
\n \/\/ \u5199\u6570\u636e\u901a\u9053
\n input [31:0] s_axi_wdata,
\n input s_axi_wvalid,
\n output reg s_axi_wready,
\n \/\/ \u5199\u54cd\u5e94\u901a\u9053
\n output reg [1:0] s_axi_bresp,
\n output reg s_axi_bvalid,
\n input s_axi_bready,
\n \/\/ \u8bfb\u5730\u5740\u901a\u9053
\n input [31:0] s_axi_araddr,
\n input s_axi_arvalid,
\n output reg s_axi_arready,
\n \/\/ \u8bfb\u6570\u636e\u901a\u9053
\n output reg [31:0] s_axi_rdata,
\n output reg [1:0] s_axi_rresp,
\n output reg s_axi_rvalid,
\n input s_axi_rready
\n);
\n\/\/ \u81ea\u5b9a\u4e49\u5bc4\u5b58\u5668：\u5730\u57400x00=\u63a7\u5236\u5bc4\u5b58\u5668，0x04=\u72b6\u6001\u5bc4\u5b58\u5668
\nreg [31:0] ctrl_reg;
\nreg [31:0] stat_reg;<\/p>\n
\/\/ \u5199\u4e8b\u52a1：\u5730\u5740\u63e1\u624b+\u6570\u636e\u63e1\u624b+\u54cd\u5e94
\nalways @(posedge clk or negedge rst_n) begin
\n if(!rst_n) begin
\n s_axi_awready <= 1'b0;
\n s_axi_wready <= 1'b0;
\n s_axi_bvalid <= 1'b0;
\n ctrl_reg <= 32'd0;
\n end else begin
\n \/\/ \u5199\u5730\u5740\u5c31\u7eea：\u5f53\u5730\u5740\u6709\u6548\u4e14\u6570\u636e\u672a\u5c31\u7eea\u65f6
\n if(s_axi_awvalid && !s_axi_awready) begin
\n s_axi_awready <= 1'b1;
\n end
\n \/\/ \u5199\u6570\u636e\u5c31\u7eea：\u5f53\u5730\u5740\u5df2\u5c31\u7eea\u4e14\u6570\u636e\u6709\u6548\u65f6
\n if(s_axi_wvalid && !s_axi_wready && s_axi_awready) begin
\n s_axi_wready <= 1'b1;
\n \/\/ \u6839\u636e\u5730\u5740\u5199\u5bc4\u5b58\u5668
\n case(s_axi_awaddr)
\n 32'h00000000: ctrl_reg <= s_axi_wdata;
\n 32'h00000004: stat_reg <= s_axi_wdata;
\n default: ;
\n endcase
\n \/\/ \u5199\u54cd\u5e94\u6709\u6548
\n s_axi_bvalid <= 1'b1;
\n s_axi_bresp <= 2'b00; \/\/ \u54cd\u5e94：\u6210\u529f
\n end
\n \/\/ \u54cd\u5e94\u63e1\u624b\u5b8c\u6210，\u6e05\u96f6\u5c31\u7eea\u548c\u6709\u6548\u4fe1\u53f7
\n if(s_axi_bvalid && s_axi_bready) begin
\n s_axi_awready <= 1'b0;
\n s_axi_wready <= 1'b0;
\n s_axi_bvalid <= 1'b0;
\n end
\n end
\nend<\/p>\n
\/\/ \u8bfb\u4e8b\u52a1：\u5730\u5740\u63e1\u624b+\u6570\u636e\u63e1\u624b
\nalways @(posedge clk or negedge rst_n) begin
\n if(!rst_n) begin
\n s_axi_arready <= 1'b0;
\n s_axi_rvalid <= 1'b0;
\n s_axi_rdata <= 32'd0;
\n end else begin
\n \/\/ \u8bfb\u5730\u5740\u5c31\u7eea：\u5f53\u5730\u5740\u6709\u6548\u4e14\u6570\u636e\u672a\u5c31\u7eea\u65f6
\n if(s_axi_arvalid && !s_axi_arready) begin
\n s_axi_arready <= 1'b1;
\n \/\/ \u6839\u636e\u5730\u5740\u8bfb\u5bc4\u5b58\u5668
\n case(s_axi_araddr)
\n 32'h00000000: s_axi_rdata <= ctrl_reg;
\n 32'h00000004: s_axi_rdata <= stat_reg;
\n default: s_axi_rdata <= 32'h00000000;
\n endcase
\n \/\/ \u8bfb\u6570\u636e\u6709\u6548
\n s_axi_rvalid <= 1'b1;
\n s_axi_rresp <= 2'b00; \/\/ \u54cd\u5e94：\u6210\u529f
\n end
\n \/\/ \u8bfb\u6570\u636e\u63e1\u624b\u5b8c\u6210，\u6e05\u96f6\u5c31\u7eea\u548c\u6709\u6548\u4fe1\u53f7
\n if(s_axi_rvalid && s_axi_rready) begin
\n s_axi_arready <= 1'b0;
\n s_axi_rvalid <= 1'b0;
\n end
\n end
\nend
\nendmodule<\/p>\n
\u9700\u6c42：\u5c06\u4e00\u8defAXI4-Stream\u8f93\u5165\u6570\u636e\u6d41，\u65e0\u4fee\u6539\u8f6c\u53d1\u5230\u4e00\u8def\u8f93\u51fa\u6570\u636e\u6d41，\u6838\u5fc3\u662f\u5b9e\u73b0TVALID-TREADY\u63e1\u624b\u548cTDATA\u6570\u636e\u4f20\u8f93，\u53ef\u9009TLAST\u5e27\u7ed3\u675f\u6807\u8bb0\u3002
\n\u6838\u5fc3\u7279\u70b9：\u65e0\u5730\u5740\u3001\u65e0\u63a7\u5236，\u53ea\u6709\u7eaf\u6570\u636e\u6d41，\u4ee3\u7801\u6781\u7b80，\u662fFPGA\u4e2d\u6700\u5e38\u5199\u7684\u903b\u8f91\u4e4b\u4e00\u3002
\n\u6838\u5fc3Verilog\u4ee3\u7801（\u76f4\u63a5\u53ef\u7528，\u5b8c\u6574\u7248）<\/p>\n
\/\/ AXI4-Stream \u6570\u636e\u6d41\u8f6c\u53d1\u6a21\u5757 (64\u4f4d\u6570\u636e\u4f4d\u5bbd，\u5e26TLAST\u5e27\u7ed3\u675f)
\nmodule axi4_stream_forward(
\n input clk,
\n input rst_n,
\n \/\/ AXI4-Stream \u8f93\u5165\u63a5\u53e3
\n input [63:0] s_axis_tdata,
\n input s_axis_tvalid,
\n output reg s_axis_tready,
\n input s_axis_tlast,
\n \/\/ AXI4-Stream \u8f93\u51fa\u63a5\u53e3
\n output reg [63:0] m_axis_tdata,
\n output reg m_axis_tvalid,
\n input m_axis_tready,
\n output reg m_axis_tlast
\n);
\n\/\/ \u6838\u5fc3\u903b\u8f91：READY-VALID\u63e1\u624b + \u6570\u636e\u900f\u4f20
\nalways @(posedge clk or negedge rst_n) begin
\n if(!rst_n) begin
\n s_axis_tready <= 1'b0;
\n m_axis_tvalid <= 1'b0;
\n m_axis_tdata <= 64'd0;
\n m_axis_tlast <= 1'b0;
\n end else begin
\n \/\/ \u63a5\u6536\u5c31\u7eea：\u5f53\u8f93\u51fa\u7aef\u5c31\u7eea\u65f6，\u624d\u5141\u8bb8\u8f93\u5165\u7aef\u4f20\u8f93
\n s_axis_tready <= m_axis_tready;
\n \/\/ \u8f93\u51fa\u6709\u6548：\u5f53\u8f93\u5165\u7aef\u6709\u6548\u4e14\u63a5\u6536\u5c31\u7eea\u65f6
\n if(s_axis_tvalid && s_axis_tready) begin
\n m_axis_tvalid <= 1'b1;
\n m_axis_tdata <= s_axis_tdata;
\n m_axis_tlast <= s_axis_tlast;
\n end else begin
\n m_axis_tvalid <= 1'b0;
\n end
\n end
\nend
\nendmodule<\/p>\n
AXI\u603b\u7ebf\u662fFPGA\u5f00\u53d1\u7684\u300c\u5fc5\u4fee\u8bfe\u300d，\u4e5f\u662fFPGA\u4ece\u5165\u95e8\u5230\u8fdb\u9636\u7684\u6838\u5fc3\u5206\u6c34\u5cad，\u638c\u63e1AXI\u603b\u7ebf\u540e，\u5c31\u80fd\u8f7b\u677e\u9a7e\u9a6dFPGA\u7684\u9ad8\u901f\u6570\u636e\u4ea4\u4e92\u3001DDR\u8bfb\u5199\u3001DMA\u4f20\u8f93\u7b49\u6838\u5fc3\u573a\u666f，\u4e5f\u662f\u505a\u5f02\u6784\u8ba1\u7b97（FPGA+ARM）\u7684\u5fc5\u5907\u6280\u80fd\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"
AXI\u603b\u7ebf\u7cfb\u7edf\u5b66\u4e60，\u8fd9\u4e2a\u603b\u7ebf\u662f\u975e\u5e38\u91cd\u8981，\u5f88\u591a\u5730\u65b9\u90fd\u4f1a\u8981\u7528，\u7528\u5230\u7684\u8bdd\u4e00\u5b9a\u8981\u597d\u597d\u5b66\u4e60
\n\u767e\u5ea6\u7f51\u76d8\u94fe\u63a5：https:\/\/pan.baidu.com\/s\/1rDsLAXGj8WbX82teSkhuIw?pwd1234 \u63d0\u53d6\u7801: 1234
\n\u5305\u542bFPGA\u7cfb\u7edf\u5b66\u4e60\u8d44\u6599，\u514d\u8d39\u5206\u4eab
\n\u4e00\u3001AXI\u603b\u7ebf \u8be6\u7ec6\u5b8c\u6574\u4ecb\u7ecd（AMBA AXI）
\n1.1 AXI\u603b\u7ebf\u7684\u57fa\u7840\u5b9a\u4f4d
\nAXI（Advanced<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[6498,6500,6499,1740,941,371],"topic":[],"class_list":["post-61474","post","type-post","status-publish","format-standard","hentry","category-server","tag-ic","tag-verilog","tag-6499","tag-fpga","tag-371"],"yoast_head":"\n