{"id":55190,"date":"2025-08-13T18:54:47","date_gmt":"2025-08-13T10:54:47","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/55190.html"},"modified":"2025-08-13T18:54:47","modified_gmt":"2025-08-13T10:54:47","slug":"%e3%80%90freertos%e3%80%91%e5%88%a8%e6%a0%b9%e9%97%ae%e5%ba%951%ef%bc%9a-systick%e5%9c%a8freertos%e4%b8%8a%e5%92%8b%e5%b7%a5%e4%bd%9c%e7%9a%84","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/55190.html","title":{"rendered":"\u3010FreeRTOS\u3011\u5228\u6839\u95ee\u5e951\uff1a SysTick\u5728FreeRTOS\u4e0a\u548b\u5de5\u4f5c\u7684"},"content":{"rendered":"

\u00a0 \u00a0 \u6709\u4e9b\u4e8b\u5427，\u4f60\u4e0d\u53bb\u6df1\u7a76，\u8fd8\u771f\u662f\u95f9\u5fc3！\u641e\u660e\u767d\u4e86，\u5403\u5230\u5634\u4e86，\u4e5f\u5c31\u6ca1\u6709\u9057\u61be\u4e86\u3002\u4f60\u8bf4\u522b\u4eba\u642d\u5efa\u79fb\u690d\u597d\u7684\u4e1c\u897f，\u4f60\u518d\u53bb\u7814\u7a76\u8fd8\u6709\u4ec0\u4e48\u610f\u4e49\u5462？\u9519！\u5403\u900f\u9ad8\u624b\u7684\u4ee3\u7801，\u5c31\u7b49\u4e8e\u6c72\u53d6\u4e86\u9ad8\u7ea7\u6280\u80fd\u7684\u8425\u517b！\u8bdd\u4e0d\u591a\u8bf4，\u5f00\u641e…<\/p>\n

\u00a0 \u00a0\u00a0<\/p>\n

\u4e00\u3001SysTick\u4ec0\u4e48\u73a9\u610f？<\/p>\n

\u00a0 \u00a0 \u5b83\u662fARM\u8bbe\u8ba1CPU\u67b6\u6784\u65f6\u5c31\u5e26\u7684\u4e00\u4e2a\u5b9a\u65f6\u5668，\u5b83\u53ef\u4e0d\u662f\u82af\u7247\u8bbe\u8ba1\u516c\u53f8\u7ed9\u7684TIMx\u554a，\u5b83\u5728CPU\u4e0a\u96c6\u6210\u7684\u8bbe\u5907，\u4e0d\u662f\u7247\u4e0a\u5916\u8bbe！<\/p>\n

\u00a0 \u00a0 \u300aCortex-M4 Devices Generic User Guide\u300b 4.4\u8282\u4e2d\u5c31\u6709\u63cf\u8ff0：<\/p>\n

\"\"<\/p>\n<\/p>\n

\u00a0 \u00a0 SFR:\u63a7\u5236\u4e0e\u72b6\u6001\u57280xE000E010,\u91cd\u8f7d\u6570\u503c\u5bc4\u5b58\u5668\u57280xE000E014,\u5f53\u524d\u8ba1\u6570\u503c\u5bc4\u5b58\u56680xE000E018,\u8fd8\u6709\u4e00\u4e2a\u4fee\u6b63\u5bc4\u5b58\u56680xE000E01C\u3002\u5b83\u4eec\u600e\u4e48\u914d\u7f6e\u7684\u6211\u4eec\u6682\u4e14\u4e0d\u63d0，\u6211\u4eec\u53ea\u8bf4\u5b83\u4eec\u5728\u7cfb\u7edf\u4e2d\u600e\u4e48\u7528\u7684！<\/p>\n<\/p>\n

\u4e8c\u3001SysTick\u7684\u5b9a\u4e49\u4e0e\u4f7f\u7528<\/p>\n

\u00a0 \u00a0 1\u3001SysTick\u5bc4\u5b58\u5668\u7ec4\u7ed3\u6784\u4f53\u58f0\u660e：Core\/CMSIS\/Core\/Include\/core_cm4.h<\/p>\n

typedef struct
\n{
\n __IOM uint32_t CTRL; \/*!< Offset: 0x000 (R\/W) SysTick Control and Status Register *\/
\n __IOM uint32_t LOAD; \/*!< Offset: 0x004 (R\/W) SysTick Reload Value Register *\/
\n __IOM uint32_t VAL; \/*!< Offset: 0x008 (R\/W) SysTick Current Value Register *\/
\n __IM uint32_t CALIB; \/*!< Offset: 0x00C (R\/ ) SysTick Calibration Register *\/
\n} SysTick_Type;<\/p>\n

\u00a0 \u00a0 \u770b，\u7ed3\u6784\u4f53\u4e2d\u5b9a\u4e49\u7684\u662fuint32_t，\u6b63\u597d4\u4e2a\u5b57\u8282\u7684offset，\u4e0eSFR\u5728\u5730\u5740\u603b\u7ebf\u4e0a\u7684\u5730\u5740\u5206\u5e03\u6b63\u597d\u5339\u914d！<\/p>\n

\u00a0 \u00a0__IOM&__IM\u53c8\u662f\u4ec0\u4e48？Core\/CMSIS\/Core\/Include\/core_cm4.h<\/p>\n

\/* following defines should be used for structure members *\/
\n#define __IM volatile const \/*! Defines 'read only' structure member permissions *\/
\n#define __OM volatile \/*! Defines 'write only' structure member permissions *\/
\n#define __IOM volatile \/*! Defines 'read \/ write' structure member permissions *\/<\/p>\n

\u00a0 \u58f0\u660e\u7684\u662f\u6613\u53d8\u91cf\u5e38\u91cf\u4e0e\u6613\u53d8\u91cf\u3010\u76f8\u5173\u4ee3\u7801\u4e0d\u8981\u88ab\u4f18\u5316\u6389\u554a~~~\u3011<\/p>\n

\u00a0 \u00a0 2\u3001SFR\u7ed3\u6784\u4f53\u6307\u5411\u7269\u7406\u5730\u5740\u57fa\u5730\u5740：Core\/CMSIS\/Core\/Include\/core_cm4.h<\/p>\n

#define SysTick ((SysTick_Type *) SysTick_BASE ) \/*!< SysTick configuration struct *\/<\/p>\n

SysTick_BASE\u53c8\u662f\u4ec0\u4e48？<\/p>\n

…
\n#define SCS_BASE (0xE000E000UL) \/*!< System Control Space Base Address *\/
\n…<\/p>\n

#define SysTick_BASE (SCS_BASE + 0x0010UL) \/*!< SysTick Base Address *\/
\n…<\/p>\n

\u00a0 \u00a0 \u662f\u4e0d\u662f\u660e\u6717\u4e86？<\/p>\n

\u00a0 \u00a0 3\u3001SysTick\u7684\u521d\u59cb\u5316：Core\/CMSIS\/Core\/Include\/core_cm4.h<\/p>\n

__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\n{
\n if ((ticks – 1UL) > SysTick_LOAD_RELOAD_Msk)
\n {
\n return (1UL); \/* Reload value impossible *\/
\n }<\/p>\n

SysTick->LOAD = (uint32_t)(ticks – 1UL); \/* set reload register *\/
\n NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) – 1UL); \/* set Priority for Systick Interrupt *\/
\n SysTick->VAL = 0UL; \/* Load the SysTick Counter Value *\/
\n SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\n SysTick_CTRL_TICKINT_Msk |
\n SysTick_CTRL_ENABLE_Msk; \/* Enable SysTick IRQ and SysTick Timer *\/
\n return (0UL); \/* Function successful *\/
\n}<\/p>\n

\u00a0 \u00a0 \u901a\u8fc7\u63a7\u5236\u5bc4\u5b58\u5668\u914d\u7f6eSysTick\u7684\u5de5\u4f5c\u6a21\u5f0f，\u901a\u8fc7\u8ba1\u6570\u4e0e\u91cd\u8f7d\u7279\u6b8a\u529f\u80fd\u5bc4\u5b58\u5668\u914d\u7f6e\u521d\u59cb\u4e0e\u91cd\u8f7d\u503c！\u5f53\u7136\u8fd8\u6709NVIC\u7684\u4f18\u5148\u7ea7\u914d\u7f6e！<\/p>\n<\/p>\n

\u00a0 \u00a0\u00a0SysTick_CTRL_CLKSOURCE_Msk \u8fd9\u6837\u7684\u5b8f\u53c8\u662f\u5e72\u4ec0\u4e48\u7684？<\/p>\n

\/* SysTick Control \/ Status Register Definitions *\/
\n#define SysTick_CTRL_COUNTFLAG_Pos 16U \/*!< SysTick CTRL: COUNTFLAG Position *\/
\n#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) \/*!< SysTick CTRL: COUNTFLAG Mask *\/<\/p>\n

#define SysTick_CTRL_CLKSOURCE_Pos 2U \/*!< SysTick CTRL: CLKSOURCE Position *\/
\n#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) \/*!< SysTick CTRL: CLKSOURCE Mask *\/<\/p>\n

#define SysTick_CTRL_TICKINT_Pos 1U \/*!< SysTick CTRL: TICKINT Position *\/
\n#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) \/*!< SysTick CTRL: TICKINT Mask *\/<\/p>\n

#define SysTick_CTRL_ENABLE_Pos 0U \/*!< SysTick CTRL: ENABLE Position *\/
\n#define SysTick_CTRL_ENABLE_Msk (1UL \/*<< SysTick_CTRL_ENABLE_Pos*\/) \/*!< SysTick CTRL: ENABLE Mask *\/<\/p>\n

\u00a0 \u00a0 \u5c31\u662fCPU \u7528\u6237\u6307\u5bfc\u624b\u518c\u4e2d\u5bf9SFR\u4e2a\u63a7\u5236\u4f4d\u7ec4\u5408\u7684\u6570\u503c\u5b9a\u4e49\u62bd\u8c61！！！<\/p>\n

\u00a0 \u00a0 4\u3001SysTick\u4e0eFreeRTOS\u7684\u5bf9\u63a5：stm32f4xx_hal_cortex.c<\/p>\n

uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
\n{
\n return SysTick_Config(TicksNumb);
\n}<\/p>\n

\u00a0 \u00a0 \u548b\u6837，\u662f\u4e0d\u662f\u4ece\u786c\u4ef6\u5e95\u5c42\u88ab\u9010\u7ea7\u62bd\u8c61\u51fa\u6765\u4e86？<\/p>\n

\u00a0 \u00a0 5\u3001\u5e94\u7528\u53c8\u662f\u600e\u4e48\u521d\u59cb\u5316\u7684\u5462？main.c<\/p>\n

void SystemClock_Config(void)
\n{
\n …
\n HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() \/ 1000);
\n HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
\n…
\n}<\/p>\n

\u00a0 \u00a0 \u662f\u4e0d\u662f\u8c41\u7136\u5f00\u6717\u4e86\u5462？\u5199\u4e86\u8fd9\u4e48\u4e45\u7684SystemClock_Config，\u5230\u5e95\u90fd\u5e72\u4e86\u5565，\u8fd9\u56de\u5fc3\u91cc\u6e05\u695a\u4e86\u4e0d？<\/p>\n

\u4e09\u3001\u5f15\u7533<\/p>\n

\u00a0 \u00a0 STM32Cube\u5e93\u6574\u4f53\u7684\u5e95\u5c42\u5230HAL\u5c42\u7684\u62bd\u8c61\u8fc7\u7a0b，\u90fd\u7c7b\u4f3c\u4e8e\u4e0a\u8ff0\u7684\u8fc7\u7a0b，\u5b83\u5c01\u88c5\u4e86\u5e95\u5c42\u7684\u786c\u4ef6\u63a7\u5236\u3001\u72b6\u6001\u67e5\u8be2\u4e0e\u6570\u636e\u4ea4\u4e92\u7684\u7ec6\u8282\u8fc7\u7a0b，\u8ba9\u7528\u6237\u4e13\u6ce8\u4e8e\u9876\u5c42\u7684\u8bbe\u8ba1\u4e0e\u5b9e\u73b0！\u4f46，\u6709\u4e9b\u65f6\u5019，\u638c\u63e1\u597dHAL\u5c42\u4ee5\u4e0b\u7684\u8bbe\u8ba1\u5b9e\u73b0\u539f\u7406\u8ddf\u91cd\u8981！\u4f60\u7ec6\u54c1…<\/p>\n","protected":false},"excerpt":{"rendered":"

\u6587\u7ae0\u6d4f\u89c8\u9605\u8bfb281\u6b21\uff0c\u70b9\u8d5e7\u6b21\uff0c\u6536\u85cf7\u6b21\u3002\u6458\u8981\uff1a\u672c\u6587\u63a2\u8ba8\u4e86ARM Cortex-M\u7cfb\u5217\u4e2d\u7684SysTick\u5b9a\u65f6\u5668\uff0c\u5f3a\u8c03\u6df1\u5165\u7406\u89e3\u9ad8\u624b\u4ee3\u7801\u7684\u91cd\u8981\u6027\u3002SysTick\u662fCPU\u5185\u7f6e\u5b9a\u65f6\u5668\uff0c\u975e\u5916\u8bbe\uff0c\u5176\u5bc4\u5b58\u5668\u5730\u5740\u5728\u300aCortex-M4 Devices Generic User Guide\u300b\u4e2d\u6709\u8be6\u7ec6\u8bf4\u660e\u3002\u6587\u7ae0\u4eceSFR\u58f0\u660e\u3001\u914d\u7f6e\u3001\u521d\u59cb\u5316\u5230\u4e0eFreeRTOS\u5bf9\u63a5\u7b49\u65b9\u9762\u5206\u6790SysTick\u7684\u4f7f\u7528\uff0c\u5e2e\u52a9\u8bfb\u8005\u638c\u63e1\u8fd9\u4e00\u6838\u5fc3\u5b9a\u65f6\u5668\u7684\u5e94\u7528\u6280\u5de7\u3002\uff0899\u5b57\uff09<\/p>\n","protected":false},"author":2,"featured_media":55189,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[5078,5666,5668,217,5667],"topic":[],"class_list":{"0":"post-55190","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","6":"hentry","7":"category-server","8":"tag-freertos","10":"tag-hal","11":"tag-stm32","12":"tag-systick"},"yoast_head":"\n\u3010FreeRTOS\u3011\u5228\u6839\u95ee\u5e951\uff1a SysTick\u5728FreeRTOS\u4e0a\u548b\u5de5\u4f5c\u7684 - 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