![\"tlm-hier\"](\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/07\/20250730100141-6889ed856d19d.png\")
<\/p>\n\u6b64UVM TLM\u793a\u4f8b\u8fd0\u7528\u4e86\u524d\u6587\u8ba8\u8bba\u7684put\u7aef\u53e3\u3001TLM FIFO\u548cget\u7aef\u53e3，\u6784\u5efa\u4e86\u4e00\u4e2a\u5728\u4e0d\u540c\u5c42\u7ea7\u5305\u542bTLM\u7aef\u53e3\u7684\u6d4b\u8bd5\u5e73\u53f0\u3002<\/p>\n
<\/p>\n
TLM\u00a0 FIFO\u00a0\u53ef\u4ee5\u6269\u5c55\u4e3a\u5305\u542b\u53e6\u4e00\u4e2a\u540d\u4e3acomponentB\u7684\u7ec4\u4ef6，\u8be5\u7ec4\u4ef6\u4f7f\u7528\u53e6\u4e00\u4e2a\u5185\u90e8FIFO\u548c\u5b50\u7ec4\u4ef6\u6765\u63a5\u6536\u6570\u636e\u5305\u3002<\/p>\n
\u4e0b\u9762\u5b9a\u4e49\u4e86\u4e00\u4e2a\u540d\u4e3aPacket\u7684\u7c7b，\u4f5c\u4e3a\u5728\u4e0d\u540c\u7ec4\u4ef6\u4e4b\u95f4\u4f20\u8f93\u7684\u6570\u636e\u9879\u3002\u8be5\u7c7b\u7684\u5bf9\u8c61\u5c06\u5305\u542b\u4e24\u4e2a\u968f\u673a\u53d8\u91cf，\u8fd9\u4e9b\u53d8\u91cf\u5728\u53d1\u9001\u524d\u53ef\u4ee5\u88ab\u968f\u673a\u5316\u3002<\/p>\n
class Packet extends uvm_object;
\n rand bit[7:0] addr;
\n rand bit[7:0] data;<\/p>\n
`uvm_object_utils_begin(Packet)
\n `uvm_field_int(addr, UVM_ALL_ON)
\n `uvm_field_int(data, UVM_ALL_ON)
\n `uvm_object_utils_end<\/p>\n
function new(string name = "Packet");
\n super.new(name);
\n endfunction
\nendclass<\/p>\n
\u8be5\u7ec4\u4ef6\u4e0eUVM TLM FIFO\u793a\u4f8b\u4e2d\u7684\u5b8c\u5168\u76f8\u540c，\u5e76\u901a\u8fc7\u5176uvm_blocking_put_port\u5f00\u59cb\u53d1\u9001\u6570\u636e\u5305\u3002<\/p>\n<\/p>\n
class subComp1 extends uvm_component;
\n `uvm_component_utils (subComp1)<\/p>\n
\/\/ Create a blocking TLM put port which can send an object
\n \/\/ of type 'Packet'
\n uvm_blocking_put_port #(Packet) m_put_port;
\n int m_num_tx;<\/p>\n
function new (string name = "subComp1", uvm_component parent= null);
\n super.new (name, parent);
\n endfunction<\/p>\n
\/\/ Remember that TLM put_port is a class object and it will have to be
\n \/\/ created with new ()
\n virtual function void build_phase (uvm_phase phase);
\n super.build_phase (phase);
\n m_put_port = new ("m_put_port", this);
\n endfunction<\/p>\n
\/\/ Create a packet, randomize it and send it through the port
\n \/\/ Note that put() is a method defined by the receiving component
\n \/\/ Repeat these steps N times to send N packets
\n virtual task run_phase (uvm_phase phase);
\n repeat (m_num_tx) begin
\n Packet pkt = Packet::type_id::create ("pkt");
\n assert(pkt.randomize ());
\n #50;
\n \/\/ Print the packet to be displayed in log
\n `uvm_info ("SUBCOMP1", "Packet sent to compA:tlm_fifo", UVM_LOW)
\n pkt.print (uvm_default_line_printer);<\/p>\n
\/\/ Call the TLM put() method of put_port class and pass packet as argument
\n m_put_port.put (pkt);
\n end
\n endtask
\nendclass<\/p>\n
\u8be5\u5b50\u7ec4\u4ef6\u63a5\u6536\u6570\u636e\u5305\u7684\u901f\u5ea6\u6bd4\u4e0a\u6587\u63d0\u5230\u7684\u7ec4\u4ef6\u7a0d\u6162，\u5e76\u901a\u8fc7uvm_blocking_get_port\u63a5\u53e3\u63a5\u6536\u6570\u636e\u3002<\/p>\n
\u9700\u6ce8\u610f：\u8be5\u7ec4\u4ef6\u8fd8\u914d\u6709\u7c7b\u578b\u4e3auvm_blocking_put_port\u7684\u53e6\u4e00\u4e2a\u8f93\u51fa\u7aef\u53e3，\u7528\u4e8e\u4ececomponentA\u5411\u5916\u4f20\u8f93\u6570\u636e\u3002<\/p>\n
class subComp2 extends uvm_component;
\n `uvm_component_utils (subComp2)<\/p>\n
\/\/ Create a get_port to request for data from subComp1
\n uvm_blocking_get_port #(Packet) m_get_port;
\n uvm_blocking_put_port #(Packet) m_put_port;<\/p>\n
function new (string name, uvm_component parent);
\n super.new (name, parent);
\n endfunction<\/p>\n
virtual function void build_phase (uvm_phase phase);
\n super.build_phase (phase);
\n m_get_port = new ("m_get_port", this);
\n m_put_port = new ("m_put_port", this);
\n endfunction<\/p>\n
virtual task run_phase (uvm_phase phase);
\n Packet pkt;
\n forever begin
\n #100;
\n m_get_port.get (pkt);
\n `uvm_info ("SUBCOMP2", "Packet received from compA:tlm_fifo, forward it", UVM_LOW)
\n pkt.print (uvm_default_line_printer);
\n m_put_port.put(pkt);
\n end
\n endtask
\nendclass<\/p>\n
\u8be5\u5c42\u5305\u542b\u901a\u8fc7TLM FIFO\u8fde\u63a5\u7684\u4e24\u4e2a\u5b50\u7ec4\u4ef6，\u56e0\u4e3a\u5b83\u4eec\u7684\u4f20\u8f93\u901f\u7387\u4e0d\u540c\u3002<\/p>\n
\u8bf7\u6ce8\u610f，\u5b83\u8fd8\u5177\u6709\u53e6\u4e00\u4e2a\u7c7b\u578b\u4e3auvm_blocking_put_port\u7684put\u7aef\u53e3，\u7528\u4e8e\u8f6c\u53d1\u4ece\u8f83\u4f4e\u5c42subComp2\u63a5\u6536\u7684\u6570\u636e\u5305\u3002<\/p>\n
class componentA extends uvm_component;
\n `uvm_component_utils (componentA)
\n function new(string name="componentA", uvm_component parent=null);
\n super.new(name, parent);
\n endfunction<\/p>\n
subComp1 m_subcomp_1;
\n subComp2 m_subcomp_2;<\/p>\n
uvm_tlm_fifo #(Packet) m_tlm_fifo;
\n uvm_blocking_put_port #(Packet) m_put_port;
\n int m_num_tx;<\/p>\n
virtual function void build_phase (uvm_phase phase);
\n super.build_phase (phase);
\n \/\/ Create an object of both components
\n m_subcomp_1 = subComp1::type_id::create ("m_subcomp_1", this);
\n m_subcomp_2 = subComp2::type_id::create ("m_subcomp_2", this);<\/p>\n
\/\/ Create a FIFO with depth 2
\n m_tlm_fifo = new ("uvm_tlm_fifo", this, 2);
\n m_put_port = new ("m_put_port", this);
\n m_subcomp_1.m_num_tx = m_num_tx;
\n endfunction<\/p>\n
\/\/ Make componentA connections
\n virtual function void connect_phase (uvm_phase phase);
\n \/\/ Connect put port from subComp1 to TLM FIFO and then
\n \/\/ connect get_export of TLM FIFO with subComp2
\n m_subcomp_1.m_put_port.connect(m_tlm_fifo.put_export);
\n m_subcomp_2.m_get_port.connect(m_tlm_fifo.get_export);<\/p>\n
\/\/ Now connect subComp2 to componentA for forwarding pkt
\n m_subcomp_2.m_put_port.connect(this.m_put_port);
\n endfunction<\/p>\n
\/\/ Display a message when the FIFO is full
\n virtual task run_phase (uvm_phase phase);
\n forever begin
\n #10 if (m_tlm_fifo.is_full ())
\n `uvm_info ("COMPA", "componentA:TLM_Fifo is now FULL !", UVM_MEDIUM)
\n end
\n endtask
\nendclass<\/p>\n
\u5047\u8bbe\u76ee\u6807\u7ec4\u4ef6\u6bd4\u4e0a\u8ff0\u5176\u4ed6\u7ec4\u4ef6\u66f4\u6162，\u5e76\u4e14\u4f7f\u7528\u00a0uvm_blocking_get_port\u00a0\u6765\u63a5\u6536\u6570\u636e\u5305\u3002<\/p>\n<\/p>\n
\/\/ subComp3 accepts packet even slower than what componentA is sending out
\n\/\/ which is the reason we need a TLM FIFO in componentB
\nclass subComp3 extends uvm_component;
\n `uvm_component_utils (subComp3)<\/p>\n
\/\/ Create a get_port to request for data from subComp1
\n uvm_blocking_get_port #(Packet) m_get_port;
\n int m_num_tx;<\/p>\n
function new (string name, uvm_component parent);
\n super.new (name, parent);
\n endfunction<\/p>\n
virtual function void build_phase (uvm_phase phase);
\n super.build_phase (phase);
\n m_get_port = new ("m_get_port", this);
\n endfunction<\/p>\n
virtual task run_phase (uvm_phase phase);
\n Packet pkt;
\n repeat(m_num_tx) begin
\n #200;
\n m_get_port.get (pkt);
\n `uvm_info ("SUBCOMP3", "Packet received from componentA", UVM_LOW)
\n pkt.print (uvm_default_line_printer);
\n end
\n endtask
\nendclass<\/p>\n
\u7531\u4e8e\u76ee\u6807\u901f\u7387\u8f83\u6162，\u9700\u8981\u518d\u8fde\u63a5\u4e00\u4e2aUVM TLM FIFO\u5230subComp3，\u7528\u4e8e\u7f13\u51b2\u5176\u63a5\u6536\u7684\u6570\u636e\u5305\u3002\u8bf7\u6ce8\u610f，\u8be5FIFO\u5177\u6709\u4e00\u4e2a\u9876\u5c42put_export\u7aef\u53e3，\u7c7b\u578b\u4e3auvm_blocking_put_export\u3002<\/p>\n
class componentB extends uvm_component;
\n `uvm_component_utils (componentB)<\/p>\n
subComp3 m_subcomp_3;
\n uvm_tlm_fifo #(Packet) m_tlm_fifo;
\n uvm_blocking_put_export #(Packet) m_put_export;
\n int m_num_tx;<\/p>\n
function new (string name = "componentB", uvm_component parent = null);
\n super.new (name, parent);
\n endfunction<\/p>\n
virtual function void build_phase (uvm_phase phase);
\n super.build_phase (phase);
\n \/\/ Create an object of both components
\n m_subcomp_3 = subComp3::type_id::create ("m_subcomp_3", this);<\/p>\n
\/\/ Create a FIFO with depth 2
\n m_tlm_fifo = new ("tlm_fifo", this, 2);<\/p>\n
\/\/ Create the export to connect with componentA
\n m_put_export = new ("m_put_export", this);<\/p>\n
m_subcomp_3.m_num_tx = m_num_tx;
\n endfunction<\/p>\n
virtual function void connect_phase (uvm_phase phase);
\n \/\/ Connect from componentB export to FIFO export
\n m_put_export.connect (m_tlm_fifo.put_export);<\/p>\n
\/\/ Connect from FIFO export to subComponent3 port
\n m_subcomp_3.m_get_port.connect (m_tlm_fifo.get_export);
\n endfunction<\/p>\n
\/\/ Display a message when the FIFO is full
\n virtual task run_phase (uvm_phase phase);
\n forever begin
\n #10 if (m_tlm_fifo.is_full ())
\n `uvm_info ("COMPB", "componentB:TLM_Fifo is now FULL !", UVM_MEDIUM)
\n end
\n endtask
\nendclass<\/p>\n
\u7aef\u53e3\u4e0e\u5176\u5b9e\u73b0\u4e4b\u95f4\u7684\u8fde\u63a5\u5fc5\u987b\u5728\u66f4\u9ad8\u7684\u5c42\u6b21\u7ed3\u6784\u4e2d\u8fdb\u884c\u3002\u7531\u4e8e\u5728\u6b64\u793a\u4f8b\u4e2d\u4e24\u4e2a\u7ec4\u4ef6\u90fd\u76f4\u63a5\u5b9e\u4f8b\u5316\u4e8e\u6d4b\u8bd5\u7c7b\u5185，\u5b83\u4eec\u4e4b\u95f4\u7684\u8fde\u63a5\u53ef\u4ee5\u5728\u6d4b\u8bd5\u7684connect_phase\u9636\u6bb5\u5b8c\u6210\u3002\u5982\u679c\u8fd9\u4e24\u4e2a\u7ec4\u4ef6\u5b9e\u4f8b\u5316\u4e8e\u53e6\u4e00\u4e2a\u7ec4\u4ef6\u6216\u73af\u5883\u4e2d，\u5219\u5fc5\u987b\u5728\u8be5\u7ec4\u4ef6\u6216\u73af\u5883\u7684connect_phase\u9636\u6bb5\u8fdb\u884c\u8fde\u63a5\u3002<\/p>\n<\/p>\n
class my_test extends uvm_env;
\n `uvm_component_utils (my_test)<\/p>\n
componentA compA;
\n componentB compB;
\n int m_num_tx;<\/p>\n
function new (string name = "my_test", uvm_component parent = null);
\n super.new (name, parent);
\n endfunction<\/p>\n
virtual function void build_phase (uvm_phase phase);
\n super.build_phase (phase);
\n compA = componentA::type_id::create("componentA", this);
\n compB = componentB::type_id::create("componentB", this);<\/p>\n
std::randomize(m_num_tx) with { m_num_tx inside {[4:10]}; };
\n `uvm_info("TEST", $sformatf("Create %0d packets in total", m_num_tx), UVM_LOW)
\n compA.m_num_tx = m_num_tx;
\n compB.m_num_tx = m_num_tx;
\n endfunction<\/p>\n
\/\/ Connect the ports to the export of FIFO.
\n virtual function void connect_phase (uvm_phase phase);
\n compA.m_put_port.connect(compB.m_put_export);
\n endfunction<\/p>\n
virtual task run_phase(uvm_phase phase);
\n super.run_phase(phase);
\n \/\/ Let all components finish for purpose of illustration
\n phase.raise_objection(this);
\n #1000;
\n phase.drop_objection(this);
\n endtask
\nendclass<\/p>\n
\u00a0Simulation Log<\/p>\n
UVM_INFO @ 0: reporter [RNTST] Running test my_test…
\nUVM_INFO testbench.sv(220) @ 0: uvm_test_top [TEST] Create 4 packets in total
\nUVM_INFO testbench.sv(48) @ 50: uvm_test_top.componentA.m_subcomp_1 [SUBCOMP1] Packet sent to compA:tlm_fifo
\npkt: (Packet@2663) { addr: 'h1f data: 'h31 }
\nUVM_INFO testbench.sv(79) @ 100: uvm_test_top.componentA.m_subcomp_2 [SUBCOMP2] Packet received from compA:tlm_fifo, forward it
\npkt: (Packet@2663) { addr: 'h1f data: 'h31 }
\nUVM_INFO testbench.sv(48) @ 100: uvm_test_top.componentA.m_subcomp_1 [SUBCOMP1] Packet sent to compA:tlm_fifo
\npkt: (Packet@2685) { addr: 'hf4 data: 'h91 }
\nUVM_INFO testbench.sv(48) @ 150: uvm_test_top.componentA.m_subcomp_1 [SUBCOMP1] Packet sent to compA:tlm_fifo
\npkt: (Packet@2699) { addr: 'hab data: 'ha8 }
\nUVM_INFO testbench.sv(126) @ 150: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 160: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 170: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 180: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 190: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(154) @ 200: uvm_test_top.componentB.m_subcomp_3 [SUBCOMP3] Packet received from componentA
\npkt: (Packet@2663) { addr: 'h1f data: 'h31 }
\nUVM_INFO testbench.sv(79) @ 200: uvm_test_top.componentA.m_subcomp_2 [SUBCOMP2] Packet received from compA:tlm_fifo, forward it
\npkt: (Packet@2685) { addr: 'hf4 data: 'h91 }
\nUVM_INFO testbench.sv(48) @ 200: uvm_test_top.componentA.m_subcomp_1 [SUBCOMP1] Packet sent to compA:tlm_fifo
\npkt: (Packet@2681) { addr: 'h77 data: 'he7 }
\nUVM_INFO testbench.sv(126) @ 200: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 210: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 220: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 230: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 240: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 250: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 260: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 270: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 280: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(126) @ 290: uvm_test_top.componentA [COMPA] componentA:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(79) @ 300: uvm_test_top.componentA.m_subcomp_2 [SUBCOMP2] Packet received from compA:tlm_fifo, forward it
\npkt: (Packet@2699) { addr: 'hab data: 'ha8 }
\nUVM_INFO testbench.sv(198) @ 300: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 310: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 320: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 330: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 340: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 350: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 360: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 370: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 380: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 390: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(154) @ 400: uvm_test_top.componentB.m_subcomp_3 [SUBCOMP3] Packet received from componentA
\npkt: (Packet@2685) { addr: 'hf4 data: 'h91 }
\nUVM_INFO testbench.sv(79) @ 400: uvm_test_top.componentA.m_subcomp_2 [SUBCOMP2] Packet received from compA:tlm_fifo, forward it
\npkt: (Packet@2681) { addr: 'h77 data: 'he7 }
\nUVM_INFO testbench.sv(198) @ 400: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 410: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 420: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 430: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 440: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 450: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 460: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 470: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 480: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 490: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 500: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 510: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 520: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 530: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 540: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 550: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 560: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 570: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 580: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(198) @ 590: uvm_test_top.componentB [COMPB] componentB:TLM_Fifo is now FULL !
\nUVM_INFO testbench.sv(154) @ 600: uvm_test_top.componentB.m_subcomp_3 [SUBCOMP3] Packet received from componentA
\npkt: (Packet@2699) { addr: 'hab data: 'ha8 }
\nUVM_INFO testbench.sv(154) @ 800: uvm_test_top.componentB.m_subcomp_3 [SUBCOMP3] Packet received from componentA
\npkt: (Packet@2681) { addr: 'h77 data: 'he7 }
\nUVM_INFO \/playground_lib\/uvm-1.2\/src\/base\/uvm_objection.svh(1271) @ 1000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
\nUVM_INFO \/playground_lib\/uvm-1.2\/src\/base\/uvm_report_server.svh(847) @ 1000: reporter [UVM\/REPORT\/SERVER]
\n— UVM Report Summary —<\/p>\n","protected":false},"excerpt":{"rendered":"
\u6587\u7ae0\u6d4f\u89c8\u9605\u8bfb300\u6b21\u3002\u6b64UVM TLM\u793a\u4f8b\u8fd0\u7528\u4e86\u524d\u6587\u8ba8\u8bba\u7684put\u7aef\u53e3\u3001TLM FIFO\u548cget\u7aef\u53e3\uff0c\u6784\u5efa\u4e86\u4e00\u4e2a\u5728\u4e0d\u540c\u5c42\u7ea7\u5305\u542bTLM\u7aef\u53e3\u7684\u6d4b\u8bd5\u5e73\u53f0\u3002TLM FIFO \u53ef\u4ee5\u6269\u5c55\u4e3a\u5305\u542b\u53e6\u4e00\u4e2a\u540d\u4e3acomponentB\u7684\u7ec4\u4ef6\uff0c\u8be5\u7ec4\u4ef6\u4f7f\u7528\u53e6\u4e00\u4e2a\u5185\u90e8FIFO\u548c\u5b50\u7ec4\u4ef6\u6765\u63a5\u6536\u6570\u636e\u5305\u3002\u4e0b\u9762\u5b9a\u4e49\u4e86\u4e00\u4e2a\u540d\u4e3aPacket\u7684\u7c7b\uff0c\u4f5c\u4e3a\u5728\u4e0d\u540c\u7ec4\u4ef6\u4e4b\u95f4\u4f20\u8f93\u7684\u6570\u636e\u9879\u3002\u8be5\u7c7b\u7684\u5bf9\u8c61\u5c06\u5305\u542b\u4e24\u4e2a\u968f\u673a\u53d8\u91cf\uff0c\u8fd9\u4e9b\u53d8\u91cf\u5728\u53d1\u9001\u524d\u53ef\u4ee5\u88ab\u968f\u673a\u5316\u3002<\/p>\n","protected":false},"author":2,"featured_media":49362,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[4800],"topic":[],"class_list":["post-49363","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-server","tag-uvm"],"yoast_head":"\n