\u00a0 \u00a0 \u00a0 \u00a0 \u5728\u524d\u6587\u300aRISCV ISA -> TCG Ops\u300b\u4e2d，TCG IR \u64cd\u4f5c\u5bf9\u8c61\u662f Variables，\u5176\u4e2d Fixed Global Variable（TEMP_FIXED），\u4e0e Global Variable（TEMP_GLOBAL）\u6bd4\u8f83\u7279\u6b8a，\u662f\u7528\u4e8e\u6307\u4ee3 CPUState \u4ee5\u53ca \u7279\u5b9aCPU \u7684\u72b6\u6001\u7684\u3002\u672c\u6587\u5c31\u68b3\u7406\u6e05\u695a，\u5728 TCG IR \u4e2d，\u8fd9\u4e9b Variable \u5177\u4f53\u5b9a\u4e49\u53ca\u5176\u5b9e\u73b0\u65b9\u5f0f\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u9996\u5148，\u6574\u4e2a\u76ee\u6807CPU\u7684\u72b6\u6001\u5b58\u5728\u00a0\u00a0CPUState *cpu \u4e2d，\u4e5f\u5c31\u662f\u6267\u884c\u4e3b\u5faa\u73af\u4f20\u5165\u7684\u00a0cpu_exec_loop(CPUState *cpu, SyncClocks *sc)\u3002\u6700\u7ec8\u6eaf\u6e90\u5230\u5728\u521b\u5efa QEMU Machine \u7684\u65f6\u5019，\u521b\u5efa\u7684CPU，\u4e5f\u5c31\u662f RISCVCPU:CPUState:DeviceState\u3002\u5176\u5305\u542b\u4e86，CPURISCVState env，\u7ee7\u800c\u5305\u62ec\u4e86 RISCV CPU \u7684\u901a\u7528\u5bc4\u5b58\u5668（General Purpose Registers \/ GPRs）\u4ee5\u53ca\u72b6\u6001\u5bc4\u5b58\u5668（Control and Status Registers \/\u00a0CSRs）\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u90a3\u4e48，\u5728 TCG IR \u7684 Global Variables \u9700\u8981\u901a\u8fc7\u6307\u9488\u53bb\u6307\u5411 RISCV CPU \u7684 GPRs，\u800c CSRs\u7684\u8bfb\u5199\u5219\u901a\u8fc7 RISCV csr \u6307\u4ee4\u8fdb\u884c\u8bfb\u5199\u8bbf\u95ee，\u5728 TCG IR \u4e2d\u901a\u8fc7\u8c03\u7528 RISCV CPU \u4e2d\u5b9a\u4e49\u7684\u51fd\u6570\u6765\u5b9e\u73b0，\u8fd9\u4e2a\u5728\u540e\u7eed\u6587\u7ae0\u4f1a\u8fdb\u884c\u8be6\u7ec6\u8bb2\u89e3\u3002\u73b0\u5728，\u5c31\u53ea\u5173\u6ce8 GPR \u7b49\u5bc4\u5b58\u5668，\u80fd\u591f\u5728 TCG IR\u4e2d，\u76f4\u63a5\u901a\u8fc7 Global Variables \u6765\u8bbf\u95ee\u7684\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 Global Variables \u662f\u901a\u8fc7\u8bb0\u5f55\u4e86 RISCV CPU GPRs \u4e0e cpu_env \u7684\u504f\u79fb\u91cf（offset）\u6765\u8fdb\u884c\u5bfb\u5740\u7684\u3002\u56e0\u6b64，\u9996\u5148\u8981\u786e\u5b9a cpu_env \u662f\u600e\u4e48\u4ece\u00a0CPUState *cpu \u8fdb\u5165\u5230 TCG IR \u4e2d\u7684\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5728 TCG IR，cpu_env \u5373 \u4e0a\u8ff0\u7684\u00a0CPURISCVState env，\u7531\u00a0TCGv_env tcg_env \u6307\u4ee3，\u662f\u4e00\u4e2aC\u7684\u516c\u5171\u53d8\u91cf（Global Variable），\u5176\u5b9a\u4e49\u5982\u4e0b：<\/p>\n
TCGContext tcg_init_ctx;
\n__thread TCGContext *tcg_ctx;
\ntypedef TCGv_ptr TCGv_env;
\nTCGv_env tcg_env;<\/p>\n
static void tcg_context_init(unsigned max_threads){
\n TCGContext *s = &tcg_init_ctx;
\n TCGTemp *ts;
\n …
\n ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env");
\n tcg_env = temp_tcgv_ptr(ts);}
\nstatic TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
\n TCGReg reg, const char *name){
\n TCGTemp *ts;
\n tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
\n ts = tcg_global_alloc(s);
\n ts->base_type = type;
\n ts->type = type;
\n ts->kind = TEMP_FIXED;
\n ts->reg = reg;
\n ts->name = name;
\n tcg_regset_set_reg(s->reserved_regs, reg);
\n return ts;}
\nstatic TCGTemp *tcg_global_alloc(TCGContext *s){
\n TCGTemp *ts;
\n …
\n s->nb_globals++;
\n ts = tcg_temp_alloc(s);
\n ts->kind = TEMP_GLOBAL;
\n return ts;}
\nstatic inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t){
\n return (TCGv_ptr)temp_tcgv_i32(t);}
\nstatic inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) {
\n (void)temp_idx(t); \/* trigger embedded assert *\/
\n return (TCGv_i32)((void *)t – (void *)tcg_ctx);}
\nstatic inline size_t temp_idx(TCGTemp *ts){
\n return ts – tcg_ctx->temps;}<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5c31\u662f\u8bf4，tcg_env \u5e76\u4e0d\u662f\u76f4\u63a5\u6307\u5411\u63cf\u8ff0 cpu_env \u7684 TCGTemp，\u8bb0\u4e3a TCGTemp cpu_env，\u800c\u662f\u8bb0\u5f55\u4e86\u5176\u4e0e tcg_ctx \u7684\u504f\u79fb\u91cf\u3002\u800c\u00a0TCGTemp cpu_env \u63cf\u8ff0\u4e86\u00a0TCG_AREG0 \u5bc4\u5b58\u5668\u6307\u5411\u4e86 CPURISCVState env\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5728TCG \u7684 X86\u540e\u7aef\u4e2d，\u5b9a\u4e49\u4e86\u00a0TCG_AREG0 \u7531 EBP \u6765\u5b58\u653e，\u5373：<\/p>\n
\/\/ qemu\/tcg\/i386\/tcg-target.h
\ntypedef enum {
\n…
\n TCG_AREG0 = TCG_REG_EBP,
\n TCG_REG_CALL_STACK = TCG_REG_ESP
\n} TCGReg;<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5e76\u5728 X86 \u751f\u6210 TB \u4ee3\u7801\u65f6，\u5728 TB prologue \u4e2d，\u8bbe\u5b9a，\u5982\u4e0b：<\/p>\n
static int __attribute__((noinline))
\ncpu_exec_loop(CPUState *cpu, SyncClocks *sc){
\n …
\n cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit);
\n …}
\nstatic inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
\n vaddr pc, TranslationBlock **last_tb,
\n int *tb_exit){
\n …
\n tb = cpu_tb_exec(cpu, tb, tb_exit);
\n …}
\n\/* Execute a TB, and fix up the CPU state afterwards if necessary *\/
\n\/*
\n * Disable CFI checks.
\n * TCG creates binary blobs at runtime, with the transformed code.
\n * A TB is a blob of binary code, created at runtime and called with an
\n * indirect function call. Since such function did not exist at compile time,
\n * the CFI runtime has no way to verify its signature and would fail.
\n * TCG is not considered a security-sensitive part of QEMU so this does not
\n * affect the impact of CFI in environment with high security requirements
\n *\/
\nstatic inline TranslationBlock * QEMU_DISABLE_CFI
\ncpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) {
\n …
\n ret = tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr);
\n …}
\nvoid tcg_prologue_init(void) {
\n …
\n tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr);
\n …
\n \/* Generate the prologue. *\/
\n tcg_target_qemu_prologue(s);
\n …}
\n\/* Generate global QEMU prologue and epilogue code *\/
\nstatic void tcg_target_qemu_prologue(TCGContext *s) {
\n …
\n tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
\n tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
\n \/* jmp *tb. *\/
\n tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
\n …}<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5bf9\u5e94\u7684\u8f93\u51fa\u6709：<\/p>\n
PROLOGUE: [size=45]
\n…
\n\/\/ %rdi used to pass 1st argument to functions, store cpu_env(cpu)
\n\/\/ %rsi used to pass 2nd argument to functions, point to tb code buffer
\n0x7d0f441b300a: 48 8b ef movq %rdi, %rbp
\n0x7d0f441b300d: 48 81 c4 78 fb ff ff addq $-0x488, %rsp
\n0x7d0f441b3014: ff e6 jmpq *%rsi
\n…<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5176\u4e2d\u00a0tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr) \u5c31\u662f \u4f20\u5165\u4e86 cpu_env \u5230 %rbp \u4e86\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u90a3\u4e48，\u627e\u5230\u4e86 cpu_env \u540e，\u5176\u5b83 TCG IR \u76f4\u63a5\u4f7f\u7528\u7684\u5bc4\u5b58\u5668\u7684\u5b9a\u4e49\u5982\u4e0b：<\/p>\n
\/* global register indices *\/
\nstatic TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
\nstatic TCGv_i64 cpu_fpr[32]; \/* assume F and D extensions *\/
\nstatic TCGv load_res;
\nstatic TCGv load_val;
\n…
\nvoid riscv_translate_init(void){
\n int i;
\n \/*
\n * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
\n * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
\n * unless you specifically block reads\/writes to reg 0.
\n *\/
\n cpu_gpr[0] = NULL;
\n cpu_gprh[0] = NULL;
\n for (i = 1; i < 32; i++) {
\n cpu_gpr[i] = tcg_global_mem_new(tcg_env,
\n offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
\n cpu_gprh[i] = tcg_global_mem_new(tcg_env,
\n offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
\n }
\n for (i = 0; i < 32; i++) {
\n cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
\n offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
\n }
\n cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
\n cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
\n cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart),
\n "vstart");
\n load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
\n "load_res");
\n load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
\n "load_val");}<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0\u90fd\u662f\u901a\u8fc7\u00a0tcg_global_mem_new() \u51fd\u6570\u6765\u5b9a\u4e49\u3002\u4ee5\u00a0static TCGv cpu_pc \u4e3a\u4f8b，\u6709：<\/p>\n
__thread TCGContext *tcg_ctx;
\ntypedef struct TCGv_i64_d *TCGv_i64;
\ntypedef TCGv_i64 TCGv;
\nstatic TCGv cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
\nTCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name){
\n TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_I64);
\n return temp_tcgv_i64(ts);}
\nstatic TCGTemp *tcg_global_mem_new_internal(TCGv_ptr base, intptr_t offset,
\n const char *name, TCGType type) {
\n TCGContext *s = tcg_ctx;
\n \/\/ In this case, base_ts == TCGTemp* cpu_env.
\n TCGTemp *base_ts = tcgv_ptr_temp(base);
\n TCGTemp *ts = tcg_global_alloc(s);
\n int indirect_reg = 0;
\n switch (base_ts->kind) {
\n case TEMP_FIXED:
\n break;
\n …}
\n if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
\n …
\n } else {
\n ts->base_type = type;
\n ts->type = type;
\n ts->indirect_reg = indirect_reg;
\n ts->mem_allocated = 1;
\n ts->mem_base = base_ts;
\n ts->mem_offset = offset;
\n ts->name = name;
\n }
\n return ts;
\n}
\nstatic inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v){
\n return tcgv_i32_temp((TCGv_i32)v);}
\nstatic inline TCGv_i64 temp_tcgv_i64(TCGTemp *t){
\n return (TCGv_i64)temp_tcgv_i32(t);}
\n\/*
\n * Using the offset of a temporary, relative to TCGContext, rather than
\n * its index means that we don't use 0. That leaves offset 0 free for
\n * a NULL representation without having to leave index 0 unused.
\n *\/
\nstatic inline TCGTemp *tcgv_i32_temp(TCGv_i32 v){
\n return (void *)tcg_ctx + (uintptr_t)v;}
\nstatic inline TCGv_i32 temp_tcgv_i32(TCGTemp *t){
\n (void)temp_idx(t); \/* trigger embedded assert *\/
\n return (TCGv_i32)((void *)t – (void *)tcg_ctx);}<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u90a3\u4e48，\u8fd9\u91cc\u7684 static TCGv cpu_pc \u8bb0\u5f55\u4e86 TCGTemp* cpu_pc \u4e0e\u00a0__thread TCGContext *tcg_ctx \u7684\u504f\u79fb\u91cf（offset）\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u4e5f\u5c31\u662f TCGv_* \u4e0e TCGTemp* \u7684\u8f6c\u6362\u9700\u8981\u7ecf\u8fc7 \u5176\u4e0etcg_ctx\u7684\u504f\u79fb\u91cf，\u800c TCGv_* \u5c31\u662f\u8bb0\u5f55\u4e86\u5bf9\u5e94\u7684\u504f\u79fb\u91cf，\u800c\u975e TCGTemp* \u6307\u9488\u3002\u800c\u5bf9\u5e94\u7684\u00a0TCGTemp* cpu_pc \u5219\u8bb0\u5f55\u4e86 pc \u5bc4\u5b58\u5668\u4e0e cpu_env \u7684\u504f\u79fb\u91cf\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u90a3\u4e48，\u56de\u987e\u524d\u6587\u7684 auipc t0,0 \u7684\u8f6c\u8bd1，\u6709<\/p>\n
static bool trans_auipc(DisasContext *ctx, arg_auipc *a){
\n \/\/ target_pc <- a->rd
\n TCGv target_pc = dest_gpr(ctx, a->rd);
\n \/\/ target_pc <- pc + a->imm
\n gen_pc_plus_diff(target_pc, ctx, a->imm);
\n \/\/ a->rd <- targe_pc
\n gen_set_gpr(ctx, a->rd, target_pc);
\n return true;}
\nstatic TCGv dest_gpr(DisasContext *ctx, int reg_num){
\n if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
\n return tcg_temp_new();
\n }
\n return cpu_gpr[reg_num];}
\nstatic void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
\n target_long diff){
\n target_ulong dest = ctx->base.pc_next + diff;
\n…
\n if (tb_cflags(ctx->base.tb) & CF_PCREL) {
\n tcg_gen_addi_tl(target, cpu_pc, dest – ctx->pc_save);
\n …} else {…}}
\nvoid tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2){
\n \/* some cases can be optimized here *\/
\n if (arg2 == 0) {
\n tcg_gen_mov_i64(ret, arg1);
\n } else if (TCG_TARGET_REG_BITS == 64) {
\n tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2));
\n } else {
\n tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
\n TCGV_LOW(arg1), TCGV_HIGH(arg1),
\n tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32));}}
\nvoid tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg){
\n if (ret == arg) {return;}
\n if (TCG_TARGET_REG_BITS == 64) {
\n tcg_gen_op2_i64(INDEX_op_mov, ret, arg);
\n } else {…}}
\nstatic void DNI tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2){
\n tcg_gen_op2(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2));}
\nTCGOp * NI tcg_gen_op2(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2){
\n TCGOp *op = tcg_emit_op(opc, 2);
\n TCGOP_TYPE(op) = type;
\n op->args[0] = a1;
\n op->args[1] = a2;
\n return op;}
\nTCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs){
\n TCGOp *op = tcg_op_alloc(opc, nargs);
\n if (tcg_ctx->emit_before_op) {
\n QTAILQ_INSERT_BEFORE(tcg_ctx->emit_before_op, op, link);
\n } else {
\n QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link);
\n }
\n return op;}
\nstatic void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t){
\n if (reg_num != 0) {
\n switch (get_ol(ctx)) {
\n …
\n case MXL_RV64:
\n case MXL_RV128:
\n tcg_gen_mov_tl(cpu_gpr[reg_num], t);
\n break;
\n …}
\n …}}
\nstatic inline TCGArg tcgv_i64_arg(TCGv_i64 v){
\n return temp_arg(tcgv_i64_temp(v));}
\nstatic inline TCGArg temp_arg(TCGTemp *ts) {
\n return (uintptr_t)ts;}<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5728\u751f\u6210\u5bf9\u5e94\u7684 struct TCGOp\u00a0\u65f6，\u4f1a\u5c06 TCGv_* \u8f6c\u53d8\u4e3a TCGArg\u3002\u800c TCGArg \u5b9e\u9645\u4e0a\u5c31\u662f TCGTemp*\u3002\u56e0\u6b64，\u5728 TCGArg (struct TCGOp)::args \u5c31\u662f\u8bb0\u5f55\u4e86 TCGTemp*\u3002\u4e5f\u5c31\u662f，\u53ef\u4ee5\u76f4\u63a5\u901a\u8fc7\u00a0 TCGArg (struct TCGOp)::args[index] \u6765\u8bbf\u95ee TCG IR \u64cd\u4f5c\u7684\u64cd\u4f5c\u5bf9\u8c61（Operands），\u5982\u00a0TCGTemp* cpu_pc，TCGTemp* cpu_gpr_x5\/t0 \u7b49\u3002<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u5176\u4e2dTCG IR \u4e2d\u7684\u4e00\u4e2a\u64cd\u4f5c\u7531\u00a0struct TCGOp \u5b9a\u4e49，\u5982\u4e0b：<\/p>\n
\/\/ TCG IR Operations
\nstruct TCGOp {
\n TCGOpcode opc : 8;
\n unsigned nargs : 8;
\n \/* Parameters for this opcode. See below. *\/
\n unsigned param1 : 8;
\n unsigned param2 : 8;
\n \/* Lifetime data of the operands. *\/
\n TCGLifeData life;
\n \/* Next and previous opcodes. *\/
\n QTAILQ_ENTRY(TCGOp) link;
\n \/* Register preferences for the output(s). *\/
\n TCGRegSet output_pref[2];
\n \/* Arguments for the opcode. *\/
\n TCGArg args[];};<\/p>\n
typedef enum TCGOpcode {
\n#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
\n#include "tcg\/tcg-opc.h"
\n#undef DEF
\n NB_OPS,
\n} TCGOpcode;<\/p>\n
\/\/ qemu\/include\/tcg\/tcg-opc.h
\n…
\n\/*
\n * DEF(name, oargs, iargs, cargs, flags)
\n *\/
\n\/* predefined ops *\/
\nDEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
\nDEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
\n\/* variable number of parameters *\/
\nDEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
\nDEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
\nDEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT)
\nDEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
\nDEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT)
\n…<\/p>\n
\u00a0 \u00a0 \u00a0 \u00a0 \u7531\u6b64，\u53ef\u4ee5\u4e86\u89e3\u5230，\u5728 TCG IR \u4e2d，\u662f\u5982\u4f55\u5bf9 RISCV CPU \u7684\u5bc4\u5b58\u5668\u8fdb\u884c\u8bbf\u95ee\u3002\u5173\u952e\u70b9\u5728\u4e8e\u5bf9 struct ArchCPU* cpu，struct CPUArchState* env，TCGv_*，TCGTemp*，TCGArg \u7684\u7406\u89e3\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"
\u6587\u7ae0\u6d4f\u89c8\u9605\u8bfb43\u6b21\u3002\u5728 TCG IR \u4e2d\uff0c\u662f\u5982\u4f55\u5bf9 RISCV CPU \u7684\u5bc4\u5b58\u5668\u8fdb\u884c\u8bbf\u95ee\u3002\u5173\u952e\u70b9\u5728\u4e8e\u5bf9 struct ArchCPU* cpu\uff0cstruct CPUArchState* env\uff0cTCGv_*\uff0cTCGTemp*\uff0cTCGArg \u7684\u7406\u89e3\u3002<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[55,81,4780,97,190,1917],"topic":[],"class_list":["post-49232","post","type-post","status-publish","format-standard","hentry","category-server","tag-c","tag-python","tag-qemu","tag-97","tag-190","tag-1917"],"yoast_head":"\n