{"id":47321,"date":"2025-07-30T07:22:05","date_gmt":"2025-07-29T23:22:05","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/47321.html"},"modified":"2025-07-30T07:22:05","modified_gmt":"2025-07-29T23:22:05","slug":"stm32l4%e7%a7%bb%e6%a4%8d-rt-thread-pm%e7%bb%84%e4%bb%b6%e8%af%a6%e8%a7%a3","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/47321.html","title":{"rendered":"STM32L4\u79fb\u690d rt-thread PM\u7ec4\u4ef6\u8be6\u89e3"},"content":{"rendered":"

\u4e00\u3001STM32L4 \u7684\u4f4e\u529f\u8017\u6a21\u5f0f\u7b80\u4ecb<\/h2>\n

STM32L4 \u7cfb\u5217\u5fae\u63a7\u5236\u5668\u4e13\u4e3a\u4f4e\u529f\u8017\u5e94\u7528\u8bbe\u8ba1，\u63d0\u4f9b\u591a\u79cd\u4f4e\u529f\u8017\u6a21\u5f0f\u4ee5\u6ee1\u8db3\u4e0d\u540c\u5e94\u7528\u573a\u666f\u7684\u9700\u6c42\u3002\u4e3b\u8981\u6a21\u5f0f\u5305\u62ec\u8fd0\u884c\u6a21\u5f0f\u3001\u4f4e\u529f\u8017\u8fd0\u884c\u6a21\u5f0f\u3001\u7761\u7720\u6a21\u5f0f\u3001\u4f4e\u529f\u8017\u7761\u7720\u6a21\u5f0f\u3001\u505c\u6b62\u6a21\u5f0f\u3001\u4f4e\u529f\u8017\u505c\u6b62\u6a21\u5f0f\u548c\u5f85\u673a\u6a21\u5f0f\u3002<\/p>\n

\u8fd0\u884c\u6a21\u5f0f（Run Mode）<\/h3>\n

\u5728\u8fd0\u884c\u6a21\u5f0f\u4e0b，\u6240\u6709\u5916\u8bbe\u548c\u5185\u6838\u6b63\u5e38\u5de5\u4f5c，\u529f\u8017\u76f8\u5bf9\u8f83\u9ad8\u3002\u901a\u8fc7\u52a8\u6001\u7535\u538b\u8c03\u8282（DVC）\u548c\u9891\u7387\u8c03\u8282（\u5982 MSI\u3001HSI\u3001HSE）\u53ef\u4f18\u5316\u529f\u8017\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 100 \u00b5A\/MHz（CoreMark \u6d4b\u8bd5）\u3002<\/p>\n

\u4f4e\u529f\u8017\u8fd0\u884c\u6a21\u5f0f（Low Power Run Mode）<\/h3>\n

\u6b64\u6a21\u5f0f\u4e0b，CPU \u4ee5\u8f83\u4f4e\u9891\u7387\u8fd0\u884c（\u901a\u5e38\u4e3a 2 MHz），\u90e8\u5206\u5916\u8bbe\u5173\u95ed，\u7535\u538b\u8c03\u8282\u5668\u5904\u4e8e\u4f4e\u529f\u8017\u72b6\u6001\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 30 \u00b5A\/MHz，\u9002\u7528\u4e8e\u9700\u8981\u5b9e\u65f6\u54cd\u5e94\u4f46\u529f\u8017\u654f\u611f\u7684\u573a\u666f\u3002<\/p>\n

\u7761\u7720\u6a21\u5f0f（Sleep Mode）<\/h3>\n

CPU \u505c\u6b62\u8fd0\u884c，\u4f46\u5916\u8bbe\u548c\u65f6\u949f\u4fdd\u6301\u6d3b\u52a8\u72b6\u6001\u3002\u53ef\u901a\u8fc7\u4e2d\u65ad\u6216\u4e8b\u4ef6\u5524\u9192\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 10 \u00b5A\/MHz（\u5916\u8bbe\u6d3b\u52a8\u65f6）\u3002<\/p>\n

\u4f4e\u529f\u8017\u7761\u7720\u6a21\u5f0f（Low Power Sleep Mode）<\/h3>\n

\u4e0e\u7761\u7720\u6a21\u5f0f\u7c7b\u4f3c，\u4f46\u7535\u538b\u8c03\u8282\u5668\u5207\u6362\u5230\u4f4e\u529f\u8017\u72b6\u6001，\u8fdb\u4e00\u6b65\u964d\u4f4e\u529f\u8017\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 5 \u00b5A\/MHz\u3002<\/p>\n

\u505c\u6b62\u6a21\u5f0f（Stop Mode）<\/h3>\n

\u5185\u6838\u548c\u5927\u90e8\u5206\u5916\u8bbe\u65f6\u949f\u5173\u95ed，\u4ec5\u4fdd\u7559\u90e8\u5206\u5173\u952e\u5916\u8bbe（\u5982 RTC\u3001LCD）\u6d3b\u52a8\u3002\u5524\u9192\u65f6\u95f4\u8f83\u77ed（\u7ea6 5 \u00b5s）\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 1 \u00b5A（\u4fdd\u7559 SRAM）\u3002<\/p>\n

\u4f4e\u529f\u8017\u505c\u6b62\u6a21\u5f0f（Low Power Stop Mode）<\/h3>\n

\u7535\u538b\u8c03\u8282\u5668\u5173\u95ed，\u4ec5\u4fdd\u6301\u6781\u4f4e\u529f\u8017\u72b6\u6001\u3002SRAM \u5185\u5bb9\u53ef\u4fdd\u7559，\u5524\u9192\u65f6\u95f4\u7a0d\u957f（\u7ea6 10 \u00b5s）\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 0.5 \u00b5A\u3002<\/p>\n

\u5f85\u673a\u6a21\u5f0f（Standby Mode）<\/h3>\n

\u6700\u4f4e\u529f\u8017\u6a21\u5f0f，\u4ec5\u5907\u4efd\u57df（\u5982 RTC\u3001\u5907\u4efd\u5bc4\u5b58\u5668）\u4fdd\u6301\u4f9b\u7535\u3002SRAM \u548c\u5bc4\u5b58\u5668\u5185\u5bb9\u4e22\u5931，\u5524\u9192\u9700\u590d\u4f4d\u3002\u5178\u578b\u7535\u6d41\u6d88\u8017\u4e3a 0.1 \u00b5A（\u65e0 RTC）\u3002<\/p>\n

\u4e0b\u9762\u662f\u5404\u4e2a\u6a21\u5f0f\u4e4b\u95f4\u7684\u72b6\u6001\u8f6c\u6362\u56fe：
\n\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\"<\/p>\n

\u4e8c\u3001\u5f71\u54cd\u7cfb\u7edf\u529f\u8017\u7684\u56e0\u7d20<\/h2>\n

\u5c3d\u7ba1 STM32L476 \u7684\u4f4e\u529f\u8017\u6a21\u5f0f\u5f88\u591a，\u4f46\u672c\u8d28\u4e0a\u5e76\u4e0d\u590d\u6742，\u7406\u89e3\u5b83\u7684\u539f\u7406\u6709\u52a9\u4e8e\u6211\u4eec\u79fb\u690d\u9a71\u52a8，\u540c\u65f6\u66f4\u597d\u7684\u5728\u4ea7\u54c1\u4e2d\u9009\u62e9\u5408\u9002\u7684\u6a21\u5f0f\u3002
\n\u6700\u7ec8\u51b3\u5b9a STM32L476 \u7cfb\u7edf\u529f\u8017\u7684\u4e3b\u8981\u662f\u4e09\u4e2a\u56e0\u7d20：\u7a33\u538b\u5668（voltage regulator）\u3001CPU \u5de5\u4f5c\u9891\u7387\u3001\u82af\u7247\u81ea\u8eab\u4f4e\u529f\u8017\u7684\u5904\u7406，\u4e0b\u9762\u5206\u522b\u5bf9\u4e09\u4e2a\u56e0\u7d20\u8fdb\u884c\u9610\u8ff0\u3002<\/p>\n

1\u3001\u7a33\u538b\u5668<\/h3>\n

L4 \u4f7f\u7528\u4e24\u4e2a\u5d4c\u5165\u5f0f\u7ebf\u6027\u7a33\u538b\u5668\u4e3a\u6240\u6709\u6570\u5b57\u7535\u8def\u3001\u5f85\u673a\u7535\u8def\u4ee5\u53ca\u5907\u4efd\u65f6\u949f\u57df\u4f9b\u7535，\u5206\u522b\u662f\u4e3b\u7a33\u538b\u5668（main regulator，\u4e0b\u6587\u7b80\u79f0 MR）\u548c\u4f4e\u529f\u8017\u7a33\u538b\u5668（low-power regulator，\u4e0b\u6587\u7b80\u79f0 LPR）\u3002\u7a33\u538b\u5668\u5728\u590d\u4f4d\u540e\u5904\u4e8e\u4f7f\u80fd\u72b6\u6001，\u6839\u636e\u5e94\u7528\u6a21\u5f0f，\u9009\u62e9\u4e0d\u540c\u7684\u7a33\u538b\u5668\u5bf9 Vcore \u57df\u4f9b\u7535\u3002\u5176\u4e2d，MR \u7684\u8f93\u51fa\u7535\u538b\u53ef\u4ee5\u7531\u8f6f\u4ef6\u914d\u7f6e\u4e3a\u4e0d\u540c\u7684\u8303\u56f4（Range 1 \u548c Rnage 2）\u3002<\/p>\n\n\u7a33\u538b\u5668\u5e94\u7528\u573a\u5408<\/tr>\n\n\n\n\n\n
MR（Range 1<\/td>\nVcore = 1.2V，\u7528\u4e8e\u8fd0\u884c\u6a21\u5f0f\u3001\u7761\u7720\u6a21\u5f0f\u548c\u505c\u6b62\u6a21\u5f0f0，MR \u672a Vcore \u57df\u63d0\u4f9b\u5168\u529f\u7387<\/td>\n<\/tr>\n
MR（Range 2）<\/td>\nVcore = 1.0V，\u4f7f\u7528\u7684\u573a\u666f\u540c\u4e0a<\/td>\n<\/tr>\n
LPR<\/td>\n\u7528\u4e8e\u4f4e\u529f\u8017\u8fd0\u884c\u6a21\u5f0f\u3001\u4f4e\u529f\u8017\u4f11\u7720\u6a21\u5f0f\u3001\u505c\u6b62\u6a21\u5f0f 1\u3001\u505c\u6b62\u6a21\u5f0f2<\/td>\n<\/tr>\n
OFF<\/td>\nStandby \u548c Shutdown \u6a21\u5f0f\u4e0b，MR \u548c LPR \u90fd\u88ab\u5173\u95ed<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

2\u3001CPU \u5de5\u4f5c\u9891\u7387<\/h3>\n

\u901a\u8fc7\u964d\u4f4e CPU \u7684\u4e3b\u9891\u8fbe\u5230\u964d\u4f4e\u529f\u8017\u7684\u76ee\u7684： MR \u5de5\u4f5c\u5728 Range 1 \u6b63\u5e38\u6a21\u5f0f\u65f6，SYSCLK \u6700\u9ad8\u53ef\u4ee5\u5de5\u4f5c\u5728 80M； MR \u5de5\u4f5c\u5728 Range 2 \u65f6，SYSCLK \u6700\u9ad8\u4e0d\u80fd\u8d85\u8fc7 26 M； \u4f4e\u529f\u8017\u8fd0\u884c\u6a21\u5f0f\u548c\u4f4e\u529f\u8017\u4f11\u7720\u6a21\u5f0f，\u5373 Vcore \u57df\u7531 LPR \u4f9b\u7535，SYSCLK \u5fc5\u987b\u5c0f\u4e8e 2M\u3002<\/p>\n

3\u3001\u82af\u7247\u672c\u8eab\u7684\u4f4e\u529f\u8017\u5904\u7406<\/h3>\n

\u82af\u7247\u672c\u8eab\u5b9a\u4e49\u4e86\u4e00\u7cfb\u5217\u7684\u4f11\u7720\u6a21\u5f0f，\u5982 Sleeep\u3001Stop\u3001Standby \u548c Shutdown，\u524d\u9762\u7684\u56db\u79cd\u6a21\u5f0f\u529f\u8017\u9010\u6e10\u964d\u4f4e，\u5b9e\u8d28\u662f\u82af\u7247\u5185\u90e8\u901a\u8fc7\u5173\u95ed\u5916\u8bbe\u548c\u65f6\u949f\u6765\u5b9e\u73b0\u3002<\/p>\n

\u4e09\u3001\u79fb\u690d\u7684\u5177\u4f53\u5b9e\u73b0<\/h2>\n

\u00a0\u00a0\u00a0\u00a0\u4e0a\u6587\u7b80\u8981\u8bf4\u660e STM32 \u7684\u4f4e\u529f\u8017\u6a21\u5f0f\u548c\u5de5\u4f5c\u539f\u7406，\u4e0b\u9762\u4ecb\u7ecd RT-Thread PM \u7684\u529f\u80fd\u548c\u79fb\u690d\u63a5\u53e3\u3002
\n\u00a0\u00a0\u00a0\u00a0RT-Thread \u4f4e\u529f\u8017\u7ba1\u7406\u7cfb\u7edf\u4ece\u8bbe\u8ba1\u4e0a\u5206\u79bb\u8fd0\u884c\u6a21\u5f0f\u548c\u4f11\u7720\u6a21\u5f0f，\u72ec\u7acb\u7ba1\u7406，\u8fd0\u884c\u6a21\u5f0f\u7528\u4e8e\u53d8\u9891\u548c\u53d8\u7535\u538b，\u4f11\u7720\u8c03\u7528\u82af\u7247\u7684\u4f11\u7720\u7279\u6027\u3002\u5bf9\u4e8e\u591a\u6570\u82af\u7247\u548c\u5f00\u53d1\u6765\u8bf4，\u53ef\u80fd\u5e76\u4e0d\u9700\u8981\u8003\u8651\u53d8\u9891\u548c\u53d8\u7535\u538b，\u4ec5\u9700\u5173\u6ce8\u4f11\u7720\u6a21\u5f0f\u3002
\n\u00a0\u00a0\u00a0\u00a0STM32 L4 \u7cfb\u5217\u7684\u82af\u7247\u6709\u8fd0\u884c\u6a21\u5f0f\u548c\u4f4e\u529f\u8017\u8fd0\u884c\u6a21\u5f0f\u7684\u6982\u5ff5，\u540c\u65f6 MR \u8fd8\u6709 Range 2 \u6a21\u5f0f，\u53ef\u7528\u4e8e\u53d8\u9891\u573a\u666f\u3002
\n\u00a0\u00a0\u00a0\u00a0PM \u7ec4\u4ef6\u7684\u5e95\u5c42\u529f\u80fd\u90fd\u662f\u901a\u8fc7struct rt_pm_ops\u7ed3\u6784\u4f53\u91cc\u7684\u51fd\u6570\u5b8c\u6210：<\/p>\n

\/**
\n * low power mode operations
\n *\/<\/span>
\nstruct<\/span> rt_pm_ops<\/span>
\n{<\/span>
\n void<\/span> (<\/span>*<\/span>sleep)<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm,<\/span> uint8_t<\/span> mode)<\/span>;<\/span>
\n void<\/span> (<\/span>*<\/span>run)<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm,<\/span> uint8_t<\/span> mode)<\/span>;<\/span>
\n void<\/span> (<\/span>*<\/span>timer_start)<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm,<\/span> rt_uint32_t<\/span> timeout)<\/span>;<\/span>
\n void<\/span> (<\/span>*<\/span>timer_stop)<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm)<\/span>;<\/span>
\n rt_tick_t<\/span> (<\/span>*<\/span>timer_get_tick)<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm)<\/span>;<\/span>
\n}<\/span>;<\/span><\/p>\n

1\u3001\u914d\u7f6e\u5de5\u7a0b<\/h3>\n

\u5f00\u542f Env \u5de5\u5177，\u8fdb\u5165\u6f58\u591a\u62c9\u5f00\u53d1\u677f\u7684 BSP \u76ee\u5f55（rt-thread\\\\bsp\\\\stm32\\\\stm32l475-atk-pandora），\u5728 Env \u547d\u4ee4\u884c\u91cc\u8f93\u5165 menuconfig \u8fdb\u5165\u914d\u7f6e\u754c\u9762\u914d\u7f6e\u5de5\u7a0b\u3002
\n\u914d\u7f6e PM \u7ec4\u4ef6：\u52fe\u9009 BSP \u91cc\u9762\u7684RT-Thread Components \u2014> Device Drivers \u2014> [*] Using Power Management device drivers：<\/p>\n

\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\"\u914d\u7f6e\u5185\u6838\u9009\u9879：\u4f7f\u7528 PM \u7ec4\u4ef6\u9700\u8981\u66f4\u5927\u7684 IDLE \u7ebf\u7a0b\u7684\u6808，\u8fd9\u91cc\u4f7f\u7528\u4e861024 \u5b57\u8282\u3002\u4f8b\u7a0b\u91cc\u8fd8\u4f7f\u7528 Software timer，\u6240\u4ee5\u6211\u4eec\u8fd8\u9700\u8981\u5f00\u542f\u76f8\u5e94\u7684\u914d\u7f6e
\n\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\"
\n\u914d\u7f6e\u5b8c\u6210，\u4fdd\u5b58\u5e76\u9000\u51fa\u914d\u7f6e\u9009\u9879，\u8f93\u5165\u547d\u4ee4scons –target=mdk5\u751f\u6210 mdk5 \u5de5\u7a0b；<\/p>\n

2\u3001\u79fb\u690d\u4f11\u7720\u6a21\u5f0f<\/h3>\n

\u79fb\u690d\u4f11\u7720\u6a21\u5f0f\u4ec5\u9700\u5173\u6ce8 sleep \u63a5\u53e3，\u6839\u636e PM \u7528\u6237\u624b\u518c\u76f8\u5173\u4ecb\u7ecd，\u9996\u5148\u5c06 RT-Thread \u7684\u4f11\u7720\u6a21\u5f0f\u548c STM32 \u7684\u6a21\u5f0f\u4f5c\u4e00\u4e2a\u8f6c\u6362：<\/p>\n\nRT-ThreadSTM32\u63cf\u8ff0<\/tr>\n\n\n\n\n\n\n\n
PM_SLEEP_MODE_NONE<\/td>\nRun<\/td>\n\u6b63\u5e38\u8fd0\u884c\u6a21\u5f0f，\u4e0d\u8fdb\u884c\u4efb\u4f55\u964d\u529f\u8017\u7684\u63aa\u65bd<\/td>\n<\/tr>\n
PM_SLEEP_MODE_IDLE<\/td>\nRun<\/td>\n\u6b63\u5e38\u8fd0\u884c\u6a21\u5f0f，\u53ef\u9009\u62e9 WFI(\u7b49\u5f85\u4e2d\u65ad\u5524\u9192)\u548cWFE(\u7b49\u5f85\u4e8b\u4ef6\u5524\u9192)，\u6b64\u5904\u6682\u4e0d\u5904\u7406<\/td>\n<\/tr>\n
PM_SLEEP_MODE_LIGHT<\/td>\nSleep<\/td>\n\u8f7b\u5ea6\u7761\u7720\u6a21\u5f0f，\u6267\u884c ST \u7684 Sleep \u6a21\u5f0f<\/td>\n<\/tr>\n
PM_SLEEP_MODE_DEEP<\/td>\nStop2<\/td>\n\u6df1\u5ea6\u7761\u7720\u6a21\u5f0f，\u6267\u884c ST \u7684 Stop2 \u6a21\u5f0f<\/td>\n<\/tr>\n
PM_SLEEP_MODE_STANDBY<\/td>\nStandby<\/td>\n\u5f85\u673a\u6a21\u5f0f，\u6267\u884c ST \u7684 Standby \u6a21\u5f0f<\/td>\n<\/tr>\n
PM_SLEEP_MODE_SHUTDOWN<\/td>\nShutdown<\/td>\n\u505c\u6b62\u6a21\u5f0f，\u6267\u884c ST \u7684 Shtudown \u6a21\u5f0f<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u4e0b\u9762\u662f\u5177\u4f53\u5b9e\u73b0：<\/p>\n

#<\/span>include<\/span> <board.h><\/span><\/span>
\n#<\/span>include<\/span> <rtthread.h><\/span><\/span>
\n#<\/span>include<\/span> <rtdevice.h><\/span><\/span><\/p>\n

static<\/span> void<\/span> sleep<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm,<\/span> uint8_t<\/span> mode)<\/span>
\n{<\/span>
\n switch<\/span> (<\/span>mode)<\/span>
\n {<\/span>
\n case<\/span> PM_SLEEP_MODE_NONE:<\/span>
\n break<\/span>;<\/span><\/p>\n

case<\/span> PM_SLEEP_MODE_IDLE:<\/span>
\n \/\/ __WFI();<\/span>
\n break<\/span>;<\/span><\/p>\n

case<\/span> PM_SLEEP_MODE_LIGHT:<\/span>
\n \/* Enter SLEEP Mode, Main regulator is ON *\/<\/span>
\n HAL_PWR_EnterSLEEPMode<\/span>(<\/span>PWR_MAINREGULATOR_ON,<\/span> PWR_SLEEPENTRY_WFI)<\/span>;<\/span>
\n break<\/span>;<\/span><\/p>\n

case<\/span> PM_SLEEP_MODE_DEEP:<\/span>
\n \/* Enter STOP 2 mode *\/<\/span>
\n HAL_PWREx_EnterSTOP2Mode<\/span>(<\/span>PWR_STOPENTRY_WFI)<\/span>;<\/span>
\n break<\/span>;<\/span><\/p>\n

case<\/span> PM_SLEEP_MODE_STANDBY:<\/span>
\n \/* Enter STANDBY mode *\/<\/span>
\n HAL_PWR_EnterSTANDBYMode<\/span>(<\/span>)<\/span>;<\/span>
\n break<\/span>;<\/span><\/p>\n

case<\/span> PM_SLEEP_MODE_SHUTDOWN:<\/span>
\n \/* Enter SHUTDOWNN mode *\/<\/span>
\n HAL_PWREx_EnterSHUTDOWNMode<\/span>(<\/span>)<\/span>;<\/span>
\n break<\/span>;<\/span><\/p>\n

default<\/span>:<\/span>
\n RT_ASSERT<\/span>(<\/span>0<\/span>)<\/span>;<\/span>
\n break<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

int<\/span> rt_hw_pm_init<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n static<\/span> const<\/span> struct<\/span> rt_pm_ops<\/span> _ops =<\/span>
\n {<\/span>
\n sleep,<\/span>
\n RT_NULL,<\/span>
\n RT_NULL,<\/span>
\n RT_NULL,<\/span>
\n RT_NULL
\n }<\/span>;<\/span><\/p>\n

rt_uint8_t<\/span> timer_mask =<\/span> 0<\/span>;<\/span><\/p>\n

\/* Enable Power Clock *\/<\/span>
\n __HAL_RCC_PWR_CLK_ENABLE<\/span>(<\/span>)<\/span>;<\/span><\/p>\n

\/* initialize system pm module *\/<\/span>
\n rt_system_pm_init<\/span>(<\/span>&<\/span>_ops,<\/span> timer_mask,<\/span> RT_NULL)<\/span>;<\/span><\/p>\n

return<\/span> 0<\/span>;<\/span>
\n}<\/span><\/p>\n

INIT_BOARD_EXPORT<\/span>(<\/span>rt_hw_pm_init)<\/span>;<\/span><\/p>\n

\u76ee\u524d\u4e3a\u6b62，ST \u7684\u4f11\u7720\u6a21\u5f0f\u5df2\u7ecf\u521d\u6b65\u52a0\u5165\u4e86，\u80fd\u591f\u6ee1\u8db3\u90e8\u5206\u7684\u5e94\u7528\u573a\u666f\u3002\u6253\u5f00\u547d\u4ee4\u884c，\u8f93\u5165\u8bf7\u6c42\/\u91ca\u653e\u4f11\u7720\u6a21\u5f0f\u547d\u4ee4，\u53ef\u4ee5\u89c2\u5bdf\u5230\u529f\u8017\u663e\u8457\u964d\u4f4e\u3002<\/p>\n

3\u3001\u79fb\u690d\u65f6\u95f4\u8865\u507f\u63a5\u53e3<\/h3>\n

\u67d0\u4e9b\u60c5\u51b5\u4e0b，\u6211\u4eec\u53ef\u80fd\u9700\u8981\u7cfb\u7edf\u5728\u7a7a\u95f2\u65f6\u8fdb\u5165 Stop \u6a21\u5f0f，\u4ee5\u8fbe\u5230\u66f4\u4f4e\u7684\u5c06\u529f\u8017\u6548\u679c\u3002L476 Stop 2 \u6a21\u5f0f\u4e0b\u7684\u7535\u6d41\u53ef\u4ee5\u8fbe\u5230 1.6 uA \u5de6\u53f3，ST \u624b\u518c\u4e0a\u5bf9 Stop2 \u6a21\u5f0f\u7684\u63cf\u8ff0\u5982\u4e0b：<\/p>\n

Stop 2 \u6a21\u5f0f\u57fa\u4e8e Cortex-M4 \u6df1\u5ea6\u7761\u7720\u6a21\u5f0f\u4e0e\u5916\u8bbe\u65f6\u949f\u95e8\u63a7\u3002\u5728 Stop 2 \u6a21\u5f0f\u4e0b， Vcore \u57df\u4e2d\u7684\u6240\u6709\u65f6\u949f\u90fd\u4f1a\u505c\u6b62， PLL\u3001 MSI\u3001 HSI16 \u548c HSE \u632f\u8361\u5668\u4e5f\u88ab\u7981\u6b62\u3002\u4e00\u4e9b\u5e26\u6709\u5524\u9192\u529f\u80fd（I2C3 \u548c LPUART）\u7684\u5916\u8bbe\u53ef\u4ee5\u5f00\u542f HSI16 \u4ee5\u83b7\u53d6\u5e27，\u5982\u679c\u8be5\u5e27\u4e0d\u662f\u5524\u9192\u5e27，\u4e5f\u53ef\u4ee5\u5728\u63a5\u6536\u5230\u5e27\u540e\u5173\u95ed HSI16\u3002SRAM1\u3001 SRAM2\u3001 SRAM3 \u548c\u5bc4\u5b58\u5668\u5185\u5bb9\u5c06\u4fdd\u7559，\u6240\u6709 I\/O \u5f15\u811a\u7684\u72b6\u6001\u4e0e\u8fd0\u884c\u6a21\u5f0f\u4e0b\u76f8\u540c\u3002<\/p>\n

\u6839\u636e\u624b\u518c\u53ef\u77e5，Stop 2 \u6a21\u5f0f\u4f1a\u5173\u95ed\u7cfb\u7edf\u65f6\u949f，\u5f53\u524d\u7684 OS Tick \u57fa\u4e8e\u5185\u6838\u7684 Systick \u5b9a\u65f6\u5668\u3002\u90a3\u4e48\u5728\u7cfb\u7edf\u65f6\u949f\u505c\u6b62\u540e，OS Tick \u4e5f\u4f1a\u505c\u6b62，\u5bf9\u4e8e\u67d0\u4e9b\u4f9d\u8d56 OS Tick \u7684\u5e94\u7528，\u5728\u8fdb\u5165 Stop 2 \u6a21\u5f0f，\u53c8\u88ab\u4e2d\u65ad\u5524\u9192\u540e，\u5c31\u4f1a\u51fa\u73b0\u95ee\u9898，\u56e0\u6b64\u9700\u8981\u5728\u7cfb\u7edf\u5524\u9192\u540e，\u5bf9 OS Tick \u8fdb\u884c\u8865\u507f\u3002Stop 2 \u6a21\u5f0f\u4e0b，\u7edd\u5927\u591a\u6570\u5916\u8bbe\u90fd\u505c\u6b62\u5de5\u4f5c，\u4ec5\u4f4e\u529f\u8017\u5b9a\u65f6\u5668 1（LP_TIM1）\u9009\u62e9 LSI \u4f5c\u4e3a\u65f6\u949f\u6e90\u540e，\u4ecd\u7136\u80fd\u6b63\u5e38\u8fd0\u884c，\u6240\u4ee5\u9009\u62e9 LP_TIM1 \u4f5c\u4e3a Stop 2 \u6a21\u5f0f\u7684\u65f6\u95f4\u8865\u507f\u5b9a\u65f6\u5668\u3002<\/p>\n

\u4f11\u7720\u7684\u65f6\u95f4\u8865\u507f\u9700\u8981\u5b9e\u73b0\u4e09\u4e2a\u63a5\u53e3，\u5206\u522b\u7528\u4e8e\u542f\u52a8\u4f4e\u529f\u8017\u5b9a\u65f6\u5668\u3001\u505c\u6b62\u5b9a\u65f6\u5668\u3001\u5524\u9192\u540e\u83b7\u53d6\u4f11\u7720\u7684 Tick，\u4e0b\u9762\u662f\u5177\u4f53\u7684\u5b9e\u73b0：<\/p>\n

static<\/span> void<\/span> pm_timer_start<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm,<\/span> rt_uint32_t<\/span> timeout)<\/span>
\n{<\/span>
\n RT_ASSERT<\/span>(<\/span>pm !=<\/span> RT_NULL)<\/span>;<\/span>
\n RT_ASSERT<\/span>(<\/span>timeout ><\/span> 0<\/span>)<\/span>;<\/span><\/p>\n

\/**
\n * \u5f53\u8d85\u65f6\u4e3a RT_TICK_MAX \u65f6，\u8868\u660e\u7cfb\u7edf\u6b64\u65f6\u6ca1\u6709\u4f9d\u8d56 OS Tick \u7684\u5e94\u7528，
\n * \u56e0\u6b64\u4e0d\u542f\u52a8\u4f4e\u529f\u8017\u5b9a\u65f6\u5668，\u907f\u514d\u8d85\u65f6\u5524\u9192\u800c\u589e\u52a0\u7cfb\u7edf\u529f\u8017
\n *\/<\/span>
\n if<\/span> (<\/span>timeout !=<\/span> RT_TICK_MAX)<\/span>
\n {<\/span>
\n \/* Convert OS Tick to pmtimer timeout value *\/<\/span>
\n timeout =<\/span> stm32l4_pm_tick_from_os_tick<\/span>(<\/span>timeout)<\/span>;<\/span>
\n if<\/span> (<\/span>timeout ><\/span> stm32l4_lptim_get_tick_max<\/span>(<\/span>)<\/span>)<\/span>
\n {<\/span>
\n timeout =<\/span> stm32l4_lptim_get_tick_max<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span><\/p>\n

\/* Enter PM_TIMER_MODE *\/<\/span>
\n stm32l4_lptim_start<\/span>(<\/span>timeout)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

static<\/span> void<\/span> pm_timer_stop<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm)<\/span>
\n{<\/span>
\n RT_ASSERT<\/span>(<\/span>pm !=<\/span> RT_NULL)<\/span>;<\/span><\/p>\n

\/* Reset pmtimer status *\/<\/span>
\n stm32l4_lptim_stop<\/span>(<\/span>)<\/span>;<\/span>
\n}<\/span><\/p>\n

static<\/span> rt_tick_t<\/span> pm_timer_get_tick<\/span>(<\/span>struct<\/span> rt_pm<\/span> *<\/span>pm)<\/span>
\n{<\/span>
\n rt_uint32_t<\/span> timer_tick;<\/span><\/p>\n

RT_ASSERT<\/span>(<\/span>pm !=<\/span> RT_NULL)<\/span>;<\/span><\/p>\n

timer_tick =<\/span> stm32l4_lptim_get_current_tick<\/span>(<\/span>)<\/span>;<\/span><\/p>\n

return<\/span> stm32l4_os_tick_from_pm_tick<\/span>(<\/span>timer_tick)<\/span>;<\/span>
\n}<\/span><\/p>\n

int<\/span> rt_hw_pm_init<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n static<\/span> const<\/span> struct<\/span> rt_pm_ops<\/span> _ops =<\/span>
\n {<\/span>
\n sleep,<\/span>
\n RT_NULL,<\/span>
\n pm_timer_start,<\/span>
\n pm_timer_stop,<\/span>
\n pm_timer_get_tick
\n }<\/span>;<\/span><\/p>\n

rt_uint8_t<\/span> timer_mask =<\/span> 0<\/span>;<\/span><\/p>\n

\/* Enable Power Clock *\/<\/span>
\n __HAL_RCC_PWR_CLK_ENABLE<\/span>(<\/span>)<\/span>;<\/span><\/p>\n

\/* initialize timer mask *\/<\/span>
\n timer_mask =<\/span> 1UL<\/span> <<<\/span> PM_SLEEP_MODE_DEEP;<\/span><\/p>\n

\/* initialize system pm module *\/<\/span>
\n rt_system_pm_init<\/span>(<\/span>&<\/span>_ops,<\/span> timer_mask,<\/span> RT_NULL)<\/span>;<\/span><\/p>\n

return<\/span> 0<\/span>;<\/span>
\n}<\/span><\/p>\n

\u4f11\u7720\u65f6\u95f4\u8865\u507f\u7684\u79fb\u690d\u76f8\u5bf9\u5e76\u4e0d\u590d\u6742，\u6839\u636e Tick \u914d\u7f6e\u4f4e\u529f\u8017\u5b9a\u65f6\u5668\u8d85\u65f6，\u5524\u9192\u540e\u83b7\u53d6\u5b9e\u9645\u4f11\u7720\u65f6\u95f4\u5e76\u8f6c\u6362\u4e3aOS Tick，\u544a\u77e5 PM \u7ec4\u4ef6\u5373\u53ef\u3002\u53e6\u5916，\u4ece Stop 2 \u6a21\u5f0f\u5524\u9192\u540e，\u9ed8\u8ba4\u4f1a\u5207\u6362\u5230\u5185\u90e8\u7684 MSI \u65f6\u949f，\u901a\u5e38\u9700\u8981\u91cd\u65b0\u914d\u7f6e\u65f6\u949f\u6811\u3002<\/p>\n

4\u3001\u79fb\u690d\u8fd0\u884c\u6a21\u5f0f<\/h3>\n

STM32L476 \u7684\u8fd0\u884c\u6a21\u5f0f\u79fb\u690d\u4e3b\u8981\u662f\u901a\u8fc7\u6539\u53d8CPU \u9891\u7387 \u548c \u7a33\u538b\u5668，\u8ba9\u5176\u5de5\u4f5c\u5728 MR Range 2 \u6216\u8005 LP_RUN \u6a21\u5f0f，\u4e24\u4e2a\u6a21\u5f0f\u5207\u6362\u90fd\u4f1a\u89e6\u53d1 CPU \u9891\u7387\u6539\u53d8\u7684\u64cd\u4f5c，\u8fd9\u662f\u4e00\u4e2a\u6bd4\u8f83\u5371\u9669\u7684\u64cd\u4f5c\u3002<\/p>\n

\/*
\n * Copyright (c) 2006-2021, RT-Thread Development Team
\n *
\n * SPDX-License-Identifier: Apache-2.0
\n *
\n * Change Logs:
\n * Date Author Notes
\n * 2019-02-05 gw first version
\n * 2019-05-05 Zero-Free Adding multiple configurations for system clock frequency
\n *\/<\/span><\/p>\n

#<\/span>include<\/span> <board.h><\/span><\/span>
\n#<\/span>include<\/span> <rtconfig.h><\/span><\/span>
\n#<\/span>include<\/span> <drv_common.h><\/span><\/span><\/p>\n

void<\/span> SystemClock_Config<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n RCC_OscInitTypeDef RCC_OscInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span>
\n RCC_ClkInitTypeDef RCC_ClkInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span>
\n RCC_PeriphCLKInitTypeDef PeriphClkInit =<\/span> {<\/span>0<\/span>}<\/span>;<\/span><\/p>\n

#<\/span>ifdef<\/span> BSP_USING_ONCHIP_RTC<\/span><\/span>
\n \/**Configure LSE Drive Capability
\n *\/<\/span>
\n HAL_PWR_EnableBkUpAccess<\/span>(<\/span>)<\/span>;<\/span>
\n __HAL_RCC_LSEDRIVE_CONFIG<\/span>(<\/span>RCC_LSEDRIVE_LOW)<\/span>;<\/span>
\n#<\/span>endif<\/span><\/span>
\n \/**Initializes the CPU, AHB and APB busses clocks
\n *\/<\/span>
\n RCC_OscInitStruct.<\/span>OscillatorType =<\/span> RCC_OSCILLATORTYPE_HSI;<\/span>
\n RCC_OscInitStruct.<\/span>HSIState =<\/span> RCC_HSI_ON;<\/span>
\n RCC_OscInitStruct.<\/span>HSICalibrationValue =<\/span> RCC_HSICALIBRATION_DEFAULT;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLState =<\/span> RCC_PLL_ON;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLSource =<\/span> RCC_PLLSOURCE_HSI;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLM =<\/span> 1<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLN =<\/span> 10<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLP =<\/span> RCC_PLLP_DIV7;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLQ =<\/span> RCC_PLLQ_DIV2;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLR =<\/span> RCC_PLLR_DIV2;<\/span>
\n if<\/span> (<\/span>HAL_RCC_OscConfig<\/span>(<\/span>&<\/span>RCC_OscInitStruct)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n \/**Initializes the CPU, AHB and APB busses clocks
\n *\/<\/span>
\n RCC_ClkInitStruct.<\/span>ClockType =<\/span> RCC_CLOCKTYPE_HCLK |<\/span> RCC_CLOCKTYPE_SYSCLK
\n |<\/span> RCC_CLOCKTYPE_PCLK1 |<\/span> RCC_CLOCKTYPE_PCLK2;<\/span>
\n RCC_ClkInitStruct.<\/span>SYSCLKSource =<\/span> RCC_SYSCLKSOURCE_PLLCLK;<\/span>
\n RCC_ClkInitStruct.<\/span>AHBCLKDivider =<\/span> RCC_SYSCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB1CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB2CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span><\/p>\n

if<\/span> (<\/span>HAL_RCC_ClockConfig<\/span>(<\/span>&<\/span>RCC_ClkInitStruct,<\/span> FLASH_LATENCY_4)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n PeriphClkInit.<\/span>PeriphClockSelection =<\/span> RCC_PERIPHCLK_USART2;<\/span>
\n PeriphClkInit.<\/span>Usart2ClockSelection =<\/span> RCC_USART2CLKSOURCE_PCLK1;<\/span>
\n if<\/span> (<\/span>HAL_RCCEx_PeriphCLKConfig<\/span>(<\/span>&<\/span>PeriphClkInit)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n \/**Configure the main internal regulator output voltage
\n *\/<\/span>
\n if<\/span> (<\/span>HAL_PWREx_ControlVoltageScaling<\/span>(<\/span>PWR_REGULATOR_VOLTAGE_SCALE1)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

#<\/span>ifdef<\/span> RT_USING_PM<\/span><\/span><\/p>\n

void<\/span> SystemClock_MSI_ON<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n RCC_OscInitTypeDef RCC_OscInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span>
\n RCC_ClkInitTypeDef RCC_ClkInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span><\/p>\n

\/* Initializes the CPU, AHB and APB busses clocks *\/<\/span>
\n RCC_OscInitStruct.<\/span>OscillatorType =<\/span> RCC_OSCILLATORTYPE_MSI;<\/span>
\n RCC_OscInitStruct.<\/span>MSIState =<\/span> RCC_MSI_ON;<\/span>
\n if<\/span> (<\/span>HAL_RCC_OscConfig<\/span>(<\/span>&<\/span>RCC_OscInitStruct)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n RT_ASSERT<\/span>(<\/span>0<\/span>)<\/span>;<\/span>
\n }<\/span><\/p>\n

RCC_ClkInitStruct.<\/span>ClockType =<\/span> RCC_CLOCKTYPE_SYSCLK;<\/span>
\n RCC_ClkInitStruct.<\/span>SYSCLKSource =<\/span> RCC_SYSCLKSOURCE_MSI;<\/span>
\n if<\/span> (<\/span>HAL_RCC_ClockConfig<\/span>(<\/span>&<\/span>RCC_ClkInitStruct,<\/span> FLASH_LATENCY_1)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

void<\/span> SystemClock_MSI_OFF<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n RCC_OscInitTypeDef RCC_OscInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span><\/p>\n

RCC_OscInitStruct.<\/span>OscillatorType =<\/span> RCC_OSCILLATORTYPE_MSI;<\/span>
\n RCC_OscInitStruct.<\/span>HSIState =<\/span> RCC_MSI_OFF;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLState =<\/span> RCC_PLL_NONE;<\/span> \/* No update on PLL *\/<\/span>
\n if<\/span> (<\/span>HAL_RCC_OscConfig<\/span>(<\/span>&<\/span>RCC_OscInitStruct)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

void<\/span> SystemClock_80M<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n RCC_OscInitTypeDef RCC_OscInitStruct;<\/span>
\n RCC_ClkInitTypeDef RCC_ClkInitStruct;<\/span><\/p>\n

\/**Initializes the CPU, AHB and APB busses clocks *\/<\/span>
\n RCC_OscInitStruct.<\/span>OscillatorType =<\/span> RCC_OSCILLATORTYPE_HSI;<\/span>
\n RCC_OscInitStruct.<\/span>HSIState =<\/span> RCC_HSI_ON;<\/span>
\n RCC_OscInitStruct.<\/span>HSICalibrationValue =<\/span> 16<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLState =<\/span> RCC_PLL_ON;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLSource =<\/span> RCC_PLLSOURCE_HSI;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLM =<\/span> 1<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLN =<\/span> 10<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLP =<\/span> RCC_PLLP_DIV7;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLQ =<\/span> RCC_PLLQ_DIV2;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLR =<\/span> RCC_PLLR_DIV2;<\/span>
\n if<\/span> (<\/span>HAL_RCC_OscConfig<\/span>(<\/span>&<\/span>RCC_OscInitStruct)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span><\/p>\n

\/**Initializes the CPU, AHB and APB busses clocks
\n *\/<\/span>
\n RCC_ClkInitStruct.<\/span>ClockType =<\/span> RCC_CLOCKTYPE_HCLK |<\/span> RCC_CLOCKTYPE_SYSCLK
\n |<\/span> RCC_CLOCKTYPE_PCLK1 |<\/span> RCC_CLOCKTYPE_PCLK2;<\/span>
\n RCC_ClkInitStruct.<\/span>SYSCLKSource =<\/span> RCC_SYSCLKSOURCE_PLLCLK;<\/span>
\n RCC_ClkInitStruct.<\/span>AHBCLKDivider =<\/span> RCC_SYSCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB1CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB2CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span><\/p>\n

if<\/span> (<\/span>HAL_RCC_ClockConfig<\/span>(<\/span>&<\/span>RCC_ClkInitStruct,<\/span> FLASH_LATENCY_4)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

void<\/span> SystemClock_24M<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n RCC_OscInitTypeDef RCC_OscInitStruct;<\/span>
\n RCC_ClkInitTypeDef RCC_ClkInitStruct;<\/span>
\n RCC_PeriphCLKInitTypeDef PeriphClkInit;<\/span><\/p>\n

\/** Initializes the CPU, AHB and APB busses clocks *\/<\/span>
\n RCC_OscInitStruct.<\/span>OscillatorType =<\/span> RCC_OSCILLATORTYPE_HSI;<\/span>
\n RCC_OscInitStruct.<\/span>HSIState =<\/span> RCC_HSI_ON;<\/span>
\n RCC_OscInitStruct.<\/span>HSICalibrationValue =<\/span> 16<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLState =<\/span> RCC_PLL_ON;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLSource =<\/span> RCC_PLLSOURCE_HSI;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLM =<\/span> 1<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLN =<\/span> 12<\/span>;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLP =<\/span> RCC_PLLP_DIV7;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLQ =<\/span> RCC_PLLQ_DIV2;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLR =<\/span> RCC_PLLR_DIV8;<\/span>
\n if<\/span> (<\/span>HAL_RCC_OscConfig<\/span>(<\/span>&<\/span>RCC_OscInitStruct)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n \/** Initializes the CPU, AHB and APB busses clocks *\/<\/span>
\n RCC_ClkInitStruct.<\/span>ClockType =<\/span> RCC_CLOCKTYPE_HCLK |<\/span> RCC_CLOCKTYPE_SYSCLK
\n |<\/span> RCC_CLOCKTYPE_PCLK1 |<\/span> RCC_CLOCKTYPE_PCLK2;<\/span>
\n RCC_ClkInitStruct.<\/span>SYSCLKSource =<\/span> RCC_SYSCLKSOURCE_PLLCLK;<\/span>
\n RCC_ClkInitStruct.<\/span>AHBCLKDivider =<\/span> RCC_SYSCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB1CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB2CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span>
\n if<\/span> (<\/span>HAL_RCC_ClockConfig<\/span>(<\/span>&<\/span>RCC_ClkInitStruct,<\/span> FLASH_LATENCY_1)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n PeriphClkInit.<\/span>PeriphClockSelection =<\/span> RCC_PERIPHCLK_USART2;<\/span>
\n PeriphClkInit.<\/span>Usart2ClockSelection =<\/span> RCC_USART2CLKSOURCE_PCLK1;<\/span>
\n if<\/span> (<\/span>HAL_RCCEx_PeriphCLKConfig<\/span>(<\/span>&<\/span>PeriphClkInit)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

void<\/span> SystemClock_2M<\/span>(<\/span>void<\/span>)<\/span>
\n{<\/span>
\n RCC_ClkInitTypeDef RCC_ClkInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span>
\n RCC_OscInitTypeDef RCC_OscInitStruct =<\/span> {<\/span>0<\/span>}<\/span>;<\/span><\/p>\n

\/* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) *\/<\/span>
\n RCC_OscInitStruct.<\/span>OscillatorType =<\/span> RCC_OSCILLATORTYPE_MSI;<\/span>
\n RCC_OscInitStruct.<\/span>MSIState =<\/span> RCC_MSI_ON;<\/span>
\n RCC_OscInitStruct.<\/span>MSIClockRange =<\/span> RCC_MSIRANGE_5;<\/span>
\n RCC_OscInitStruct.<\/span>MSICalibrationValue =<\/span> RCC_MSICALIBRATION_DEFAULT;<\/span>
\n RCC_OscInitStruct.<\/span>PLL.<\/span>PLLState =<\/span> RCC_PLL_NONE;<\/span>
\n if<\/span> (<\/span>HAL_RCC_OscConfig<\/span>(<\/span>&<\/span>RCC_OscInitStruct)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n \/* Initialization Error *\/<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span><\/p>\n

\/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
\n clocks dividers *\/<\/span>
\n RCC_ClkInitStruct.<\/span>ClockType =<\/span> RCC_CLOCKTYPE_SYSCLK;<\/span>
\n RCC_ClkInitStruct.<\/span>SYSCLKSource =<\/span> RCC_SYSCLKSOURCE_MSI;<\/span>
\n RCC_ClkInitStruct.<\/span>AHBCLKDivider =<\/span> RCC_SYSCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB1CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span>
\n RCC_ClkInitStruct.<\/span>APB2CLKDivider =<\/span> RCC_HCLK_DIV1;<\/span>
\n if<\/span> (<\/span>HAL_RCC_ClockConfig<\/span>(<\/span>&<\/span>RCC_ClkInitStruct,<\/span> FLASH_LATENCY_0)<\/span> !=<\/span> HAL_OK)<\/span>
\n {<\/span>
\n \/* Initialization Error *\/<\/span>
\n Error_Handler<\/span>(<\/span>)<\/span>;<\/span>
\n }<\/span>
\n}<\/span><\/p>\n

\/**
\n * @brief Configures system clock after wake-up from STOP: enable HSI, PLL
\n * and select PLL as system clock source.
\n * @param None
\n * @retval None
\n *\/<\/span>
\nvoid<\/span> SystemClock_ReConfig<\/span>(<\/span>uint8_t<\/span> mode)<\/span>
\n{<\/span>
\n SystemClock_MSI_ON<\/span>(<\/span>)<\/span>;<\/span><\/p>\n

switch<\/span> (<\/span>mode)<\/span>
\n {<\/span>
\n case<\/span> PM_RUN_MODE_HIGH_SPEED:<\/span>
\n case<\/span> PM_RUN_MODE_NORMAL_SPEED:<\/span>
\n SystemClock_80M<\/span>(<\/span>)<\/span>;<\/span>
\n break<\/span>;<\/span>
\n case<\/span> PM_RUN_MODE_MEDIUM_SPEED:<\/span>
\n SystemClock_24M<\/span>(<\/span>)<\/span>;<\/span>
\n break<\/span>;<\/span>
\n case<\/span> PM_RUN_MODE_LOW_SPEED:<\/span>
\n SystemClock_2M<\/span>(<\/span>)<\/span>;<\/span>
\n break<\/span>;<\/span>
\n default<\/span>:<\/span>
\n break<\/span>;<\/span>
\n }<\/span><\/p>\n

\/\/ SystemClock_MSI_OFF();<\/span>
\n}<\/span><\/p>\n

#<\/span>endif<\/span><\/span><\/p>\n

\u6309\u4e0b\u590d\u4f4d\u6309\u952e\u91cd\u542f\u5f00\u53d1\u677f，\u6253\u5f00\u7ec8\u7aef\u8f6f\u4ef6，\u6211\u4eec\u53ef\u4ee5\u770b\u5230\u6709\u5b9a\u65f6\u8f93\u51fa\u65e5\u5fd7：<\/p>\n

\\\\ |<\/span> \/<\/span>
\n–<\/span> RT –<\/span> Thread Operating System
\n \/<\/span> |<\/span> \\\\ 4.0<\/span>.<\/span>1<\/span> build May 9<\/span> 2019<\/span>
\n 2006<\/span> –<\/span> 2019<\/span> Copyright by rt–<\/span>thread team
\nmsh ><\/span>current tick:<\/span> 2001<\/span>
\ncurrent tick:<\/span> 4002<\/span>
\ncurrent tick:<\/span> 6003<\/span>
\ncurrent tick:<\/span> 8004<\/span><\/p>\n

\u6211\u4eec\u53ef\u4ee5\u5728msh\u91cc\u8f93\u5165pm_dump\u547d\u4ee4\u89c2\u5bdfPM\u7ec4\u4ef6\u7684\u6a21\u5f0f\u72b6\u6001：<\/p>\n

pm_dump
\n|<\/span> Power Management Mode |<\/span> Counter |<\/span> Timer |<\/span>
\n+<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>–<\/span>+<\/span>—<\/span>—<\/span>—<\/span>—<\/span>–<\/span>+<\/span>—<\/span>—<\/span>—<\/span>–<\/span>+<\/span>
\n|<\/span> None Mode |<\/span> 0<\/span> |<\/span> 0<\/span> |<\/span>
\n|<\/span> Idle Mode |<\/span> 1<\/span> |<\/span> 0<\/span> |<\/span>
\n|<\/span> LightSleep Mode |<\/span> 1<\/span> |<\/span> 0<\/span> |<\/span>
\n|<\/span> DeepSleep Mode |<\/span> 1<\/span> |<\/span> 1<\/span> |<\/span>
\n|<\/span> Standby Mode |<\/span> 0<\/span> |<\/span> 0<\/span> |<\/span>
\n|<\/span> Shutdown Mode |<\/span> 0<\/span> |<\/span> 0<\/span> |<\/span>
\n+<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>—<\/span>–<\/span>+<\/span>—<\/span>—<\/span>—<\/span>—<\/span>–<\/span>+<\/span>—<\/span>—<\/span>—<\/span>–<\/span>+<\/span>
\npm current sleep mode:<\/span> Idle Mode
\npm current run mode:<\/span> Normal Speed
\nmsh ><\/span><\/p>\n

\u4ee5\u4e0a\u7684\u8f93\u51fa\u8bf4\u660e，PM \u7ec4\u4ef6\u91cc Idle\u3001Light Sleep\u3001Deep Sleep \u90fd\u88ab\u8bf7\u6c42\u4e86\u4e00\u6b21，\u73b0\u5728\u6b63\u5904\u4e8e\u7a7a\u95f2\u6a21\u5f0f（Idle Mode）\u3002<\/p>\n

\u6211\u4eec\u4f9d\u6b21\u8f93\u5165\u547d\u4ee4pm_release 1\u548cpm_release 2 \u624b\u52a8\u91ca\u653e Idle \u548c Light Sleep \u6a21\u5f0f\u540e，\u5c06\u8fdb\u5165Deep Sleep Mode\u3002\u8fdb\u5165Deep Sleep Mode\u4e4b\u540e\u4f1a\u5b9a\u65f6\u5524\u9192，shell \u8fd8\u662f\u4e00\u76f4\u5728\u8f93\u51fa：<\/p>\n

msh \/<\/span>><\/span>pm_release 1<\/span>
\nmsh \/<\/span>><\/span>
\nmsh \/<\/span>><\/span>current tick:<\/span> 8023<\/span>
\ncurrent tick:<\/span> 10024<\/span>
\ncurrent tick:<\/span> 12025<\/span><\/p>\n

msh \/<\/span>><\/span>pm_release 2<\/span>
\nmsh \/<\/span>><\/span>
\nmsh \/<\/span>><\/span>current tick:<\/span> 14026<\/span>
\ncurrent tick:<\/span> 16027<\/span>
\ncurrent tick:<\/span> 18028<\/span>
\ncurrent tick:<\/span> 20029<\/span>
\ncurrent tick:<\/span> 22030<\/span>
\ncurrent tick:<\/span> 24031<\/span><\/p>\n

\u6211\u4eec\u53ef\u4ee5\u901a\u8fc7\u529f\u8017\u4eea\u5668\u89c2\u5bdf\u529f\u8017\u7684\u53d8\u5316\u3002\u4e0b\u56fe\u662f\u57fa\u4e8e Monsoon Solutions Inc \u7684 Power Monitor \u7684\u8fd0\u884c\u622a\u56fe，\u53ef\u4ee5\u770b\u5230\u968f\u7740\u6a21\u5f0f\u53d8\u5316，\u529f\u8017\u660e\u663e\u53d8\u5316：
\n\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\"<\/p>\n

\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\"<\/p>\n","protected":false},"excerpt":{"rendered":"

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