{"id":121682,"date":"2026-11-03T10:17:04","date_gmt":"2026-11-03T02:17:04","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/121682.html"},"modified":"2026-11-03T10:17:04","modified_gmt":"2026-11-03T02:17:04","slug":"fpga-%e5%8d%83%e5%85%86%e4%bb%a5%e5%a4%aa%e7%bd%91%e5%b8%a7%e6%a0%bc%e5%bc%8f%e5%85%a8%e8%a7%a3%ef%bc%9a%e4%bb%8e-ieee-802-3-%e5%b8%a7%e7%bb%93%e6%9e%84%e5%88%b0-verilog-%e6%94%b6%e5%8f%91%e5%ae%9e","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/121682.html","title":{"rendered":"FPGA \u5343\u5146\u4ee5\u592a\u7f51\u5e27\u683c\u5f0f\u5168\u89e3\uff1a\u4ece IEEE 802.3 \u5e27\u7ed3\u6784\u5230 Verilog \u6536\u53d1\u5b9e\u73b0"},"content":{"rendered":"<h3>1. \u4e3a\u4ec0\u4e48 FPGA \u5de5\u7a0b\u5e08\u5fc5\u987b\u5403\u900f\u4ee5\u592a\u7f51\u5e27\u683c\u5f0f<\/h3>\n<p>\u5728 FPGA \u4e0a\u505a\u5343\u5146\u4ee5\u592a\u7f51&#xff08;1000BASE-T \/ 1000BASE-X&#xff09;&#xff0c;\u5f88\u591a\u4eba\u7b2c\u4e00\u6b65\u5c31\u5361\u4f4f&#xff1a;PHY \u82af\u7247\u5df2\u7ecf\u94fe\u8def up&#xff0c;MAC \u4fa7\u4e5f\u6536\u5230\u4e86\u6570\u636e&#xff0c;\u4f46\u6293\u5305\u5de5\u5177\u91cc\u5168\u662f\u9519\u5e27&#xff0c;\u6216\u8005\u4e0a\u4f4d\u673a\u6839\u672c\u6536\u4e0d\u5230\u5305\u3002\u6392\u67e5\u5230\u6700\u540e&#xff0c;\u95ee\u9898\u5f80\u5f80\u4e0d\u5728\u65f6\u5e8f\u3001\u4e0d\u5728\u65f6\u949f\u57df&#xff0c;\u800c\u662f\u5e27\u683c\u5f0f\u7684\u67d0\u4e2a\u5b57\u6bb5\u5199\u9519\u4e86\u2014\u2014\u524d\u5bfc\u7801\u5c11\u4e86\u4e00\u4e2a\u5b57\u8282\u3001FCS \u7b97\u9519\u4e86\u3001IFG \u4e0d\u591f\u3001\u957f\u5ea6\u5b57\u6bb5\u548c\u5b9e\u9645\u8d1f\u8f7d\u5bf9\u4e0d\u4e0a\u3002<\/p>\n<p>\u5982\u679c\u9700\u8981\u7cfb\u7edf\u5b66\u4e60FPGA&#xff0c;\u8fd9\u91cc\u6709\u4e00\u4efd\u6574\u7406\u7684FPGA\u6c47\u603b\u8bfe\u7a0b\u8d44\u6599&#xff0c;\u5305\u542bBD\u6559\u7a0b\u3001Vivado\u6559\u7a0b\u3001IP \u6838\u6559\u7a0b\u7b49&#xff0c;\u6709\u9700\u8981\u7684\u670b\u53cb\u53ef\u4ee5\u4fdd\u5b58&#xff1a;\u94fe\u63a5: https:\/\/pan.baidu.com\/s\/1pIFS8GEYu_jH1np4ZLG2Kw?pwd&#061;wbbw \u63d0\u53d6\u7801: wbbw \u6574\u7406\u4e0d\u6613&#xff0c;\u5c3d\u5feb\u4fdd\u5b58<\/p>\n<p>\u4ee5\u592a\u7f51\u5e27\u683c\u5f0f\u770b\u8d77\u6765\u7b80\u5355&#xff1a;7 \u5b57\u8282\u524d\u5bfc\u7801 &#043; 1 \u5b57\u8282 SFD &#043; 6 \u5b57\u8282\u76ee\u7684 MAC &#043; 6 \u5b57\u8282\u6e90 MAC &#043; 2 \u5b57\u8282\u7c7b\u578b\/\u957f\u5ea6 &#043; 46~1500 \u5b57\u8282\u8d1f\u8f7d &#043; 4 \u5b57\u8282 FCS\u3002\u4f46\u771f\u6b63\u843d\u5230 RTL \u91cc&#xff0c;\u6bcf\u4e00\u4e2a\u5b57\u8282\u90fd\u6709\u8bb2\u7a76&#xff1a;<\/p>\n<ul>\n<li>\u524d\u5bfc\u7801\u662f 0x55 \u8fd8\u662f 0xAA&#xff1f;\u4e3a\u4ec0\u4e48\u662f\u4ea4\u66ff\u7684 1010 \u8fd8\u662f 0101&#xff1f;<\/li>\n<li>SFD \u662f 0xD5&#xff0c;\u5b83\u5728 8 \u4f4d\u6570\u636e\u901a\u8def\u4e0a\u5230\u5e95\u600e\u4e48\u5bf9\u9f50&#xff1f;<\/li>\n<li>\u7c7b\u578b\u5b57\u6bb5 0x0800 \u662f\u5927\u7aef\u8fd8\u662f\u5c0f\u7aef&#xff1f;\u5728 8 \u4f4d\u603b\u7ebf\u4e0a\u5148\u53d1\u9ad8\u5b57\u8282\u8fd8\u662f\u4f4e\u5b57\u8282&#xff1f;<\/li>\n<li>\u6700\u5c0f\u5e27 64 \u5b57\u8282\u662f\u600e\u4e48\u7b97\u51fa\u6765\u7684&#xff1f;\u4e0d\u542b\u524d\u5bfc\u7801\u8fd8\u662f\u542b&#xff1f;<\/li>\n<li>FCS \u7684 CRC-32 \u591a\u9879\u5f0f\u662f\u54ea\u4e2a&#xff1f;\u521d\u503c\u3001\u53cd\u5c04\u3001\u6700\u7ec8\u5f02\u6216\u5206\u522b\u662f\u4ec0\u4e48&#xff1f;<\/li>\n<li>\u5343\u5146\u6a21\u5f0f\u4e0b GMII \u662f 8 \u4f4d 125MHz&#xff0c;RGMII \u662f DDR \u53cc\u6cbf&#xff0c;SGMII \u662f\u4e32\u884c 1.25Gbps&#xff0c;\u5e27\u683c\u5f0f\u4e00\u6837\u4f46\u63a5\u53e3\u65f6\u5e8f\u5b8c\u5168\u4e0d\u540c\u3002<\/li>\n<li><\/li>\n<\/ul>\n<p>\u5982\u679c\u9700\u8981\u7cfb\u7edf\u5b66\u4e60FPGA&#xff0c;\u8fd9\u91cc\u6709\u4e00\u4efd\u6574\u7406\u7684FPGA\u6c47\u603b\u8bfe\u7a0b\u8d44\u6599&#xff0c;\u5305\u542bBD\u6559\u7a0b\u3001Vivado\u6559\u7a0b\u3001IP \u6838\u6559\u7a0b\u7b49&#xff0c;\u6709\u9700\u8981\u7684\u670b\u53cb\u53ef\u4ee5\u4fdd\u5b58&#xff1a;\u94fe\u63a5: https:\/\/pan.baidu.com\/s\/1pIFS8GEYu_jH1np4ZLG2Kw?pwd&#061;wbbw \u63d0\u53d6\u7801: wbbw \u6574\u7406\u4e0d\u6613&#xff0c;\u5c3d\u5feb\u4fdd\u5b58<\/p>\n<p>\u8fd9\u7bc7\u6587\u7ae0\u53ea\u8bb2\u4e00\u4ef6\u4e8b&#xff1a;FPGA \u91cc\u5343\u5146\u4ee5\u592a\u7f51\u5e27\u683c\u5f0f\u7684\u5b8c\u6574\u5b9a\u4e49&#xff0c;\u4ee5\u53ca\u5982\u4f55\u7528 Verilog \u628a\u5b83\u4e00\u4e2a\u5b57\u8282\u4e00\u4e2a\u5b57\u8282\u5730\u53d1\u51fa\u53bb\u3001\u6536\u8fdb\u6765\u3002\u4e0d\u8bb2 TCP\/IP \u534f\u8bae\u6808&#xff0c;\u4e0d\u8bb2 UDP \u6821\u9a8c\u548c&#xff0c;\u4e0d\u8bb2 ARP \u6d41\u7a0b&#xff0c;\u53ea\u628a\u4e8c\u5c42\u5e27\u683c\u5f0f\u548c\u5b83\u7684\u786c\u4ef6\u5b9e\u73b0\u8bb2\u900f\u3002<\/p>\n<p>\u5168\u6587\u4f1a\u8986\u76d6&#xff1a;<\/p>\n<li>IEEE 802.3 \/ Ethernet II \u5e27\u7684\u9010\u5b57\u6bb5\u5b9a\u4e49\u4e0e\u5b57\u8282\u5e8f&#xff1b;<\/li>\n<li>\u5343\u5146\u4ee5\u592a\u7f51\u7684\u7269\u7406\u5c42\u63a5\u53e3&#xff1a;GMII\u3001RGMII\u3001SGMII \u7684\u5dee\u5f02&#xff1b;<\/li>\n<li>\u53d1\u9001\u65b9\u5411&#xff1a;\u4ece\u5e27\u7f13\u5b58\u5230 GMII \u8f93\u51fa\u7684\u5b8c\u6574\u72b6\u6001\u673a&#xff1b;<\/li>\n<li>\u63a5\u6536\u65b9\u5411&#xff1a;\u4ece GMII \u8f93\u5165\u5230\u5e27\u89e3\u6790\u3001FCS \u6821\u9a8c\u7684\u72b6\u6001\u673a&#xff1b;<\/li>\n<li>CRC-32 FCS \u7684\u5e76\u884c\/\u4e32\u884c\u5b9e\u73b0\u4e0e\u9010\u4f4d\u63a8\u5bfc&#xff1b;<\/li>\n<li>\u524d\u5bfc\u7801\u3001SFD\u3001IFG\u3001\u80cc\u9760\u80cc\u5e27\u7684\u65f6\u5e8f\u7ec6\u8282&#xff1b;<\/li>\n<li>\u6700\u5c0f\u5e27\u586b\u5145\u3001\u5de8\u578b\u5e27\u3001VLAN \u6807\u7b7e\u6269\u5c55\u683c\u5f0f&#xff1b;<\/li>\n<li>\u5b8c\u6574\u53ef\u7efc\u5408\u7684 Verilog \u4ee3\u7801\u4e0e\u4eff\u771f\u9a8c\u8bc1\u65b9\u6cd5&#xff1b;<\/li>\n<li>\u5e38\u89c1\u9519\u8bef\u6e05\u5355\u4e0e\u8c03\u8bd5\u624b\u6bb5\u3002<\/li>\n<h3>1.1 \u4e3b\u8981\u65b9\u6848\u5bf9\u6bd4\u4e0e\u6574\u4f53\u5904\u7406\u6d41\u7a0b<\/h3>\n<p>\u5728\u6df1\u5165\u9010\u5b57\u6bb5\u7ec6\u8282\u4e4b\u524d&#xff0c;\u5148\u628a\u672c\u6587\u6d89\u53ca\u7684\u4e3b\u8981\u65b9\u6848\u653e\u5728\u4e00\u8d77\u6a2a\u5411\u5bf9\u6bd4&#xff0c;\u4fbf\u4e8e\u6839\u636e\u9879\u76ee\u5b9e\u9645\u9700\u6c42\u505a\u53d6\u820d\u3002\u4e0b\u8868\u4ece\u9002\u7528\u573a\u666f\u3001\u4f18\u7f3a\u70b9\u3001\u590d\u6742\u5ea6\u4e09\u4e2a\u7ef4\u5ea6\u8fdb\u884c\u68b3\u7406&#xff1a;<\/p>\n<table>\n<tr>\u65b9\u6848\u9002\u7528\u573a\u666f\u4f18\u70b9\u7f3a\u70b9\u590d\u6742\u5ea6<\/tr>\n<tbody>\n<tr>\n<td>Ethernet II \u5e27\u683c\u5f0f<\/td>\n<td>\u7edd\u5927\u591a\u6570 IP\/\u79c1\u6709\u534f\u8bae\u6570\u636e\u91c7\u96c6\u3001\u56fe\u50cf\u4f20\u8f93<\/td>\n<td>\u4e0e\u4e3b\u6d41\u534f\u8bae\u6808\u517c\u5bb9&#xff0c;EtherType \u8bed\u4e49\u6e05\u6670&#xff0c;\u89e3\u6790\u7b80\u5355<\/td>\n<td>\u65e0\u957f\u5ea6\u5b57\u6bb5&#xff0c;\u77ed\u5e27\u9700\u4f9d\u8d56\u4e0a\u5c42\u534f\u8bae\u5224\u65ad\u771f\u5b9e\u957f\u5ea6<\/td>\n<td>\u4f4e<\/td>\n<\/tr>\n<tr>\n<td>IEEE 802.3 \u5e27\u683c\u5f0f<\/td>\n<td>\u9700\u8981\u663e\u5f0f\u957f\u5ea6\u5b57\u6bb5\u7684 LLC\/SNAP \u573a\u666f\u3001\u90e8\u5206\u5de5\u4e1a\u534f\u8bae<\/td>\n<td>\u81ea\u5e26\u957f\u5ea6\u5b57\u6bb5&#xff0c;\u4fbf\u4e8e\u63a5\u6536\u7aef\u88c1\u526a\u586b\u5145<\/td>\n<td>\u9700\u989d\u5916\u89e3\u6790 LLC\/SNAP \u5934&#xff0c;\u5b9e\u9645\u4f7f\u7528\u8f83\u5c11<\/td>\n<td>\u4e2d<\/td>\n<\/tr>\n<tr>\n<td>GMII \u63a5\u53e3<\/td>\n<td>FPGA \u4e0e PHY \u540c\u677f\u3001\u5f15\u811a\u8d44\u6e90\u5145\u8db3<\/td>\n<td>8 \u4f4d\u5e76\u884c\u3001\u65f6\u5e8f\u76f4\u89c2\u3001\u8c03\u8bd5\u65b9\u4fbf<\/td>\n<td>\u4fe1\u53f7\u7ebf\u7ea6 25 \u6839&#xff0c;\u5f15\u811a\u5360\u7528\u5927<\/td>\n<td>\u4f4e<\/td>\n<\/tr>\n<tr>\n<td>RGMII \u63a5\u53e3<\/td>\n<td>\u677f\u7ea7\u8bbe\u8ba1\u4e3b\u6d41\u3001\u5f15\u811a\u53d7\u9650\u573a\u666f<\/td>\n<td>\u5f15\u811a\u6570\u51cf\u534a&#xff0c;\u6210\u672c\u4f4e<\/td>\n<td>DDR \u53cc\u6cbf\u65f6\u5e8f&#xff0c;\u9700\u5904\u7406 1.5~2ns skew&#xff0c;\u65f6\u5e8f\u7ea6\u675f\u590d\u6742<\/td>\n<td>\u4e2d<\/td>\n<\/tr>\n<tr>\n<td>SGMII \u63a5\u53e3<\/td>\n<td>\u9700\u8981\u957f\u8ddd\u79bb\/\u80cc\u677f\u4f20\u8f93\u3001\u4f7f\u7528\u9ad8\u901f\u6536\u53d1\u5668<\/td>\n<td>\u4e32\u884c\u5dee\u5206&#xff0c;\u6297\u5e72\u6270\u5f3a&#xff0c;\u8d70\u7ebf\u7b80\u5355<\/td>\n<td>\u4f9d\u8d56 GTX\/GTH \u6536\u53d1\u5668&#xff0c;8b\/10b \u7f16\u7801&#xff0c;\u8c03\u8bd5\u95e8\u69db\u9ad8<\/td>\n<td>\u9ad8<\/td>\n<\/tr>\n<tr>\n<td>\u9010\u4f4d\u4e32\u884c CRC-32<\/td>\n<td>\u4f4e\u901f\u94fe\u8def\u3001\u8d44\u6e90\u6781\u5ea6\u53d7\u9650<\/td>\n<td>\u903b\u8f91\u6781\u7b80&#xff0c;\u8d44\u6e90\u5360\u7528\u5c11<\/td>\n<td>\u6bcf\u5468\u671f\u4ec5 1 bit&#xff0c;\u5343\u5146\u4e0b\u65e0\u6cd5\u6ee1\u8db3\u541e\u5410<\/td>\n<td>\u4f4e<\/td>\n<\/tr>\n<tr>\n<td>8 \u4f4d\u5e76\u884c CRC-32<\/td>\n<td>\u5343\u5146 MAC \u53d1\u9001\/\u63a5\u6536 FCS \u8ba1\u7b97<\/td>\n<td>\u5355\u5468\u671f\u5904\u7406 1 \u5b57\u8282&#xff0c;\u6ee1\u8db3 125MHz \u541e\u5410<\/td>\n<td>\u5f02\u6216\u8868\u8fbe\u5f0f\u957f&#xff0c;\u9700\u811a\u672c\u751f\u6210\u6216 IP \u652f\u6301<\/td>\n<td>\u4e2d<\/td>\n<\/tr>\n<tr>\n<td>\u5355\u5e27\u7f13\u5b58<\/td>\n<td>\u4f4e\u901f\u3001\u975e\u8fde\u7eed\u53d1\u9001\u573a\u666f<\/td>\n<td>\u7ed3\u6784\u7b80\u5355&#xff0c;BRAM \u5360\u7528\u5c11<\/td>\n<td>\u65e0\u6cd5\u4e52\u4e53&#xff0c;\u541e\u5410\u53d7\u9650<\/td>\n<td>\u4f4e<\/td>\n<\/tr>\n<tr>\n<td>\u4e52\u4e53\u53cc\u7f13\u5b58<\/td>\n<td>\u9ad8\u541e\u5410\u3001\u8fde\u7eed\u80cc\u9760\u80cc\u53d1\u9001<\/td>\n<td>\u53d1\u9001\u4e0e\u586b\u5145\u5e76\u884c&#xff0c;\u541e\u5410\u9ad8<\/td>\n<td>\u63a7\u5236\u903b\u8f91\u590d\u6742&#xff0c;BRAM \u7ffb\u500d<\/td>\n<td>\u9ad8<\/td>\n<\/tr>\n<tr>\n<td>\u6807\u51c6\u5e27&#xff08;\u22641518 \u5b57\u8282&#xff09;<\/td>\n<td>\u901a\u7528\u4ee5\u592a\u7f51\u4e92\u901a<\/td>\n<td>\u517c\u5bb9\u6240\u6709\u4ea4\u6362\u673a\u4e0e\u7f51\u5361<\/td>\n<td>\u5355\u5e27\u6709\u6548\u8d1f\u8f7d\u6709\u9650<\/td>\n<td>\u4f4e<\/td>\n<\/tr>\n<tr>\n<td>\u5de8\u578b\u5e27&#xff08;Jumbo&#xff09;<\/td>\n<td>\u5927\u6570\u636e\u5757\u4f20\u8f93\u3001\u70b9\u5bf9\u70b9\u76f4\u8fde<\/td>\n<td>\u51cf\u5c11\u5e27\u6570\u3001\u964d\u4f4e\u534f\u8bae\u5f00\u9500<\/td>\n<td>\u975e\u6807\u51c6&#xff0c;\u9700\u4e24\u7aef\u534f\u5546&#xff0c;\u4ea4\u6362\u673a\u53ef\u80fd\u4e0d\u652f\u6301<\/td>\n<td>\u4e2d<\/td>\n<\/tr>\n<tr>\n<td>802.1Q VLAN Tag<\/td>\n<td>\u591a\u4e1a\u52a1\u9694\u79bb\u3001\u4f18\u5148\u7ea7\u8c03\u5ea6<\/td>\n<td>\u5355\u5e27\u643a\u5e26 VLAN \u4fe1\u606f&#xff0c;\u7075\u6d3b<\/td>\n<td>\u5e27\u957f\u589e\u52a0 4 \u5b57\u8282&#xff0c;\u9700\u89e3\u6790 TPID\/TCI<\/td>\n<td>\u4e2d<\/td>\n<\/tr>\n<tr>\n<td>QinQ \u53cc\u6807\u7b7e<\/td>\n<td>\u8fd0\u8425\u5546\u7ea7\u591a\u79df\u6237\u9694\u79bb<\/td>\n<td>\u53cc\u5c42\u6807\u7b7e&#xff0c;\u9694\u79bb\u7c92\u5ea6\u66f4\u7ec6<\/td>\n<td>\u5e27\u957f\u589e\u52a0 8 \u5b57\u8282&#xff0c;\u89e3\u6790\u5c42\u7ea7\u66f4\u591a<\/td>\n<td>\u9ad8<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u4ece\u8868\u4e2d\u53ef\u4ee5\u770b\u51fa&#xff1a;\u5e27\u683c\u5f0f\u9009 Ethernet II\u3001\u63a5\u53e3\u6309\u677f\u7ea7\u6761\u4ef6\u5728 GMII\/RGMII\/SGMII \u4e2d\u53d6\u820d\u3001CRC \u7528 8 \u4f4d\u5e76\u884c\u3001\u7f13\u5b58\u6309\u541e\u5410\u9700\u6c42\u51b3\u5b9a\u662f\u5426\u4e52\u4e53&#xff0c;\u662f\u7edd\u5927\u591a\u6570 FPGA \u5343\u5146\u4ee5\u592a\u7f51\u9879\u76ee\u7684\u5408\u7406\u8d77\u70b9\u3002<\/p>\n<p>\u4e0b\u9762\u7528\u4e00\u5f20\u6d41\u7a0b\u56fe\u5c55\u793a\u4ece\u4e0a\u5c42\u5e94\u7528\u8bf7\u6c42\u5230\u5e27\u4e0a\u7ebf\u7684\u6574\u4f53\u5904\u7406\u6d41\u7a0b&#xff0c;\u6db5\u76d6\u53d1\u9001\u4e0e\u63a5\u6536\u4e24\u6761\u4e3b\u8def\u5f84&#xff1a;<\/p>\n<p>#mermaid-svg-tPjaibC3Mz0Nwcjw{font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;font-size:16px;fill:#333;}@keyframes edge-animation-frame{from{stroke-dashoffset:0;}}@keyframes dash{to{stroke-dashoffset:0;}}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-animation-slow{stroke-dasharray:9,5!important;stroke-dashoffset:900;animation:dash 50s linear infinite;stroke-linecap:round;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-animation-fast{stroke-dasharray:9,5!important;stroke-dashoffset:900;animation:dash 20s linear infinite;stroke-linecap:round;}#mermaid-svg-tPjaibC3Mz0Nwcjw .error-icon{fill:#552222;}#mermaid-svg-tPjaibC3Mz0Nwcjw .error-text{fill:#552222;stroke:#552222;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-thickness-normal{stroke-width:1px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-thickness-thick{stroke-width:3.5px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-pattern-solid{stroke-dasharray:0;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-thickness-invisible{stroke-width:0;fill:none;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-pattern-dashed{stroke-dasharray:3;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edge-pattern-dotted{stroke-dasharray:2;}#mermaid-svg-tPjaibC3Mz0Nwcjw .marker{fill:#333333;stroke:#333333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .marker.cross{stroke:#333333;}#mermaid-svg-tPjaibC3Mz0Nwcjw svg{font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;font-size:16px;}#mermaid-svg-tPjaibC3Mz0Nwcjw p{margin:0;}#mermaid-svg-tPjaibC3Mz0Nwcjw .label{font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;color:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .cluster-label text{fill:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .cluster-label span{color:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .cluster-label span p{background-color:transparent;}#mermaid-svg-tPjaibC3Mz0Nwcjw .label text,#mermaid-svg-tPjaibC3Mz0Nwcjw span{fill:#333;color:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .node rect,#mermaid-svg-tPjaibC3Mz0Nwcjw .node circle,#mermaid-svg-tPjaibC3Mz0Nwcjw .node ellipse,#mermaid-svg-tPjaibC3Mz0Nwcjw .node polygon,#mermaid-svg-tPjaibC3Mz0Nwcjw .node path{fill:#ECECFF;stroke:#9370DB;stroke-width:1px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .rough-node .label text,#mermaid-svg-tPjaibC3Mz0Nwcjw .node .label text,#mermaid-svg-tPjaibC3Mz0Nwcjw .image-shape .label,#mermaid-svg-tPjaibC3Mz0Nwcjw .icon-shape .label{text-anchor:middle;}#mermaid-svg-tPjaibC3Mz0Nwcjw .node .katex path{fill:#000;stroke:#000;stroke-width:1px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .rough-node .label,#mermaid-svg-tPjaibC3Mz0Nwcjw .node .label,#mermaid-svg-tPjaibC3Mz0Nwcjw .image-shape .label,#mermaid-svg-tPjaibC3Mz0Nwcjw .icon-shape .label{text-align:center;}#mermaid-svg-tPjaibC3Mz0Nwcjw .node.clickable{cursor:pointer;}#mermaid-svg-tPjaibC3Mz0Nwcjw .root .anchor path{fill:#333333!important;stroke-width:0;stroke:#333333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .arrowheadPath{fill:#333333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edgePath .path{stroke:#333333;stroke-width:2.0px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .flowchart-link{stroke:#333333;fill:none;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edgeLabel{background-color:rgba(232,232,232, 0.8);text-align:center;}#mermaid-svg-tPjaibC3Mz0Nwcjw .edgeLabel p{background-color:rgba(232,232,232, 0.8);}#mermaid-svg-tPjaibC3Mz0Nwcjw .edgeLabel rect{opacity:0.5;background-color:rgba(232,232,232, 0.8);fill:rgba(232,232,232, 0.8);}#mermaid-svg-tPjaibC3Mz0Nwcjw .labelBkg{background-color:rgba(232, 232, 232, 0.5);}#mermaid-svg-tPjaibC3Mz0Nwcjw .cluster rect{fill:#ffffde;stroke:#aaaa33;stroke-width:1px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .cluster text{fill:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw .cluster span{color:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw div.mermaidTooltip{position:absolute;text-align:center;max-width:200px;padding:2px;font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;font-size:12px;background:hsl(80, 100%, 96.2745098039%);border:1px solid #aaaa33;border-radius:2px;pointer-events:none;z-index:100;}#mermaid-svg-tPjaibC3Mz0Nwcjw .flowchartTitleText{text-anchor:middle;font-size:18px;fill:#333;}#mermaid-svg-tPjaibC3Mz0Nwcjw rect.text{fill:none;stroke-width:0;}#mermaid-svg-tPjaibC3Mz0Nwcjw .icon-shape,#mermaid-svg-tPjaibC3Mz0Nwcjw .image-shape{background-color:rgba(232,232,232, 0.8);text-align:center;}#mermaid-svg-tPjaibC3Mz0Nwcjw .icon-shape p,#mermaid-svg-tPjaibC3Mz0Nwcjw .image-shape p{background-color:rgba(232,232,232, 0.8);padding:2px;}#mermaid-svg-tPjaibC3Mz0Nwcjw .icon-shape .label rect,#mermaid-svg-tPjaibC3Mz0Nwcjw .image-shape .label rect{opacity:0.5;background-color:rgba(232,232,232, 0.8);fill:rgba(232,232,232, 0.8);}#mermaid-svg-tPjaibC3Mz0Nwcjw .label-icon{display:inline-block;height:1em;overflow:visible;vertical-align:-0.125em;}#mermaid-svg-tPjaibC3Mz0Nwcjw .node .label-icon path{fill:currentColor;stroke:revert;stroke-width:revert;}#mermaid-svg-tPjaibC3Mz0Nwcjw :root{&#8211;mermaid-font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;}<span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u662f<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u5426<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u5426<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u662f<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u5426<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u662f<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u5426<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u662f<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u4e0a\u5c42\u5e94\u7528\u8bf7\u6c42\u53d1\u9001<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u8d1f\u8f7d\u957f\u5ea6 &lt; 46 \u5b57\u8282?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u586b\u5145 0 \u81f3 46 \u5b57\u8282<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u6309\u5b9e\u9645\u957f\u5ea6\u7ec4\u5e27<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u586b\u5145 DA \/ SA \/ Type<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>8 \u4f4d\u5e76\u884c CRC-32 \u8ba1\u7b97 FCS<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u53d1\u9001\u72b6\u6001\u673a: \u524d\u5bfc\u7801 7\u00d70x55<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u53d1\u9001 SFD 0xD5<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u9010\u5b57\u8282\u53d1\u9001 DA\/SA\/Type\/Payload<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u9ad8\u5b57\u8282\u5148\u53d1 4 \u5b57\u8282 FCS<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>IFG \u7b49\u5f85 12 \u4e2a\u5468\u671f<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u7ecf GMII\/RGMII\/SGMII \u8f93\u51fa\u81f3 PHY<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>PHY \u8f93\u5165 GMII \u6570\u636e<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u68c0\u6d4b\u524d\u5bfc\u7801 0x55<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u68c0\u6d4b\u5230 SFD 0xD5?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u9010\u5b57\u8282\u63a5\u6536\u5e76\u5199\u5165\u5e27\u7f13\u5b58<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u540c\u6b65\u8ba1\u7b97 CRC-32<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u63a5\u6536 4 \u5b57\u8282 FCS<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>CRC \u6821\u9a8c\u901a\u8fc7?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u6807\u8bb0 err_crc \u5e76\u4e22\u5f03<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u957f\u5ea6 \u2265 64 \u5b57\u8282?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u6807\u8bb0 err_len \u5e76\u4e22\u5f03<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u8f93\u51fa rx_valid \u4e0e\u5e27\u4fe1\u606f<\/p>\n<p><\/span><\/p>\n<p>\u6d41\u7a0b\u56fe\u4e2d\u5de6\u4fa7\u4e3a\u53d1\u9001\u8def\u5f84&#xff0c;\u53f3\u4fa7\u4e3a\u63a5\u6536\u8def\u5f84\u3002\u53d1\u9001\u4fa7\u7684\u5173\u952e\u662f\u586b\u5145\u3001\u7ec4\u5e27\u3001CRC\u3001\u524d\u5bfc\u7801\/SFD\u3001FCS \u5b57\u8282\u5e8f\u3001IFG\u516d\u4e2a\u73af\u8282&#xff1b;\u63a5\u6536\u4fa7\u7684\u5173\u952e\u662f\u524d\u5bfc\u7801\u540c\u6b65\u3001SFD \u8bc6\u522b\u3001CRC \u6821\u9a8c\u3001\u957f\u5ea6\u68c0\u67e5\u56db\u4e2a\u73af\u8282\u3002\u540e\u7eed\u5404\u7ae0\u8282\u5c06\u56f4\u7ed5\u8fd9\u4e9b\u73af\u8282\u9010\u4e00\u5c55\u5f00\u3002<\/p>\n<h3>2. \u4ee5\u592a\u7f51\u5e27\u683c\u5f0f\u7684\u6743\u5a01\u5b9a\u4e49<\/h3>\n<p>\u5982\u679c\u9700\u8981\u7cfb\u7edf\u5b66\u4e60FPGA&#xff0c;\u8fd9\u91cc\u6709\u4e00\u4efd\u6574\u7406\u7684FPGA\u6c47\u603b\u8bfe\u7a0b\u8d44\u6599&#xff0c;\u5305\u542bBD\u6559\u7a0b\u3001Vivado\u6559\u7a0b\u3001IP \u6838\u6559\u7a0b\u7b49&#xff0c;\u6709\u9700\u8981\u7684\u670b\u53cb\u53ef\u4ee5\u4fdd\u5b58&#xff1a;\u94fe\u63a5: https:\/\/pan.baidu.com\/s\/1pIFS8GEYu_jH1np4ZLG2Kw?pwd&#061;wbbw \u63d0\u53d6\u7801: wbbw \u6574\u7406\u4e0d\u6613&#xff0c;\u5c3d\u5feb\u4fdd\u5b58<\/p>\n<h4>2.1 \u4e24\u79cd\u5e27\u683c\u5f0f&#xff1a;Ethernet II \u4e0e IEEE 802.3<\/h4>\n<p>\u5386\u53f2\u4e0a\u5b58\u5728\u4e24\u79cd\u5e27\u683c\u5f0f&#xff0c;\u533a\u522b\u53ea\u5728\u7b2c 13~14 \u5b57\u8282&#xff08;\u4ece\u76ee\u7684 MAC \u7b97\u8d77\u7684\u504f\u79fb 12~13&#xff09;\u7684\u8bed\u4e49&#xff1a;<\/p>\n<table>\n<tr>\u5b57\u6bb5\u4f4d\u7f6e&#xff08;\u4ece DA \u8d77&#xff09;Ethernet IIIEEE 802.3<\/tr>\n<tbody>\n<tr>\n<td>0~5<\/td>\n<td>\u76ee\u7684 MAC<\/td>\n<td>\u76ee\u7684 MAC<\/td>\n<\/tr>\n<tr>\n<td>6~11<\/td>\n<td>\u6e90 MAC<\/td>\n<td>\u6e90 MAC<\/td>\n<\/tr>\n<tr>\n<td>12~13<\/td>\n<td>EtherType&#xff08;\u2265 0x0600&#xff09;<\/td>\n<td>Length&#xff08;\u2264 1500&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>14~<\/td>\n<td>\u8d1f\u8f7d<\/td>\n<td>LLC\/SNAP \u5934 &#043; \u8d1f\u8f7d<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u5224\u65ad\u89c4\u5219\u5f88\u7b80\u5355&#xff1a;\u8fd9\u4e2a 16 \u4f4d\u5b57\u6bb5\u7684\u503c \u2265 0x0600&#xff08;1536&#xff09; \u5c31\u6309 EtherType \u89e3\u91ca&#xff0c;\u2264 0x05DC&#xff08;1500&#xff09; \u5c31\u6309\u957f\u5ea6\u89e3\u91ca\u3002\u4e2d\u95f4 1501~1535 \u662f\u672a\u5b9a\u4e49\u533a\u95f4\u3002<\/p>\n<p>\u4eca\u5929\u5b9e\u9645\u7f51\u7edc\u4e2d 99% \u4ee5\u4e0a\u662f Ethernet II&#xff0c;\u56e0\u4e3a IP \u62a5\u6587\u7528 0x0800\u3001ARP \u7528 0x0806\u3001IPv6 \u7528 0x86DD\u3001VLAN \u7528 0x8100\u3002FPGA \u505a\u6570\u636e\u91c7\u96c6\u3001\u56fe\u50cf\u4f20\u8f93\u3001\u9ad8\u901f\u91c7\u96c6\u5361&#xff0c;\u57fa\u672c\u90fd\u7528 Ethernet II\u3002\u672c\u6587\u4ee5 Ethernet II \u4e3a\u4e3b&#xff0c;\u540c\u65f6\u8bf4\u660e 802.3 \u957f\u5ea6\u5b57\u6bb5\u7684\u5904\u7406\u65b9\u5f0f\u3002<\/p>\n<h4>2.2 \u5b8c\u6574\u5e27\u7ed3\u6784&#xff08;\u4e0d\u542b\u7269\u7406\u5c42\u5c01\u88c5&#xff09;<\/h4>\n<p>\u4ece MAC \u5b50\u5c42\u770b&#xff0c;\u4e00\u4e2a\u5b8c\u6574\u7684\u4ee5\u592a\u7f51\u5e27\u5982\u4e0b&#xff1a;<\/p>\n<p>&#043;&#8212;&#8212;&#8212;&#043;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#043;&#8212;&#8211;&#043;<br \/>\n|Preamble | SFD |   DA   |   SA   |  Type  |  Payload   | FCS |<br \/>\n|  7 Byte |1Byte| 6 Byte | 6 Byte | 2 Byte | 46~1500 B  |4Byte|<br \/>\n&#043;&#8212;&#8212;&#8212;&#043;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#043;&#8212;&#8211;&#043;<\/p>\n<p>\u5404\u5b57\u6bb5\u542b\u4e49&#xff1a;<\/p>\n<ul>\n<li>Preamble&#xff08;\u524d\u5bfc\u7801&#xff09;&#xff1a;7 \u4e2a\u5b57\u8282&#xff0c;\u6bcf\u4e2a\u5b57\u8282 0x55&#xff0c;\u5373\u4e8c\u8fdb\u5236 0101_0101\u3002\u5728\u7269\u7406\u5c42\u4e0a\u8868\u73b0\u4e3a 7 \u4e2a\u5468\u671f\u7684 5MHz \u65b9\u6ce2&#xff08;\u5343\u5146\u4e0b\u662f 125MHz \u7684 0101 \u4ea4\u66ff&#xff09;&#xff0c;\u7528\u4e8e\u63a5\u6536\u7aef CDR&#xff08;\u65f6\u949f\u6570\u636e\u6062\u590d&#xff09;\u9501\u5b9a\u76f8\u4f4d\u3001\u5747\u8861\u5668\u6536\u655b\u3002<\/li>\n<li>SFD&#xff08;\u5e27\u8d77\u59cb\u5b9a\u754c\u7b26&#xff09;&#xff1a;1 \u4e2a\u5b57\u8282 0xD5&#xff0c;\u4e8c\u8fdb\u5236 1101_0101\u3002\u524d 6 \u4f4d\u4ecd\u662f 101010 \u7684\u5ef6\u7eed&#xff0c;\u6700\u540e\u4e24\u4f4d 11 \u8868\u793a&#034;\u540e\u9762\u5f00\u59cb\u662f\u771f\u6b63\u7684\u6570\u636e&#034;\u3002\u63a5\u6536\u7aef\u68c0\u6d4b\u5230 &#8230;10101011 \u8fd9\u4e2a\u6a21\u5f0f\u5c31\u8ba4\u4e3a\u5e27\u5f00\u59cb\u3002<\/li>\n<li>DA&#xff08;Destination Address&#xff09;&#xff1a;6 \u5b57\u8282\u76ee\u7684 MAC \u5730\u5740&#xff0c;\u5148\u53d1\u7b2c 0 \u5b57\u8282&#xff08;\u6700\u9ad8\u5b57\u8282&#xff0c;OUI \u90e8\u5206&#xff09;\u3002<\/li>\n<li>SA&#xff08;Source Address&#xff09;&#xff1a;6 \u5b57\u8282\u6e90 MAC \u5730\u5740&#xff0c;\u540c\u6837\u5148\u53d1\u9ad8\u5b57\u8282\u3002<\/li>\n<li>Type\/Length&#xff1a;2 \u5b57\u8282&#xff0c;\u5148\u53d1\u9ad8\u5b57\u8282\u3002EtherType \u5e38\u89c1\u503c\u89c1\u4e0b\u8868\u3002<\/li>\n<li>Payload&#xff1a;46~1500 \u5b57\u8282\u3002\u4e0d\u8db3 46 \u5b57\u8282\u8981\u586b\u5145&#xff08;padding&#xff09;\u5230 46&#xff0c;\u4fdd\u8bc1\u6574\u5e27&#xff08;\u4e0d\u542b\u524d\u5bfc\u7801\u548c SFD&#xff09;\u81f3\u5c11 64 \u5b57\u8282\u3002<\/li>\n<li>FCS&#xff08;Frame Check Sequence&#xff09;&#xff1a;4 \u5b57\u8282 CRC-32&#xff0c;\u8986\u76d6\u8303\u56f4\u662f DA &#043; SA &#043; Type &#043; Payload &#043; Padding&#xff0c;\u4e0d\u5305\u62ec\u524d\u5bfc\u7801\u548c SFD\u3002\u53d1\u9001\u65f6\u6309 CRC \u8ba1\u7b97\u7ed3\u679c\u7684\u9ad8\u5b57\u8282\u5148\u53d1\u8fd8\u662f\u4f4e\u5b57\u8282\u5148\u53d1&#xff0c;\u662f\u4e00\u4e2a\u9ad8\u9891\u8e29\u5751\u70b9&#xff0c;\u540e\u9762\u4e13\u95e8\u8bb2\u3002<\/li>\n<\/ul>\n<h4>2.3 \u5e38\u89c1 EtherType \u53d6\u503c<\/h4>\n<table>\n<tr>EtherType\u534f\u8bae<\/tr>\n<tbody>\n<tr>\n<td>0x0800<\/td>\n<td>IPv4<\/td>\n<\/tr>\n<tr>\n<td>0x0806<\/td>\n<td>ARP<\/td>\n<\/tr>\n<tr>\n<td>0x8100<\/td>\n<td>IEEE 802.1Q VLAN Tag<\/td>\n<\/tr>\n<tr>\n<td>0x86DD<\/td>\n<td>IPv6<\/td>\n<\/tr>\n<tr>\n<td>0x8847<\/td>\n<td>MPLS Unicast<\/td>\n<\/tr>\n<tr>\n<td>0x88CC<\/td>\n<td>LLDP<\/td>\n<\/tr>\n<tr>\n<td>0x88F7<\/td>\n<td>PTP (IEEE 1588)<\/td>\n<\/tr>\n<tr>\n<td>0x8892<\/td>\n<td>PROFINET<\/td>\n<\/tr>\n<tr>\n<td>0x88A4<\/td>\n<td>EtherCAT<\/td>\n<\/tr>\n<tr>\n<td>0x22F0<\/td>\n<td>AVTP (\u97f3\u89c6\u9891\u4f20\u8f93)<\/td>\n<\/tr>\n<tr>\n<td>0x88B5 \/ 0x88B6<\/td>\n<td>\u5b9e\u9a8c\u7528 EtherType&#xff08;\u672c\u5730\u5b9e\u9a8c\u63a8\u8350&#xff09;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u505a FPGA \u79c1\u6709\u534f\u8bae\u65f6&#xff0c;\u5efa\u8bae\u4f7f\u7528 0x88B5 \u6216 0x88B6&#xff0c;\u8fd9\u662f IEEE \u4fdd\u7559\u7ed9\u672c\u5730\u5b9e\u9a8c\u7684 EtherType&#xff0c;\u4e0d\u4f1a\u548c\u516c\u7f51\u534f\u8bae\u51b2\u7a81\u3002<\/p>\n<h4>2.4 \u5e27\u957f\u7ea6\u675f<\/h4>\n<table>\n<tr>\u9879\u76ee\u6570\u503c\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u6700\u5c0f\u5e27\u957f&#xff08;\u4e0d\u542b\u524d\u5bfc\u7801&#043;SFD&#xff09;<\/td>\n<td>64 \u5b57\u8282<\/td>\n<td>DA&#043;SA&#043;Type&#043;Payload&#043;FCS<\/td>\n<\/tr>\n<tr>\n<td>\u6700\u5c0f\u8d1f\u8f7d<\/td>\n<td>46 \u5b57\u8282<\/td>\n<td>64 &#8211; 6 &#8211; 6 &#8211; 2 &#8211; 4 &#061; 46<\/td>\n<\/tr>\n<tr>\n<td>\u6700\u5927\u5e27\u957f&#xff08;\u6807\u51c6&#xff09;<\/td>\n<td>1518 \u5b57\u8282<\/td>\n<td>\u4e0d\u542b\u524d\u5bfc\u7801&#043;SFD&#xff0c;\u4e0d\u542b VLAN Tag<\/td>\n<\/tr>\n<tr>\n<td>\u6700\u5927\u8d1f\u8f7d<\/td>\n<td>1500 \u5b57\u8282<\/td>\n<td>MTU<\/td>\n<\/tr>\n<tr>\n<td>\u5e26 VLAN Tag \u6700\u5927\u5e27\u957f<\/td>\n<td>1522 \u5b57\u8282<\/td>\n<td>\u591a\u4e86 4 \u5b57\u8282 Tag<\/td>\n<\/tr>\n<tr>\n<td>\u5de8\u578b\u5e27&#xff08;Jumbo&#xff09;<\/td>\n<td>\u901a\u5e38 9000 \u5b57\u8282<\/td>\n<td>\u975e\u6807\u51c6&#xff0c;\u9700\u4e24\u7aef\u534f\u5546<\/td>\n<\/tr>\n<tr>\n<td>\u524d\u5bfc\u7801&#043;SFD<\/td>\n<td>8 \u5b57\u8282<\/td>\n<td>\u7269\u7406\u5c42\u5f00\u9500<\/td>\n<\/tr>\n<tr>\n<td>IFG&#xff08;\u5e27\u95f4\u9694&#xff09;<\/td>\n<td>12 \u5b57\u8282\u65f6\u95f4<\/td>\n<td>96 bit time&#xff0c;\u5343\u5146\u4e0b 96ns<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u6ce8\u610f&#xff1a;64 \u5b57\u8282\u6700\u5c0f\u5e27\u4e0d\u542b\u524d\u5bfc\u7801\u548c SFD\u3002\u5f88\u591a\u8d44\u6599\u5199&#034;\u6700\u5c0f\u5e27 64 \u5b57\u8282&#034;&#xff0c;\u7136\u540e\u53c8\u8bf4&#034;\u52a0\u4e0a\u524d\u5bfc\u7801 8 \u5b57\u8282\u5171 72 \u5b57\u8282&#034;&#xff0c;\u8fd9\u4e24\u4e2a\u8bf4\u6cd5\u90fd\u5bf9&#xff0c;\u53ea\u662f\u7edf\u8ba1\u53e3\u5f84\u4e0d\u540c\u3002\u5728 RTL \u91cc\u505a\u957f\u5ea6\u68c0\u67e5\u65f6&#xff0c;\u8981\u660e\u786e\u4f60\u7edf\u8ba1\u7684\u662f\u4ece DA \u5f00\u59cb\u8fd8\u662f\u4ece Preamble \u5f00\u59cb\u3002<\/p>\n<p>\u5343\u5146\u901f\u7387\u4e0b&#xff0c;\u4e00\u4e2a\u6700\u5c0f\u5e27&#xff08;64 \u5b57\u8282 &#061; 512 bit&#xff09;\u52a0\u4e0a\u524d\u5bfc\u7801&#xff08;64 bit&#xff09;\u548c IFG&#xff08;96 bit&#xff09;&#xff0c;\u603b\u5171 672 bit&#xff0c;\u5373 672ns\u3002\u7406\u8bba\u6700\u5927\u5e27\u901f\u7387 &#061; 1 \/ 672ns \u2248 1.488 Mpps\u3002\u8fd9\u4e2a\u6570\u5b57\u5728\u505a\u6d41\u91cf\u53d1\u751f\u5668\u65f6\u7ecf\u5e38\u7528\u5230\u3002<\/p>\n<h3>3. \u5343\u5146\u4ee5\u592a\u7f51\u7684\u7269\u7406\u5c42\u63a5\u53e3<\/h3>\n<p>\u5e27\u683c\u5f0f\u662f MAC \u5c42\u7684\u4e8b&#xff0c;\u4f46 FPGA \u8981\u628a\u5b83\u9001\u51fa\u53bb&#xff0c;\u5fc5\u987b\u7ecf\u8fc7 PHY \u63a5\u53e3\u3002\u5343\u5146\u4ee5\u592a\u7f51\u5728 FPGA \u4fa7\u5e38\u89c1\u7684\u4e09\u79cd\u63a5\u53e3&#xff1a;<\/p>\n<h4>3.1 GMII&#xff08;Gigabit Media Independent Interface&#xff09;<\/h4>\n<p>GMII \u662f IEEE 802.3 \u5b9a\u4e49\u7684\u6807\u51c6\u63a5\u53e3&#xff1a;<\/p>\n<ul>\n<li>\u53d1\u9001&#xff1a;gtx_clk&#xff08;125MHz&#xff09;\u3001txd[7:0]\u3001tx_en\u3001tx_er&#xff1b;<\/li>\n<li>\u63a5\u6536&#xff1a;rx_clk&#xff08;\u4ece PHY \u6062\u590d\u7684 125MHz&#xff09;\u3001rxd[7:0]\u3001rx_dv\u3001rx_er&#xff1b;<\/li>\n<li>\u7ba1\u7406&#xff1a;mdc\u3001mdio\u3002<\/li>\n<\/ul>\n<p>8 \u4f4d\u6570\u636e \u00d7 125MHz &#061; 1000Mbps\u3002GMII \u9700\u8981 25 \u6839\u5de6\u53f3\u7684\u4fe1\u53f7\u7ebf&#xff0c;\u5f15\u811a\u591a&#xff0c;\u901a\u5e38\u53ea\u5728 FPGA \u4e0e PHY \u82af\u7247\u540c\u677f\u65f6\u4f7f\u7528\u3002<\/p>\n<p>\u5173\u952e\u65f6\u5e8f&#xff1a;tx_en \u62c9\u9ad8\u7684\u7b2c\u4e00\u4e2a\u5468\u671f&#xff0c;txd \u4e0a\u5c31\u662f\u524d\u5bfc\u7801\u7684\u7b2c\u4e00\u4e2a 0x55\u3002tx_en \u62c9\u4f4e\u7684\u6700\u540e\u4e00\u4e2a\u5468\u671f&#xff0c;txd \u4e0a\u662f FCS \u7684\u6700\u540e\u4e00\u4e2a\u5b57\u8282\u3002tx_en \u8fde\u7eed\u4e3a\u9ad8\u7684\u5468\u671f\u6570 &#061; \u5e27\u957f&#xff08;\u542b\u524d\u5bfc\u7801\u548c SFD&#xff09;\u3002<\/p>\n<h4>3.2 RGMII&#xff08;Reduced GMII&#xff09;<\/h4>\n<p>RGMII \u628a 8 \u4f4d\u6570\u636e\u780d\u6210 4 \u4f4d&#xff0c;\u7528 DDR&#xff08;\u53cc\u6cbf&#xff09;\u4f20\u8f93&#xff0c;125MHz \u00d7 2 \u00d7 4bit &#061; 1000Mbps\u3002\u5f15\u811a\u6570\u51cf\u534a&#xff0c;\u662f\u677f\u7ea7\u8bbe\u8ba1\u6700\u5e38\u7528\u7684\u63a5\u53e3\u3002<\/p>\n<ul>\n<li>\u53d1\u9001&#xff1a;tx_clk&#xff08;125MHz&#xff0c;\u7531 MAC \u63d0\u4f9b&#xff09;\u3001txd[3:0]\u3001tx_ctl&#xff1b;<\/li>\n<li>\u63a5\u6536&#xff1a;rx_clk&#xff08;PHY \u6062\u590d&#xff09;\u3001rxd[3:0]\u3001rx_ctl\u3002<\/li>\n<\/ul>\n<p>tx_ctl \u5728\u4e0a\u5347\u6cbf\u8868\u793a tx_en&#xff0c;\u4e0b\u964d\u6cbf\u8868\u793a tx_en XOR tx_er\u3002\u6570\u636e txd[3:0] \u5728\u4e0a\u5347\u6cbf\u662f\u4f4e 4 \u4f4d&#xff0c;\u4e0b\u964d\u6cbf\u662f\u9ad8 4 \u4f4d\u3002\u4e5f\u5c31\u662f\u8bf4&#xff0c;\u4e00\u4e2a GMII \u5b57\u8282\u5728 RGMII \u4e0a\u88ab\u62c6\u6210\u4e24\u4e2a\u534a\u5b57\u8282&#xff0c;\u5206\u522b\u5728\u65f6\u949f\u7684\u4e24\u4e2a\u6cbf\u53d1\u9001\u3002<\/p>\n<p>RGMII \u901a\u5e38\u9700\u8981 PHY \u5185\u90e8\u6216 FPGA \u4fa7\u52a0 1.5~2ns \u7684\u65f6\u949f\u5ef6\u8fdf&#xff08;TXC \u76f8\u5bf9 TXD \u7684 skew&#xff09;&#xff0c;\u5426\u5219\u91c7\u6837\u7a97\u53e3\u4f1a\u9519\u3002Xilinx 7 \u7cfb\u5217\u53ef\u4ee5\u7528 ODELAY\/IDELAY \u539f\u8bed&#xff0c;\u6216\u8005\u5728 PCB \u4e0a\u505a\u7b49\u957f\u7ed5\u7ebf\u3002<\/p>\n<h4>3.3 SGMII&#xff08;Serial GMII&#xff09;<\/h4>\n<p>SGMII \u662f\u4e32\u884c\u63a5\u53e3&#xff0c;1.25Gbps \u5dee\u5206\u5bf9&#xff0c;8b\/10b \u7f16\u7801&#xff0c;\u6709\u6548\u901f\u7387 1000Mbps\u3002FPGA \u4fa7\u9700\u8981 GTX\/GTH\/GTY \u6536\u53d1\u5668\u6216\u8005\u4e13\u7528\u7684 SGMII PHY\u3002<\/p>\n<p>SGMII \u7684\u5e27\u683c\u5f0f\u548c GMII \u5b8c\u5168\u4e00\u6837&#xff0c;\u53ea\u662f\u7269\u7406\u7f16\u7801\u4e0d\u540c\u3002\u6536\u53d1\u5668\u5185\u90e8\u5b8c\u6210 8b\/10b \u7f16\u89e3\u7801\u548c\u65f6\u949f\u6062\u590d&#xff0c;\u5bf9 MAC \u5c42\u5448\u73b0\u7684\u8fd8\u662f 8 \u4f4d\u6570\u636e &#043; \u6709\u6548\u4fe1\u53f7\u3002<\/p>\n<h4>3.4 \u4e09\u79cd\u63a5\u53e3\u7684\u5e27\u683c\u5f0f\u4e00\u81f4\u6027<\/h4>\n<p>\u91cd\u8981\u7ed3\u8bba&#xff1a;\u65e0\u8bba GMII\u3001RGMII \u8fd8\u662f SGMII&#xff0c;MAC \u5c42\u770b\u5230\u7684\u5e27\u683c\u5f0f\u5b8c\u5168\u76f8\u540c\u3002 \u524d\u5bfc\u7801\u3001SFD\u3001DA\u3001SA\u3001Type\u3001Payload\u3001FCS \u7684\u5b57\u8282\u5185\u5bb9\u548c\u987a\u5e8f\u4e0d\u53d8&#xff0c;\u53d8\u7684\u53ea\u662f\u7535\u6c14\u7279\u6027\u548c\u4f4d\u5bbd\/\u65f6\u949f\u3002<\/p>\n<p>\u6240\u4ee5\u672c\u6587\u7684 RTL \u8bbe\u8ba1\u4ee5 GMII \u4e3a\u57fa\u51c6&#xff08;8 \u4f4d\u6570\u636e\u901a\u8def\u6700\u76f4\u89c2&#xff09;&#xff0c;RGMII \u53ea\u9700\u8981\u5728 GMII \u5916\u9762\u5957\u4e00\u5c42 DDR \u8f6c\u6362&#xff0c;SGMII \u53ea\u9700\u8981\u628a GMII \u63a5\u5230\u6536\u53d1\u5668\u7684 GMII \u63a5\u53e3\u4e0a\u3002<\/p>\n<h3>4. \u5b57\u8282\u5e8f&#xff1a;\u6700\u5bb9\u6613\u51fa\u9519\u7684\u5730\u65b9<\/h3>\n<h4>4.1 \u7f51\u7edc\u5b57\u8282\u5e8f\u662f\u5927\u7aef<\/h4>\n<p>\u4ee5\u592a\u7f51\u89c4\u5b9a\u6240\u6709\u591a\u5b57\u8282\u5b57\u6bb5\u6309**\u5927\u7aef&#xff08;Big-Endian&#xff09;**\u4f20\u8f93&#xff0c;\u5373\u9ad8\u5b57\u8282\u5148\u53d1\u3002\u4f8b\u5982 EtherType &#061; 0x0800&#xff0c;\u5728 8 \u4f4d\u6570\u636e\u603b\u7ebf\u4e0a\u5148\u51fa\u73b0 0x08&#xff0c;\u518d\u51fa\u73b0 0x00\u3002<\/p>\n<p>MAC \u5730\u5740 00:1A:2B:3C:4D:5E&#xff0c;\u53d1\u9001\u987a\u5e8f\u662f 0x00\u30010x1A\u30010x2B\u30010x3C\u30010x4D\u30010x5E\u3002<\/p>\n<h4>4.2 \u5728 8 \u4f4d\u603b\u7ebf\u4e0a\u5982\u4f55\u7ec4\u7ec7<\/h4>\n<p>\u5047\u8bbe\u6211\u4eec\u6709\u4e00\u4e2a 64 \u4f4d\u5bbd\u7684\u5e27\u7f13\u5b58&#xff0c;\u91cc\u9762\u6309\u5c0f\u7aef\u5b58\u653e\u4e86 MAC \u5730\u5740&#xff0c;\u90a3\u4e48\u53d1\u9001\u65f6\u9700\u8981\u505a\u5b57\u8282\u91cd\u6392\u3002\u6700\u7a33\u59a5\u7684\u505a\u6cd5\u662f&#xff1a;\u5e27\u7f13\u5b58\u6309\u5b57\u8282\u6570\u7ec4\u7ec4\u7ec7&#xff0c;\u53d1\u9001\u72b6\u6001\u673a\u6309\u5b57\u8282\u7d22\u5f15\u53d6\u6570&#xff0c;\u4e0d\u8981\u8bd5\u56fe\u7528\u4f4d\u62fc\u63a5\u53bb&#034;\u4f18\u5316&#034;&#xff0c;\u90a3\u6837\u6781\u6613\u51fa\u9519\u3002<\/p>\n<p>\/\/ \u5e27\u7f13\u5b58&#xff1a;\u6309\u5b57\u8282\u5b58\u50a8&#xff0c;\u7d22\u5f15 0 \u662f DA \u7684\u7b2c 0 \u5b57\u8282<br \/>\nreg [7:0] frame_buf [0:2047];<\/p>\n<p>\u53d1\u9001\u65f6 frame_buf[0] \u5148\u53d1&#xff0c;frame_buf[1] \u6b21\u4e4b&#xff0c;\u4ee5\u6b64\u7c7b\u63a8\u3002\u8fd9\u6837\u5b57\u8282\u5e8f\u95ee\u9898\u5728\u7f13\u5b58\u586b\u5145\u9636\u6bb5\u5c31\u89e3\u51b3\u4e86&#xff0c;\u53d1\u9001\u72b6\u6001\u673a\u53ea\u7ba1\u987a\u5e8f\u53d6\u6570\u3002<\/p>\n<h4>4.3 FCS \u7684\u5b57\u8282\u5e8f\u9677\u9631<\/h4>\n<p>CRC-32 \u8ba1\u7b97\u51fa\u6765\u662f\u4e00\u4e2a 32 \u4f4d\u503c\u3002\u4ee5\u592a\u7f51\u89c4\u5b9a FCS \u5b57\u6bb5\u4f20\u8f93\u65f6&#xff0c;CRC \u7ed3\u679c\u7684\u6700\u9ad8\u5b57\u8282\u5148\u53d1&#xff0c;\u4f46\u6bcf\u4e2a\u5b57\u8282\u5185\u90e8\u662f\u4f4e\u4f4d\u5148\u53d1&#xff08;\u56e0\u4e3a CRC \u662f\u6309\u4f4d\u4e32\u884c\u8ba1\u7b97\u7684&#xff0c;\u4e14\u4ee5\u592a\u7f51\u662f LSB first&#xff09;\u3002<\/p>\n<p>\u5177\u4f53\u6765\u8bf4&#xff0c;\u5982\u679c CRC \u8ba1\u7b97\u7ed3\u679c\u662f 0x12345678&#xff0c;\u90a3\u4e48\u7ebf\u4e0a\u4f20\u8f93\u7684\u5b57\u8282\u987a\u5e8f\u662f 0x12\u30010x34\u30010x56\u30010x78&#xff0c;\u4f46\u6bcf\u4e2a\u5b57\u8282\u5728\u7269\u7406\u5c42\u662f LSB \u5148\u51fa\u3002\u5728 8 \u4f4d GMII \u4e0a&#xff0c;\u4e00\u4e2a\u5b57\u8282\u662f\u4e00\u4e2a\u5468\u671f&#xff0c;\u6240\u4ee5\u5b57\u8282\u987a\u5e8f\u5c31\u662f 0x12 \u2192 0x34 \u2192 0x56 \u2192 0x78\u3002<\/p>\n<p>\u5f88\u591a\u5b9e\u73b0\u9519\u8bef\u5730\u628a 0x78 \u5148\u53d1&#xff0c;\u5bfc\u81f4\u63a5\u6536\u7aef FCS \u6821\u9a8c\u5931\u8d25\u3002\u8bb0\u4f4f&#xff1a;FCS \u662f CRC \u503c\u7684\u9ad8\u5b57\u8282\u5728\u524d\u3002<\/p>\n<h3>5. \u53d1\u9001\u65b9\u5411 RTL \u8bbe\u8ba1<\/h3>\n<h4>5.1 \u6574\u4f53\u67b6\u6784<\/h4>\n<p>&#043;&#8212;&#8212;&#8212;&#8211;&#043;     &#043;&#8212;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#043;<br \/>\n| \u5e27\u7f13\u5b58    | &#8211;&gt; | \u53d1\u9001\u72b6\u6001\u673a  | &#8211;&gt; | CRC-32   | &#8211;&gt; | GMII |<br \/>\n| frame_buf |     | tx_fsm      |     | \u8ba1\u7b97\u6a21\u5757 |     | \u8f93\u51fa |<br \/>\n&#043;&#8212;&#8212;&#8212;&#8211;&#043;     &#043;&#8212;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#043;<\/p>\n<p>\u53d1\u9001\u72b6\u6001\u673a\u8d1f\u8d23&#xff1a;\u4ea7\u751f\u524d\u5bfc\u7801\u548c SFD\u3001\u6309\u5b57\u8282\u8bfb\u51fa DA\/SA\/Type\/Payload\u3001\u8ba1\u7b97\u5e76\u63d2\u5165 FCS\u3001\u63a7\u5236 IFG\u3002<\/p>\n<h4>5.2 \u72b6\u6001\u673a\u8bbe\u8ba1<\/h4>\n<p>module eth_tx (<br \/>\n    input  wire        clk,          \/\/ 125MHz<br \/>\n    input  wire        rst_n,<\/p>\n<p>    \/\/ \u5e27\u8bf7\u6c42\u63a5\u53e3<br \/>\n    input  wire        tx_req,       \/\/ \u8bf7\u6c42\u53d1\u9001\u4e00\u5e27<br \/>\n    input  wire [15:0] tx_len,       \/\/ \u8d1f\u8f7d\u957f\u5ea6&#xff08;\u4e0d\u542b\u524d\u5bfc\u7801\u3001FCS&#xff09;<br \/>\n    output reg         tx_busy,      \/\/ \u6b63\u5728\u53d1\u9001<br \/>\n    output reg         tx_done,      \/\/ \u53d1\u9001\u5b8c\u6210&#xff08;\u5355\u5468\u671f\u8109\u51b2&#xff09;<\/p>\n<p>    \/\/ \u5e27\u6570\u636e\u8bfb\u53d6\u63a5\u53e3<br \/>\n    output reg  [10:0] rd_addr,      \/\/ \u5b57\u8282\u5730\u5740<br \/>\n    input  wire [7:0]  rd_data,      \/\/ \u5b57\u8282\u6570\u636e<br \/>\n    output reg         rd_en,<\/p>\n<p>    \/\/ GMII \u8f93\u51fa<br \/>\n    output reg  [7:0]  gmii_txd,<br \/>\n    output reg         gmii_tx_en,<br \/>\n    output reg         gmii_tx_er<br \/>\n);<\/p>\n<p>    \/\/ \u72b6\u6001\u5b9a\u4e49<br \/>\n    localparam S_IDLE    &#061; 3&#039;d0;<br \/>\n    localparam S_PREAMBLE&#061; 3&#039;d1;<br \/>\n    localparam S_SFD     &#061; 3&#039;d2;<br \/>\n    localparam S_DATA    &#061; 3&#039;d3;<br \/>\n    localparam S_FCS     &#061; 3&#039;d4;<br \/>\n    localparam S_IFG     &#061; 3&#039;d5;<\/p>\n<p>    reg [2:0]  state, next_state;<br \/>\n    reg [3:0]  pre_cnt;      \/\/ \u524d\u5bfc\u7801\u5b57\u8282\u8ba1\u6570 0~6<br \/>\n    reg [10:0] byte_cnt;     \/\/ \u6570\u636e\u5b57\u8282\u8ba1\u6570<br \/>\n    reg [1:0]  fcs_cnt;      \/\/ FCS \u5b57\u8282\u8ba1\u6570 0~3<br \/>\n    reg [7:0]  ifg_cnt;      \/\/ IFG \u8ba1\u6570<\/p>\n<p>    \/\/ CRC \u8ba1\u7b97\u6a21\u5757\u63a5\u53e3<br \/>\n    reg        crc_init;<br \/>\n    reg        crc_en;<br \/>\n    reg  [7:0] crc_data;<br \/>\n    wire [31:0] crc_out;<\/p>\n<p>    \/\/ \u5e27\u603b\u957f\u5ea6 &#061; \u8d1f\u8f7d\u957f\u5ea6 &#043; 14&#xff08;DA&#043;SA&#043;Type&#xff09;<br \/>\n    wire [10:0] frame_len &#061; tx_len &#043; 11&#039;d14;<\/p>\n<p>    \/\/ CRC \u6a21\u5757\u4f8b\u5316<br \/>\n    crc32_8bit u_crc (<br \/>\n        .clk    (clk),<br \/>\n        .rst_n  (rst_n),<br \/>\n        .init   (crc_init),<br \/>\n        .en     (crc_en),<br \/>\n        .data   (crc_data),<br \/>\n        .crc    (crc_out)<br \/>\n    );<\/p>\n<p>    \/\/ \u72b6\u6001\u8f6c\u79fb<br \/>\n    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (!rst_n)<br \/>\n            state &lt;&#061; S_IDLE;<br \/>\n        else<br \/>\n            state &lt;&#061; next_state;<br \/>\n    end<\/p>\n<p>    always &#064;(*) begin<br \/>\n        next_state &#061; state;<br \/>\n        case (state)<br \/>\n            S_IDLE: begin<br \/>\n                if (tx_req)<br \/>\n                    next_state &#061; S_PREAMBLE;<br \/>\n            end<br \/>\n            S_PREAMBLE: begin<br \/>\n                if (pre_cnt &#061;&#061; 4&#039;d6)<br \/>\n                    next_state &#061; S_SFD;<br \/>\n            end<br \/>\n            S_SFD: begin<br \/>\n                next_state &#061; S_DATA;<br \/>\n            end<br \/>\n            S_DATA: begin<br \/>\n                if (byte_cnt &#061;&#061; frame_len &#8211; 1)<br \/>\n                    next_state &#061; S_FCS;<br \/>\n            end<br \/>\n            S_FCS: begin<br \/>\n                if (fcs_cnt &#061;&#061; 2&#039;d3)<br \/>\n                    next_state &#061; S_IFG;<br \/>\n            end<br \/>\n            S_IFG: begin<br \/>\n                if (ifg_cnt &#061;&#061; 8&#039;d11)<br \/>\n                    next_state &#061; S_IDLE;<br \/>\n            end<br \/>\n            default: next_state &#061; S_IDLE;<br \/>\n        endcase<br \/>\n    end<\/p>\n<p>    \/\/ \u8f93\u51fa\u903b\u8f91<br \/>\n    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (!rst_n) begin<br \/>\n            gmii_txd    &lt;&#061; 8&#039;h00;<br \/>\n            gmii_tx_en  &lt;&#061; 1&#039;b0;<br \/>\n            gmii_tx_er  &lt;&#061; 1&#039;b0;<br \/>\n            pre_cnt     &lt;&#061; 4&#039;d0;<br \/>\n            byte_cnt    &lt;&#061; 11&#039;d0;<br \/>\n            fcs_cnt     &lt;&#061; 2&#039;d0;<br \/>\n            ifg_cnt     &lt;&#061; 8&#039;d0;<br \/>\n            rd_addr     &lt;&#061; 11&#039;d0;<br \/>\n            rd_en       &lt;&#061; 1&#039;b0;<br \/>\n            tx_busy     &lt;&#061; 1&#039;b0;<br \/>\n            tx_done     &lt;&#061; 1&#039;b0;<br \/>\n            crc_init    &lt;&#061; 1&#039;b0;<br \/>\n            crc_en      &lt;&#061; 1&#039;b0;<br \/>\n            crc_data    &lt;&#061; 8&#039;h00;<br \/>\n        end else begin<br \/>\n            tx_done  &lt;&#061; 1&#039;b0;<br \/>\n            crc_init &lt;&#061; 1&#039;b0;<br \/>\n            crc_en   &lt;&#061; 1&#039;b0;<br \/>\n            rd_en    &lt;&#061; 1&#039;b0;<\/p>\n<p>            case (state)<br \/>\n                S_IDLE: begin<br \/>\n                    gmii_tx_en &lt;&#061; 1&#039;b0;<br \/>\n                    gmii_tx_er &lt;&#061; 1&#039;b0;<br \/>\n                    gmii_txd   &lt;&#061; 8&#039;h00;<br \/>\n                    pre_cnt    &lt;&#061; 4&#039;d0;<br \/>\n                    byte_cnt   &lt;&#061; 11&#039;d0;<br \/>\n                    fcs_cnt    &lt;&#061; 2&#039;d0;<br \/>\n                    ifg_cnt    &lt;&#061; 8&#039;d0;<br \/>\n                    tx_busy    &lt;&#061; 1&#039;b0;<br \/>\n                    if (tx_req) begin<br \/>\n                        tx_busy  &lt;&#061; 1&#039;b1;<br \/>\n                        crc_init &lt;&#061; 1&#039;b1;   \/\/ \u8fdb\u5165\u524d\u5bfc\u7801\u65f6\u521d\u59cb\u5316 CRC<br \/>\n                    end<br \/>\n                end<\/p>\n<p>                S_PREAMBLE: begin<br \/>\n                    gmii_tx_en &lt;&#061; 1&#039;b1;<br \/>\n                    gmii_txd   &lt;&#061; 8&#039;h55;<br \/>\n                    if (pre_cnt &#061;&#061; 4&#039;d6)<br \/>\n                        pre_cnt &lt;&#061; 4&#039;d0;<br \/>\n                    else<br \/>\n                        pre_cnt &lt;&#061; pre_cnt &#043; 1&#039;b1;<br \/>\n                end<\/p>\n<p>                S_SFD: begin<br \/>\n                    gmii_tx_en &lt;&#061; 1&#039;b1;<br \/>\n                    gmii_txd   &lt;&#061; 8&#039;hD5;<br \/>\n                end<\/p>\n<p>                S_DATA: begin<br \/>\n                    gmii_tx_en &lt;&#061; 1&#039;b1;<br \/>\n                    gmii_txd   &lt;&#061; rd_data;<br \/>\n                    crc_en     &lt;&#061; 1&#039;b1;<br \/>\n                    crc_data   &lt;&#061; rd_data;<br \/>\n                    rd_en      &lt;&#061; 1&#039;b1;<br \/>\n                    rd_addr    &lt;&#061; byte_cnt;<br \/>\n                    if (byte_cnt &#061;&#061; frame_len &#8211; 1)<br \/>\n                        byte_cnt &lt;&#061; 11&#039;d0;<br \/>\n                    else<br \/>\n                        byte_cnt &lt;&#061; byte_cnt &#043; 1&#039;b1;<br \/>\n                end<\/p>\n<p>                S_FCS: begin<br \/>\n                    gmii_tx_en &lt;&#061; 1&#039;b1;<br \/>\n                    \/\/ \u9ad8\u5b57\u8282\u5148\u53d1<br \/>\n                    case (fcs_cnt)<br \/>\n                        2&#039;d0: gmii_txd &lt;&#061; crc_out[31:24];<br \/>\n                        2&#039;d1: gmii_txd &lt;&#061; crc_out[23:16];<br \/>\n                        2&#039;d2: gmii_txd &lt;&#061; crc_out[15:8];<br \/>\n                        2&#039;d3: gmii_txd &lt;&#061; crc_out[7:0];<br \/>\n                    endcase<br \/>\n                    fcs_cnt &lt;&#061; fcs_cnt &#043; 1&#039;b1;<br \/>\n                end<\/p>\n<p>                S_IFG: begin<br \/>\n                    gmii_tx_en &lt;&#061; 1&#039;b0;<br \/>\n                    gmii_txd   &lt;&#061; 8&#039;h00;<br \/>\n                    if (ifg_cnt &#061;&#061; 8&#039;d11) begin<br \/>\n                        ifg_cnt &lt;&#061; 8&#039;d0;<br \/>\n                        tx_busy &lt;&#061; 1&#039;b0;<br \/>\n                        tx_done &lt;&#061; 1&#039;b1;<br \/>\n                    end else begin<br \/>\n                        ifg_cnt &lt;&#061; ifg_cnt &#043; 1&#039;b1;<br \/>\n                    end<br \/>\n                end<br \/>\n            endcase<br \/>\n        end<br \/>\n    end<\/p>\n<p>endmodule<\/p>\n<h4>5.3 \u72b6\u6001\u673a\u8981\u70b9\u89e3\u6790<\/h4>\n<p>\u524d\u5bfc\u7801\u8ba1\u6570&#xff1a;pre_cnt \u4ece 0 \u5230 6&#xff0c;\u5171 7 \u4e2a\u5468\u671f&#xff0c;\u6bcf\u4e2a\u5468\u671f\u8f93\u51fa 0x55\u3002\u6ce8\u610f\u8fdb\u5165 S_PREAMBLE \u7684\u7b2c\u4e00\u4e2a\u5468\u671f\u5c31\u8981\u62c9\u9ad8 tx_en \u5e76\u8f93\u51fa\u7b2c\u4e00\u4e2a 0x55&#xff0c;\u4e0d\u80fd\u6709\u6c14\u6ce1\u3002<\/p>\n<p>SFD&#xff1a;\u5355\u72ec\u4e00\u4e2a\u72b6\u6001&#xff0c;\u8f93\u51fa 0xD5&#xff0c;tx_en \u4fdd\u6301\u9ad8\u3002<\/p>\n<p>\u6570\u636e\u6bb5&#xff1a;byte_cnt \u4ece 0 \u8ba1\u6570\u5230 frame_len &#8211; 1&#xff0c;frame_len &#061; tx_len &#043; 14\u3002\u8fd9\u91cc tx_len \u662f\u8d1f\u8f7d\u957f\u5ea6&#xff0c;14 \u662f DA&#043;SA&#043;Type\u3002\u6ce8\u610f rd_addr \u7684\u65f6\u5e8f&#xff1a;\u5f53\u524d\u5468\u671f\u7ed9\u51fa\u5730\u5740&#xff0c;\u4e0b\u4e00\u5468\u671f rd_data \u624d\u6709\u6548&#xff0c;\u6240\u4ee5 gmii_txd &lt;&#061; rd_data \u7528\u7684\u662f\u4e0a\u4e00\u5468\u671f\u5730\u5740\u5bf9\u5e94\u7684\u6570\u636e\u3002\u5982\u679c\u5e27\u7f13\u5b58\u662f\u540c\u6b65\u8bfb\u7684 BRAM&#xff0c;\u9700\u8981\u989d\u5916\u4e00\u4e2a\u5468\u671f\u7684\u5ef6\u8fdf\u5bf9\u9f50&#xff0c;\u5b9e\u9645\u5b9e\u73b0\u65f6\u8981\u628a tx_en \u4e5f\u5ef6\u8fdf\u4e00\u62cd&#xff0c;\u6216\u8005\u7528\u9884\u53d6&#xff08;prefetch&#xff09;\u65b9\u5f0f\u3002<\/p>\n<p>FCS&#xff1a;crc_out \u5728\u6700\u540e\u4e00\u4e2a\u6570\u636e\u5b57\u8282\u8f93\u5165\u540e\u7684\u4e0b\u4e00\u5468\u671f\u624d\u6709\u6548&#xff08;\u53d6\u51b3\u4e8e CRC \u6a21\u5757\u7684\u6d41\u6c34\u7ebf\u7ea7\u6570&#xff09;\u3002\u4e0a\u9762\u7684\u4ee3\u7801\u5047\u8bbe CRC \u6a21\u5757\u662f\u5355\u5468\u671f\u7ec4\u5408\u8f93\u51fa&#xff0c;\u5b9e\u9645\u7528 8 \u4f4d\u5e76\u884c CRC \u65f6\u901a\u5e38\u6709 1~2 \u7ea7\u6d41\u6c34&#xff0c;\u9700\u8981\u5728 S_DATA \u7ed3\u675f\u540e\u63d2\u5165\u7b49\u5f85\u5468\u671f&#xff0c;\u6216\u8005\u628a crc_out \u6253\u62cd\u5bf9\u9f50\u3002<\/p>\n<p>IFG&#xff1a;\u6807\u51c6\u8981\u6c42 96 bit time&#xff0c;\u5343\u5146\u4e0b 96ns &#061; 12 \u4e2a 125MHz \u5468\u671f\u3002\u4ee3\u7801\u91cc ifg_cnt \u4ece 0 \u5230 11&#xff0c;\u5171 12 \u4e2a\u5468\u671f&#xff0c;\u7b26\u5408\u8981\u6c42\u3002\u6ce8\u610f IFG \u671f\u95f4 tx_en \u5fc5\u987b\u4e3a\u4f4e\u3002<\/p>\n<h4>5.4 \u5e27\u7f13\u5b58\u7684\u7ec4\u7ec7<\/h4>\n<p>\u5e27\u7f13\u5b58\u5efa\u8bae\u7528\u53cc\u7aef\u53e3 BRAM&#xff0c;\u5199\u7aef\u53e3\u7ed9\u4e0a\u5c42\u5e94\u7528&#xff08;\u6bd4\u5982 ADC \u91c7\u96c6\u3001\u56fe\u50cf\u4f20\u611f\u5668&#xff09;&#xff0c;\u8bfb\u7aef\u53e3\u7ed9\u53d1\u9001\u72b6\u6001\u673a\u3002\u7f13\u5b58\u6df1\u5ea6\u81f3\u5c11 2048 \u5b57\u8282&#xff0c;\u652f\u6301\u6700\u5927\u5e27 1518 \u5b57\u8282\u3002<\/p>\n<p>\/\/ \u53cc\u7aef\u53e3 BRAM \u5e27\u7f13\u5b58<br \/>\nreg [7:0] frame_buf [0:2047];<\/p>\n<p>always &#064;(posedge clk) begin<br \/>\n    if (wr_en)<br \/>\n        frame_buf[wr_addr] &lt;&#061; wr_data;<br \/>\nend<\/p>\n<p>always &#064;(posedge clk) begin<br \/>\n    if (rd_en)<br \/>\n        rd_data &lt;&#061; frame_buf[rd_addr];<br \/>\nend<\/p>\n<p>\u6ce8\u610f\u8bfb\u5ef6\u8fdf\u4e00\u62cd&#xff0c;\u53d1\u9001\u72b6\u6001\u673a\u8981\u76f8\u5e94\u8c03\u6574\u3002<\/p>\n<h3>6. CRC-32 FCS \u7684\u5b8c\u6574\u5b9e\u73b0<\/h3>\n<h4>6.1 \u6807\u51c6\u5b9a\u4e49<\/h4>\n<p>\u4ee5\u592a\u7f51 FCS \u4f7f\u7528 CRC-32&#xff0c;\u53c2\u6570\u5982\u4e0b&#xff1a;<\/p>\n<table>\n<tr>\u53c2\u6570\u503c<\/tr>\n<tbody>\n<tr>\n<td>\u591a\u9879\u5f0f<\/td>\n<td>0x04C11DB7&#xff08;\u6b63\u5e38&#xff09;&#xff0c;0xEDB88320&#xff08;\u53cd\u5c04&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u4f4d\u5bbd<\/td>\n<td>32<\/td>\n<\/tr>\n<tr>\n<td>\u521d\u503c<\/td>\n<td>0xFFFFFFFF<\/td>\n<\/tr>\n<tr>\n<td>\u8f93\u5165\u53cd\u5c04<\/td>\n<td>\u662f&#xff08;LSB first&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u8f93\u51fa\u53cd\u5c04<\/td>\n<td>\u662f<\/td>\n<\/tr>\n<tr>\n<td>\u6700\u7ec8\u5f02\u6216<\/td>\n<td>0xFFFFFFFF<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u6807\u51c6\u5199\u6cd5&#xff08;\u53cd\u5c04\u5f62\u5f0f&#xff09;&#xff1a;<\/p>\n<p>crc &#061; 0xFFFFFFFF;<br \/>\nfor each byte b:<br \/>\n    crc &#061; crc ^ b;<br \/>\n    for i in 0..7:<br \/>\n        if (crc &amp; 1)<br \/>\n            crc &#061; (crc &gt;&gt; 1) ^ 0xEDB88320;<br \/>\n        else<br \/>\n            crc &#061; crc &gt;&gt; 1;<br \/>\ncrc &#061; crc ^ 0xFFFFFFFF;<\/p>\n<h4>6.2 \u9010\u4f4d\u4e32\u884c\u5b9e\u73b0<\/h4>\n<p>module crc32_bitwise (<br \/>\n    input  wire        clk,<br \/>\n    input  wire        rst_n,<br \/>\n    input  wire        init,<br \/>\n    input  wire        en,<br \/>\n    input  wire        bit_in,<br \/>\n    output reg  [31:0] crc<br \/>\n);<\/p>\n<p>    wire feedback &#061; crc[0] ^ bit_in;<\/p>\n<p>    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (!rst_n)<br \/>\n            crc &lt;&#061; 32&#039;hFFFFFFFF;<br \/>\n        else if (init)<br \/>\n            crc &lt;&#061; 32&#039;hFFFFFFFF;<br \/>\n        else if (en) begin<br \/>\n            crc[0]  &lt;&#061; crc[1];<br \/>\n            crc[1]  &lt;&#061; crc[2];<br \/>\n            crc[2]  &lt;&#061; crc[3];<br \/>\n            crc[3]  &lt;&#061; crc[4];<br \/>\n            crc[4]  &lt;&#061; crc[5] ^ feedback;<br \/>\n            crc[5]  &lt;&#061; crc[6];<br \/>\n            crc[6]  &lt;&#061; crc[7];<br \/>\n            crc[7]  &lt;&#061; crc[8];<br \/>\n            crc[8]  &lt;&#061; crc[9] ^ feedback;<br \/>\n            crc[9]  &lt;&#061; crc[10];<br \/>\n            crc[10] &lt;&#061; crc[11];<br \/>\n            crc[11] &lt;&#061; crc[12];<br \/>\n            crc[12] &lt;&#061; crc[13] ^ feedback;<br \/>\n            crc[13] &lt;&#061; crc[14];<br \/>\n            crc[14] &lt;&#061; crc[15];<br \/>\n            crc[15] &lt;&#061; crc[16];<br \/>\n            crc[16] &lt;&#061; crc[17] ^ feedback;<br \/>\n            crc[17] &lt;&#061; crc[18];<br \/>\n            crc[18] &lt;&#061; crc[19];<br \/>\n            crc[19] &lt;&#061; crc[20];<br \/>\n            crc[20] &lt;&#061; crc[21] ^ feedback;<br \/>\n            crc[21] &lt;&#061; crc[22];<br \/>\n            crc[22] &lt;&#061; crc[23];<br \/>\n            crc[23] &lt;&#061; crc[24];<br \/>\n            crc[24] &lt;&#061; crc[25] ^ feedback;<br \/>\n            crc[25] &lt;&#061; crc[26];<br \/>\n            crc[26] &lt;&#061; crc[27];<br \/>\n            crc[27] &lt;&#061; crc[28];<br \/>\n            crc[28] &lt;&#061; crc[29] ^ feedback;<br \/>\n            crc[29] &lt;&#061; crc[30];<br \/>\n            crc[30] &lt;&#061; crc[31];<br \/>\n            crc[31] &lt;&#061; feedback;<br \/>\n        end<br \/>\n    end<\/p>\n<p>endmodule<\/p>\n<p>\u8fd9\u4e2a\u5b9e\u73b0\u6bcf\u5468\u671f\u5904\u7406 1 bit&#xff0c;\u5343\u5146\u4e0b 8 \u4f4d\u6570\u636e\u9700\u8981 8 \u4e2a\u5468\u671f&#xff0c;\u592a\u6162\u3002\u5b9e\u9645\u8981\u7528 8 \u4f4d\u5e76\u884c\u3002<\/p>\n<h4>6.3 8 \u4f4d\u5e76\u884c\u5b9e\u73b0<\/h4>\n<p>8 \u4f4d\u5e76\u884c CRC \u7684\u63a8\u5bfc\u601d\u8def&#xff1a;\u628a 8 \u4e2a bit \u7684\u4e32\u884c\u8fed\u4ee3\u5c55\u5f00&#xff0c;\u5f97\u5230\u5f53\u524d CRC \u4e0e\u8f93\u5165\u5b57\u8282\u7684\u5f02\u6216\u7ec4\u5408\u3002\u6807\u51c6\u7ed3\u679c\u5982\u4e0b&#xff08;\u53cd\u5c04\u5f62\u5f0f&#xff0c;\u591a\u9879\u5f0f 0xEDB88320&#xff09;&#xff1a;<\/p>\n<p>module crc32_8bit (<br \/>\n    input  wire        clk,<br \/>\n    input  wire        rst_n,<br \/>\n    input  wire        init,<br \/>\n    input  wire        en,<br \/>\n    input  wire [7:0]  data,<br \/>\n    output reg  [31:0] crc<br \/>\n);<\/p>\n<p>    wire [31:0] c;<br \/>\n    assign c &#061; crc;<\/p>\n<p>    wire [7:0] d;<br \/>\n    assign d &#061; data;<\/p>\n<p>    \/\/ 8 \u4f4d\u5e76\u884c CRC-32&#xff08;\u53cd\u5c04&#xff0c;\u591a\u9879\u5f0f 0xEDB88320&#xff09;<br \/>\n    wire [31:0] crc_next;<br \/>\n    assign crc_next[0]  &#061; c[8]  ^ c[14] ^ c[20] ^ c[26] ^ c[30] ^ d[0] ^ d[6];<br \/>\n    assign crc_next[1]  &#061; c[9]  ^ c[15] ^ c[21] ^ c[27] ^ c[31] ^ d[1] ^ d[7];<br \/>\n    assign crc_next[2]  &#061; c[10] ^ c[16] ^ c[22] ^ c[28] ^ d[2];<br \/>\n    assign crc_next[3]  &#061; c[11] ^ c[17] ^ c[23] ^ c[29] ^ d[3];<br \/>\n    assign crc_next[4]  &#061; c[12] ^ c[18] ^ c[24] ^ c[30] ^ d[4];<br \/>\n    assign crc_next[5]  &#061; c[13] ^ c[19] ^ c[25] ^ c[31] ^ d[5];<br \/>\n    assign crc_next[6]  &#061; c[14] ^ c[20] ^ c[26] ^ d[6];<br \/>\n    assign crc_next[7]  &#061; c[15] ^ c[21] ^ c[27] ^ d[7];<br \/>\n    assign crc_next[8]  &#061; c[0]  ^ c[16] ^ c[22] ^ c[28] ^ d[0];<br \/>\n    assign crc_next[9]  &#061; c[1]  ^ c[17] ^ c[23] ^ c[29] ^ d[1];<br \/>\n    assign crc_next[10] &#061; c[2]  ^ c[18] ^ c[24] ^ c[30] ^ d[2];<br \/>\n    assign crc_next[11] &#061; c[3]  ^ c[19] ^ c[25] ^ c[31] ^ d[3];<br \/>\n    assign crc_next[12] &#061; c[4]  ^ c[20] ^ c[26] ^ d[4];<br \/>\n    assign crc_next[13] &#061; c[5]  ^ c[21] ^ c[27] ^ d[5];<br \/>\n    assign crc_next[14] &#061; c[6]  ^ c[22] ^ c[28] ^ d[6];<br \/>\n    assign crc_next[15] &#061; c[7]  ^ c[23] ^ c[29] ^ d[7];<br \/>\n    assign crc_next[16] &#061; c[8]  ^ c[24] ^ c[30] ^ d[0];<br \/>\n    assign crc_next[17] &#061; c[9]  ^ c[25] ^ c[31] ^ d[1];<br \/>\n    assign crc_next[18] &#061; c[10] ^ c[26] ^ d[2];<br \/>\n    assign crc_next[19] &#061; c[11] ^ c[27] ^ d[3];<br \/>\n    assign crc_next[20] &#061; c[12] ^ c[28] ^ d[4];<br \/>\n    assign crc_next[21] &#061; c[13] ^ c[29] ^ d[5];<br \/>\n    assign crc_next[22] &#061; c[14] ^ c[30] ^ d[6];<br \/>\n    assign crc_next[23] &#061; c[15] ^ c[31] ^ d[7];<br \/>\n    assign crc_next[24] &#061; c[16] ^ d[0];<br \/>\n    assign crc_next[25] &#061; c[17] ^ d[1];<br \/>\n    assign crc_next[26] &#061; c[18] ^ d[2];<br \/>\n    assign crc_next[27] &#061; c[19] ^ d[3];<br \/>\n    assign crc_next[28] &#061; c[20] ^ d[4];<br \/>\n    assign crc_next[29] &#061; c[21] ^ d[5];<br \/>\n    assign crc_next[30] &#061; c[22] ^ d[6];<br \/>\n    assign crc_next[31] &#061; c[23] ^ d[7];<\/p>\n<p>    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (!rst_n)<br \/>\n            crc &lt;&#061; 32&#039;hFFFFFFFF;<br \/>\n        else if (init)<br \/>\n            crc &lt;&#061; 32&#039;hFFFFFFFF;<br \/>\n        else if (en)<br \/>\n            crc &lt;&#061; crc_next;<br \/>\n    end<\/p>\n<p>endmodule<\/p>\n<h4>6.4 \u5e76\u884c CRC \u7684\u63a8\u5bfc\u65b9\u6cd5<\/h4>\n<p>\u4e0a\u9762\u90a3 32 \u884c\u5f02\u6216\u8868\u8fbe\u5f0f\u4e0d\u662f\u80cc\u51fa\u6765\u7684&#xff0c;\u53ef\u4ee5\u7528\u811a\u672c\u751f\u6210\u3002\u601d\u8def&#xff1a;<\/p>\n<li>\u628a 32 \u4f4d CRC \u5bc4\u5b58\u5668\u8bb0\u4e3a c[31:0]&#xff0c;\u8f93\u5165\u5b57\u8282\u8bb0\u4e3a d[7:0]&#xff1b;<\/li>\n<li>\u4e32\u884c\u7b97\u6cd5\u6bcf\u5904\u7406 1 bit&#xff0c;\u505a\u4e00\u6b21 feedback &#061; c[0] ^ bit&#xff0c;\u7136\u540e\u53f3\u79fb\u5e76\u6761\u4ef6\u5f02\u6216\u591a\u9879\u5f0f&#xff1b;<\/li>\n<li>\u8fde\u7eed\u505a 8 \u6b21&#xff0c;\u628a\u4e2d\u95f4\u53d8\u91cf\u5168\u90e8\u4ee3\u5165&#xff0c;\u6700\u7ec8\u5f97\u5230 c_next \u5173\u4e8e c \u548c d \u7684\u5f02\u6216\u8868\u8fbe\u5f0f&#xff1b;<\/li>\n<li>\u7528 Python \u811a\u672c\u7b26\u53f7\u5316\u5c55\u5f00&#xff0c;\u8f93\u51fa Verilog \u8d4b\u503c\u8bed\u53e5\u3002<\/li>\n<p><span class=\"token comment\"># \u751f\u6210 8 \u4f4d\u5e76\u884c CRC-32 \u8868\u8fbe\u5f0f<\/span><br \/>\nPOLY <span class=\"token operator\">&#061;<\/span> <span class=\"token number\">0xEDB88320<\/span><\/p>\n<p><span class=\"token keyword\">def<\/span> <span class=\"token function\">step<\/span><span class=\"token punctuation\">(<\/span>crc<span class=\"token punctuation\">,<\/span> bit<span class=\"token punctuation\">)<\/span><span class=\"token punctuation\">:<\/span><br \/>\n    fb <span class=\"token operator\">&#061;<\/span> <span class=\"token punctuation\">(<\/span>crc <span class=\"token operator\">&amp;<\/span> <span class=\"token number\">1<\/span><span class=\"token punctuation\">)<\/span> <span class=\"token operator\">^<\/span> bit<br \/>\n    crc <span class=\"token operator\">&gt;&gt;<\/span><span class=\"token operator\">&#061;<\/span> <span class=\"token number\">1<\/span><br \/>\n    <span class=\"token keyword\">if<\/span> fb<span class=\"token punctuation\">:<\/span><br \/>\n        crc <span class=\"token operator\">^<\/span><span class=\"token operator\">&#061;<\/span> POLY<br \/>\n    <span class=\"token keyword\">return<\/span> crc<\/p>\n<p><span class=\"token comment\"># \u7b26\u53f7\u5316&#xff1a;\u7528 32 \u4e2a\u53d8\u91cf\u8868\u793a crc&#xff0c;8 \u4e2a\u53d8\u91cf\u8868\u793a data<\/span><br \/>\n<span class=\"token comment\"># \u8fd9\u91cc\u7528\u6574\u6570\u4f4d\u63a9\u7801\u6a21\u62df&#xff0c;\u5b9e\u9645\u751f\u6210\u65f6\u7528\u7b26\u53f7\u8fd0\u7b97\u5e93<\/span><\/p>\n<p>\u5b9e\u9645\u5de5\u7a0b\u4e2d\u66f4\u5e38\u7528\u7684\u505a\u6cd5\u662f\u76f4\u63a5\u4f7f\u7528 Xilinx \u7684 crc32 IP \u6216\u8005\u5f00\u6e90\u7684 crc32_d8 \u6a21\u5757&#xff0c;\u4f46\u7406\u89e3\u63a8\u5bfc\u8fc7\u7a0b\u5bf9\u8c03\u8bd5\u81f3\u5173\u91cd\u8981\u2014\u2014\u5f53 FCS \u6821\u9a8c\u5931\u8d25\u65f6&#xff0c;\u4f60\u9700\u8981\u77e5\u9053\u662f\u521d\u503c\u9519\u4e86\u3001\u53cd\u5c04\u9519\u4e86\u8fd8\u662f\u5b57\u8282\u5e8f\u9519\u4e86\u3002<\/p>\n<h4>6.5 \u63a5\u6536\u7aef FCS \u6821\u9a8c<\/h4>\n<p>\u63a5\u6536\u7aef\u6709\u4e24\u79cd\u6821\u9a8c\u65b9\u5f0f&#xff1a;<\/p>\n<p>\u65b9\u5f0f\u4e00&#xff1a;\u91cd\u65b0\u8ba1\u7b97\u5e76\u6bd4\u8f83\u3002\u628a\u6536\u5230\u7684 DA \u5230 Payload \u91cd\u65b0\u7b97\u4e00\u904d CRC&#xff0c;\u7136\u540e\u4e0e\u6536\u5230\u7684 FCS \u6bd4\u8f83\u3002\u6ce8\u610f\u6536\u5230\u7684 FCS \u662f&#034;\u5df2\u7ecf\u8fc7\u6700\u7ec8\u5f02\u6216&#034;\u7684\u503c&#xff0c;\u6240\u4ee5\u6bd4\u8f83\u65f6\u8981\u5148\u628a\u8ba1\u7b97\u7ed3\u679c\u5f02\u6216 0xFFFFFFFF\u3002<\/p>\n<p>\u65b9\u5f0f\u4e8c&#xff1a;\u628a FCS \u4e5f\u5582\u8fdb CRC\u3002\u4ee5\u592a\u7f51 CRC \u6709\u4e00\u4e2a\u6027\u8d28&#xff1a;\u5982\u679c\u628a FCS \u7684 4 \u4e2a\u5b57\u8282\u4e5f\u6309\u987a\u5e8f\u5582\u8fdb CRC \u8ba1\u7b97\u5668&#xff08;\u521d\u503c 0xFFFFFFFF&#xff0c;\u4e0d\u53d6\u53cd&#xff09;&#xff0c;\u6700\u7ec8\u7ed3\u679c\u5e94\u8be5\u662f 0x2144DF1C&#xff08;\u8fd9\u662f\u4e00\u4e2a\u56fa\u5b9a\u5e38\u6570&#xff0c;\u79f0\u4e3a CRC-32 \u7684&#034;\u9b54\u672f\u503c&#034;&#xff09;\u3002\u8fd9\u79cd\u65b9\u5f0f\u4e0d\u9700\u8981\u989d\u5916\u6bd4\u8f83\u903b\u8f91&#xff0c;\u76f4\u63a5\u5224\u65ad CRC \u5bc4\u5b58\u5668\u662f\u5426\u7b49\u4e8e\u9b54\u672f\u503c\u5373\u53ef\u3002<\/p>\n<p>\u65b9\u5f0f\u4e8c\u5728\u786c\u4ef6\u91cc\u66f4\u5e38\u7528&#xff0c;\u56e0\u4e3a\u7701\u53bb\u4e86\u6bd4\u8f83\u5668\u548c\u989d\u5916\u7684\u5bc4\u5b58\u5668\u3002\u4f46\u8981\u6ce8\u610f&#xff1a;\u9b54\u672f\u503c 0x2144DF1C \u662f\u9488\u5bf9&#034;\u53cd\u5c04\u8f93\u5165\u3001\u53cd\u5c04\u8f93\u51fa\u3001\u521d\u503c\u5168 1\u3001\u6700\u7ec8\u5f02\u6216\u5168 1&#034;\u8fd9\u7ec4\u53c2\u6570\u7684&#xff0c;\u53c2\u6570\u4e0d\u540c\u9b54\u672f\u503c\u4e5f\u4e0d\u540c\u3002<\/p>\n<h3>7. \u63a5\u6536\u65b9\u5411 RTL \u8bbe\u8ba1<\/h3>\n<h4>7.1 \u6574\u4f53\u67b6\u6784<\/h4>\n<p>&#043;&#8212;&#8212;&#043;     &#043;&#8212;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#8212;&#8211;&#043;<br \/>\n| GMII | &#8211;&gt; | \u524d\u5bfc\u7801\u68c0\u6d4b  | &#8211;&gt; | \u5e27\u89e3\u6790   | &#8211;&gt; | \u5e27\u7f13\u5b58    |<br \/>\n| \u8f93\u5165 |     | SFD \u5bf9\u9f50    |     | CRC \u6821\u9a8c |     | &#043; \u72b6\u6001\u8f93\u51fa|<br \/>\n&#043;&#8212;&#8212;&#043;     &#043;&#8212;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#8212;-&#043;     &#043;&#8212;&#8212;&#8212;&#8211;&#043;<\/p>\n<p>\u63a5\u6536\u72b6\u6001\u673a\u8981\u5b8c\u6210&#xff1a;\u68c0\u6d4b\u524d\u5bfc\u7801\u3001\u8bc6\u522b SFD\u3001\u9010\u5b57\u8282\u63a5\u6536\u3001CRC \u6821\u9a8c\u3001\u957f\u5ea6\u68c0\u67e5\u3001\u8f93\u51fa\u5e27\u6709\u6548\u4fe1\u53f7\u3002<\/p>\n<h4>7.2 \u63a5\u6536\u72b6\u6001\u673a<\/h4>\n<p>module eth_rx (<br \/>\n    input  wire        clk,          \/\/ 125MHz&#xff08;rx_clk&#xff09;<br \/>\n    input  wire        rst_n,<\/p>\n<p>    \/\/ GMII \u8f93\u5165<br \/>\n    input  wire [7:0]  gmii_rxd,<br \/>\n    input  wire        gmii_rx_dv,<br \/>\n    input  wire        gmii_rx_er,<\/p>\n<p>    \/\/ \u5e27\u8f93\u51fa\u63a5\u53e3<br \/>\n    output reg         rx_valid,     \/\/ \u5e27\u6709\u6548&#xff08;CRC \u6b63\u786e\u3001\u957f\u5ea6\u5408\u6cd5&#xff09;<br \/>\n    output reg         rx_done,      \/\/ \u5e27\u63a5\u6536\u5b8c\u6210&#xff08;\u5355\u5468\u671f\u8109\u51b2&#xff09;<br \/>\n    output reg  [10:0] rx_len,       \/\/ \u5e27\u957f\u5ea6&#xff08;DA \u5230 FCS&#xff0c;\u542b FCS&#xff09;<br \/>\n    output reg  [47:0] rx_da,        \/\/ \u76ee\u7684 MAC<br \/>\n    output reg  [47:0] rx_sa,        \/\/ \u6e90 MAC<br \/>\n    output reg  [15:0] rx_type,      \/\/ \u7c7b\u578b\/\u957f\u5ea6<br \/>\n    output reg  [10:0] wr_addr,<br \/>\n    output reg  [7:0]  wr_data,<br \/>\n    output reg         wr_en,<\/p>\n<p>    \/\/ \u9519\u8bef\u7edf\u8ba1<br \/>\n    output reg         err_crc,<br \/>\n    output reg         err_len<br \/>\n);<\/p>\n<p>    localparam S_IDLE     &#061; 3&#039;d0;<br \/>\n    localparam S_PREAMBLE &#061; 3&#039;d1;<br \/>\n    localparam S_DATA     &#061; 3&#039;d2;<br \/>\n    localparam S_FCS      &#061; 3&#039;d3;<br \/>\n    localparam S_DONE     &#061; 3&#039;d4;<\/p>\n<p>    reg [2:0]  state;<br \/>\n    reg [3:0]  pre_cnt;<br \/>\n    reg [10:0] byte_cnt;<br \/>\n    reg [1:0]  fcs_cnt;<br \/>\n    reg [7:0]  fcs_buf [0:3];<br \/>\n    reg [7:0]  byte_idx;<\/p>\n<p>    \/\/ CRC \u6a21\u5757<br \/>\n    reg        crc_init;<br \/>\n    reg        crc_en;<br \/>\n    reg  [7:0] crc_data;<br \/>\n    wire [31:0] crc_out;<\/p>\n<p>    crc32_8bit u_crc (<br \/>\n        .clk   (clk),<br \/>\n        .rst_n (rst_n),<br \/>\n        .init  (crc_init),<br \/>\n        .en    (crc_en),<br \/>\n        .data  (crc_data),<br \/>\n        .crc   (crc_out)<br \/>\n    );<\/p>\n<p>    \/\/ \u524d\u5bfc\u7801\u68c0\u6d4b&#xff1a;\u8fde\u7eed\u6536\u5230 0x55<br \/>\n    wire pre_match &#061; (gmii_rxd &#061;&#061; 8&#039;h55);<br \/>\n    wire sfd_match &#061; (gmii_rxd &#061;&#061; 8&#039;hD5);<\/p>\n<p>    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (!rst_n) begin<br \/>\n            state     &lt;&#061; S_IDLE;<br \/>\n            pre_cnt   &lt;&#061; 4&#039;d0;<br \/>\n            byte_cnt  &lt;&#061; 11&#039;d0;<br \/>\n            fcs_cnt   &lt;&#061; 2&#039;d0;<br \/>\n            rx_valid  &lt;&#061; 1&#039;b0;<br \/>\n            rx_done   &lt;&#061; 1&#039;b0;<br \/>\n            rx_len    &lt;&#061; 11&#039;d0;<br \/>\n            rx_da     &lt;&#061; 48&#039;d0;<br \/>\n            rx_sa     &lt;&#061; 48&#039;d0;<br \/>\n            rx_type   &lt;&#061; 16&#039;d0;<br \/>\n            wr_addr   &lt;&#061; 11&#039;d0;<br \/>\n            wr_data   &lt;&#061; 8&#039;d0;<br \/>\n            wr_en     &lt;&#061; 1&#039;b0;<br \/>\n            crc_init  &lt;&#061; 1&#039;b0;<br \/>\n            crc_en    &lt;&#061; 1&#039;b0;<br \/>\n            crc_data  &lt;&#061; 8&#039;d0;<br \/>\n            err_crc   &lt;&#061; 1&#039;b0;<br \/>\n            err_len   &lt;&#061; 1&#039;b0;<br \/>\n        end else begin<br \/>\n            rx_done  &lt;&#061; 1&#039;b0;<br \/>\n            wr_en    &lt;&#061; 1&#039;b0;<br \/>\n            crc_init &lt;&#061; 1&#039;b0;<br \/>\n            crc_en   &lt;&#061; 1&#039;b0;<\/p>\n<p>            case (state)<br \/>\n                S_IDLE: begin<br \/>\n                    rx_valid &lt;&#061; 1&#039;b0;<br \/>\n                    pre_cnt  &lt;&#061; 4&#039;d0;<br \/>\n                    byte_cnt &lt;&#061; 11&#039;d0;<br \/>\n                    fcs_cnt  &lt;&#061; 2&#039;d0;<br \/>\n                    if (gmii_rx_dv &amp;&amp; pre_match) begin<br \/>\n                        state    &lt;&#061; S_PREAMBLE;<br \/>\n                        pre_cnt  &lt;&#061; 4&#039;d1;<br \/>\n                        crc_init &lt;&#061; 1&#039;b1;<br \/>\n                    end<br \/>\n                end<\/p>\n<p>                S_PREAMBLE: begin<br \/>\n                    if (!gmii_rx_dv) begin<br \/>\n                        state &lt;&#061; S_IDLE;   \/\/ \u524d\u5bfc\u7801\u4e2d\u65ad&#xff0c;\u4e22\u5f03<br \/>\n                    end else if (sfd_match) begin<br \/>\n                        state    &lt;&#061; S_DATA;<br \/>\n                        byte_cnt &lt;&#061; 11&#039;d0;<br \/>\n                    end else if (pre_match) begin<br \/>\n                        pre_cnt &lt;&#061; pre_cnt &#043; 1&#039;b1;<br \/>\n                    end else begin<br \/>\n                        state &lt;&#061; S_IDLE;   \/\/ \u975e\u6cd5\u524d\u5bfc\u7801<br \/>\n                    end<br \/>\n                end<\/p>\n<p>                S_DATA: begin<br \/>\n                    if (!gmii_rx_dv) begin<br \/>\n                        state &lt;&#061; S_IDLE;   \/\/ \u5e27\u4e2d\u65ad<br \/>\n                    end else begin<br \/>\n                        \/\/ \u5199\u5165\u5e27\u7f13\u5b58<br \/>\n                        wr_en   &lt;&#061; 1&#039;b1;<br \/>\n                        wr_addr &lt;&#061; byte_cnt;<br \/>\n                        wr_data &lt;&#061; gmii_rxd;<\/p>\n<p>                        \/\/ CRC \u8ba1\u7b97&#xff08;DA \u5230 Payload&#xff09;<br \/>\n                        crc_en   &lt;&#061; 1&#039;b1;<br \/>\n                        crc_data &lt;&#061; gmii_rxd;<\/p>\n<p>                        \/\/ \u63d0\u53d6 DA\/SA\/Type<br \/>\n                        case (byte_cnt)<br \/>\n                            11&#039;d0: rx_da[47:40] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d1: rx_da[39:32] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d2: rx_da[31:24] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d3: rx_da[23:16] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d4: rx_da[15:8]  &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d5: rx_da[7:0]   &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d6: rx_sa[47:40] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d7: rx_sa[39:32] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d8: rx_sa[31:24] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d9: rx_sa[23:16] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d10: rx_sa[15:8] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d11: rx_sa[7:0]  &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d12: rx_type[15:8] &lt;&#061; gmii_rxd;<br \/>\n                            11&#039;d13: rx_type[7:0]  &lt;&#061; gmii_rxd;<br \/>\n                            default: ;<br \/>\n                        endcase<\/p>\n<p>                        byte_cnt &lt;&#061; byte_cnt &#043; 1&#039;b1;<br \/>\n                    end<br \/>\n                end<\/p>\n<p>                S_FCS: begin<br \/>\n                    \/\/ \u63a5\u6536 4 \u5b57\u8282 FCS<br \/>\n                    fcs_buf[fcs_cnt] &lt;&#061; gmii_rxd;<br \/>\n                    if (fcs_cnt &#061;&#061; 2&#039;d3) begin<br \/>\n                        state &lt;&#061; S_DONE;<br \/>\n                    end else begin<br \/>\n                        fcs_cnt &lt;&#061; fcs_cnt &#043; 1&#039;b1;<br \/>\n                    end<br \/>\n                end<\/p>\n<p>                S_DONE: begin<br \/>\n                    \/\/ \u6821\u9a8c CRC<br \/>\n                    \/\/ \u65b9\u5f0f\u4e00&#xff1a;\u6bd4\u8f83 crc_out \u4e0e fcs_buf<br \/>\n                    \/\/ \u65b9\u5f0f\u4e8c&#xff1a;\u628a FCS \u5582\u8fdb CRC&#xff0c;\u5224\u65ad\u9b54\u672f\u503c<br \/>\n                    \/\/ \u8fd9\u91cc\u7528\u65b9\u5f0f\u4e00<br \/>\n                    if (crc_out &#061;&#061; {fcs_buf[0], fcs_buf[1], fcs_buf[2], fcs_buf[3]}) begin<br \/>\n                        rx_valid &lt;&#061; 1&#039;b1;<br \/>\n                        err_crc  &lt;&#061; 1&#039;b0;<br \/>\n                    end else begin<br \/>\n                        rx_valid &lt;&#061; 1&#039;b0;<br \/>\n                        err_crc  &lt;&#061; 1&#039;b1;<br \/>\n                    end<\/p>\n<p>                    \/\/ \u957f\u5ea6\u68c0\u67e5<br \/>\n                    rx_len &lt;&#061; byte_cnt &#043; 11&#039;d4;   \/\/ \u6570\u636e\u5b57\u8282 &#043; FCS<br \/>\n                    if (byte_cnt &#043; 11&#039;d4 &lt; 11&#039;d64) begin<br \/>\n                        err_len &lt;&#061; 1&#039;b1;<br \/>\n                        rx_valid &lt;&#061; 1&#039;b0;<br \/>\n                    end else begin<br \/>\n                        err_len &lt;&#061; 1&#039;b0;<br \/>\n                    end<\/p>\n<p>                    rx_done &lt;&#061; 1&#039;b1;<br \/>\n                    state   &lt;&#061; S_IDLE;<br \/>\n                end<br \/>\n            endcase<br \/>\n        end<br \/>\n    end<\/p>\n<p>endmodule<\/p>\n<h4>7.3 \u63a5\u6536\u72b6\u6001\u673a\u7684\u5173\u952e\u7ec6\u8282<\/h4>\n<p>\u524d\u5bfc\u7801\u68c0\u6d4b\u7684\u9c81\u68d2\u6027&#xff1a;\u5b9e\u9645\u94fe\u8def\u4e2d&#xff0c;\u524d\u5bfc\u7801\u53ef\u80fd\u56e0\u4e3a PHY \u7684\u65f6\u949f\u6062\u590d\u800c\u4e22\u5931\u524d\u51e0\u4e2a\u5b57\u8282\u3002\u6807\u51c6\u5141\u8bb8\u63a5\u6536\u7aef\u5728\u68c0\u6d4b\u5230 SFD \u4e4b\u524d\u7684\u4efb\u610f\u4f4d\u7f6e\u5f00\u59cb\u540c\u6b65&#xff0c;\u53ea\u8981\u770b\u5230 0xD5 \u5c31\u8ba4\u4e3a\u5e27\u5f00\u59cb\u3002\u4e0a\u9762\u7684\u4ee3\u7801\u8981\u6c42\u5148\u770b\u5230 0x55 \u518d\u770b\u5230 0xD5&#xff0c;\u5728\u5927\u591a\u6570\u573a\u666f\u4e0b\u591f\u7528&#xff0c;\u4f46\u66f4\u9c81\u68d2\u7684\u505a\u6cd5\u662f\u76f4\u63a5\u68c0\u6d4b 0xD5&#xff0c;\u6216\u8005\u7528\u79fb\u4f4d\u5bc4\u5b58\u5668\u68c0\u6d4b &#8230;10101011 \u7684\u4f4d\u6a21\u5f0f\u3002<\/p>\n<p>SFD \u4e0e\u6570\u636e\u7684\u5206\u754c&#xff1a;0xD5 \u662f SFD&#xff0c;\u4e0d\u5c5e\u4e8e\u5e27\u5185\u5bb9&#xff0c;\u4e0d\u53c2\u4e0e CRC \u8ba1\u7b97\u3002\u4ee3\u7801\u91cc\u5728 S_PREAMBLE \u72b6\u6001\u68c0\u6d4b\u5230 0xD5 \u540e\u76f4\u63a5\u8df3\u5230 S_DATA&#xff0c;0xD5 \u672c\u8eab\u4e0d\u5199\u5165\u7f13\u5b58\u4e5f\u4e0d\u5582 CRC&#xff0c;\u8fd9\u662f\u6b63\u786e\u7684\u3002<\/p>\n<p>FCS \u7684\u63a5\u6536&#xff1a;FCS \u7684 4 \u4e2a\u5b57\u8282\u8981\u63a5\u6536\u4f46\u4e0d\u53c2\u4e0e CRC \u8ba1\u7b97&#xff08;\u5982\u679c\u7528\u65b9\u5f0f\u4e00&#xff09;\u3002\u4ee3\u7801\u91cc S_FCS \u72b6\u6001\u53ea\u628a\u6570\u636e\u5b58\u5165 fcs_buf&#xff0c;\u4e0d\u4f7f\u80fd crc_en&#xff0c;\u6b63\u786e\u3002<\/p>\n<p>CRC \u6bd4\u8f83\u7684\u65f6\u5e8f&#xff1a;crc_out \u5728\u6700\u540e\u4e00\u4e2a\u6570\u636e\u5b57\u8282\u8f93\u5165\u540e\u7684\u4e0b\u4e00\u5468\u671f\u624d\u6709\u6548\u3002\u4ee3\u7801\u91cc\u5728 S_DONE \u72b6\u6001\u6bd4\u8f83&#xff0c;\u6b64\u65f6 crc_out \u5df2\u7ecf\u7a33\u5b9a\u3002\u4f46\u5982\u679c CRC \u6a21\u5757\u6709\u6d41\u6c34\u7ebf\u5ef6\u8fdf&#xff0c;\u9700\u8981\u5728 S_FCS \u548c S_DONE \u4e4b\u95f4\u63d2\u5165\u7b49\u5f85\u5468\u671f\u3002<\/p>\n<p>\u957f\u5ea6\u68c0\u67e5&#xff1a;\u6700\u5c0f\u5e27 64 \u5b57\u8282&#xff08;DA \u5230 FCS&#xff09;&#xff0c;\u4ee3\u7801\u91cc byte_cnt \u7edf\u8ba1\u7684\u662f DA \u5230 Payload \u7684\u5b57\u8282\u6570&#xff0c;\u52a0 4 \u662f FCS&#xff0c;\u6240\u4ee5 byte_cnt &#043; 4 \u5c31\u662f\u6574\u5e27\u957f\u5ea6\u3002\u5c0f\u4e8e 64 \u5224\u4e3a\u9519\u8bef\u3002<\/p>\n<h3>8. \u524d\u5bfc\u7801\u3001SFD \u4e0e IFG \u7684\u65f6\u5e8f\u7ec6\u8282<\/h3>\n<h4>8.1 \u524d\u5bfc\u7801\u7684\u7269\u7406\u610f\u4e49<\/h4>\n<p>\u524d\u5bfc\u7801 0x55 \u91cd\u590d 7 \u6b21&#xff0c;\u5728\u7269\u7406\u5c42\u4e0a\u662f 0101_0101 \u7684\u4ea4\u66ff\u6a21\u5f0f\u3002\u8fd9\u4e2a\u6a21\u5f0f\u7684\u4f5c\u7528&#xff1a;<\/p>\n<li>\u65f6\u949f\u6062\u590d&#xff1a;\u63a5\u6536\u7aef CDR \u9700\u8981\u8db3\u591f\u7684\u8df3\u53d8\u6cbf\u6765\u9501\u5b9a\u9891\u7387\u548c\u76f8\u4f4d\u3002\u5168 0 \u6216\u5168 1 \u6ca1\u6709\u8df3\u53d8&#xff0c;\u65e0\u6cd5\u6062\u590d\u65f6\u949f\u3002<\/li>\n<li>\u5747\u8861\u5668\u6536\u655b&#xff1a;\u81ea\u9002\u5e94\u5747\u8861\u5668\u9700\u8981\u8bad\u7ec3\u5e8f\u5217\u6765\u8c03\u6574\u62bd\u5934\u7cfb\u6570\u3002<\/li>\n<li>\u4fe1\u53f7\u68c0\u6d4b&#xff1a;\u63a5\u6536\u7aef\u901a\u8fc7\u68c0\u6d4b\u524d\u5bfc\u7801\u5224\u65ad\u94fe\u8def\u4e0a\u6709\u5e27\u5230\u6765\u3002<\/li>\n<p>\u5343\u5146\u4ee5\u592a\u7f51\u4f7f\u7528 4D-PAM5 \u7f16\u7801&#xff08;1000BASE-T&#xff09;&#xff0c;\u524d\u5bfc\u7801\u5728\u7269\u7406\u5c42\u88ab\u7f16\u7801\u6210\u7279\u5b9a\u7684\u7b26\u53f7\u5e8f\u5217&#xff0c;\u4f46 MAC \u5c42\u770b\u5230\u7684\u4ecd\u7136\u662f 0x55\u3002<\/p>\n<h4>8.2 SFD \u7684\u4f4d\u6a21\u5f0f<\/h4>\n<p>SFD &#061; 0xD5 &#061; 1101_0101\u3002\u6ce8\u610f\u4ee5\u592a\u7f51\u662f LSB first \u4f20\u8f93&#xff0c;\u6240\u4ee5\u7ebf\u4e0a\u5b9e\u9645\u7684\u4f4d\u987a\u5e8f\u662f 1010_1011\u3002\u524d\u5bfc\u7801 0x55 &#061; 0101_0101&#xff0c;LSB first \u662f 1010_1010\u3002\u6240\u4ee5\u524d\u5bfc\u7801 &#043; SFD \u7684\u7ebf\u4e0a\u4f4d\u6d41\u662f&#xff1a;<\/p>\n<p>1010_1010 1010_1010 &#8230; 1010_1011<\/p>\n<p>\u5373 7 \u7ec4 1010_1010 \u52a0\u4e0a\u6700\u540e\u7684 1010_1011\u3002\u63a5\u6536\u7aef\u68c0\u6d4b\u5230 1011 \u8fd9\u4e2a\u6a21\u5f0f&#xff08;\u76f8\u5bf9\u4e8e\u524d\u9762\u7684 1010 \u51fa\u73b0\u4e86\u8fde\u7eed\u4e24\u4e2a 1&#xff09;\u5c31\u77e5\u9053\u6570\u636e\u5f00\u59cb\u4e86\u3002<\/p>\n<h4>8.3 IFG \u7684\u4f5c\u7528\u4e0e\u5b9e\u73b0<\/h4>\n<p>IFG&#xff08;Inter-Frame Gap&#xff09;\u662f\u5e27\u4e0e\u5e27\u4e4b\u95f4\u7684\u6700\u5c0f\u95f4\u9694&#xff0c;\u6807\u51c6\u89c4\u5b9a 96 bit time\u3002\u5343\u5146\u4e0b 96ns &#061; 12 \u4e2a 125MHz \u5468\u671f\u3002<\/p>\n<p>IFG \u7684\u4f5c\u7528&#xff1a;<\/p>\n<li>\u7ed9\u63a5\u6536\u7aef\u65f6\u95f4\u5904\u7406\u4e0a\u4e00\u5e27&#xff08;CRC \u6821\u9a8c\u3001DMA \u642c\u8fd0&#xff09;&#xff1b;<\/li>\n<li>\u7ed9 PHY \u65f6\u95f4\u5207\u6362\u72b6\u6001&#xff1b;<\/li>\n<li>\u4fdd\u8bc1\u516c\u5e73\u6027&#xff0c;\u9632\u6b62\u67d0\u4e2a\u8282\u70b9\u72ec\u5360\u94fe\u8def\u3002<\/li>\n<p>\u5b9e\u73b0\u4e0a&#xff0c;\u53d1\u9001\u72b6\u6001\u673a\u5728 S_IFG \u72b6\u6001\u4fdd\u6301 tx_en \u4e3a\u4f4e&#xff0c;\u8ba1\u6570 12 \u4e2a\u5468\u671f\u3002\u6ce8\u610f IFG \u662f\u4ece\u4e0a\u4e00\u5e27\u7684\u6700\u540e\u4e00\u4e2a\u5b57\u8282&#xff08;FCS \u6700\u540e\u4e00\u5b57\u8282&#xff09;\u7ed3\u675f\u5230\u4e0b\u4e00\u5e27\u524d\u5bfc\u7801\u7b2c\u4e00\u4e2a\u5b57\u8282\u5f00\u59cb\u7684\u65f6\u95f4&#xff0c;\u6240\u4ee5\u8ba1\u6570\u8981\u4ece tx_en \u62c9\u4f4e\u7684\u90a3\u4e00\u62cd\u5f00\u59cb\u3002<\/p>\n<h4>8.4 \u80cc\u9760\u80cc\u5e27<\/h4>\n<p>\u80cc\u9760\u80cc\u5e27\u662f\u6307\u8fde\u7eed\u53d1\u9001\u591a\u4e2a\u5e27&#xff0c;\u5e27\u95f4\u53ea\u6709\u6700\u5c0f IFG\u3002\u5343\u5146\u4e0b\u7406\u8bba\u6700\u5927\u5e27\u901f\u7387&#xff1a;<\/p>\n<ul>\n<li>\u6700\u5c0f\u5e27 64 \u5b57\u8282 &#043; \u524d\u5bfc\u7801 8 \u5b57\u8282 &#043; IFG 12 \u5b57\u8282 &#061; 84 \u5b57\u8282 &#061; 672 bit&#xff1b;<\/li>\n<li>672 bit \/ 1Gbps &#061; 672ns&#xff1b;<\/li>\n<li>\u5e27\u901f\u7387 &#061; 1 \/ 672ns \u2248 1.488 Mpps\u3002<\/li>\n<\/ul>\n<p>\u5982\u679c\u53d1\u9001 1518 \u5b57\u8282\u7684\u5927\u5e27&#xff1a;<\/p>\n<ul>\n<li>1518 &#043; 8 &#043; 12 &#061; 1538 \u5b57\u8282 &#061; 12304 bit&#xff1b;<\/li>\n<li>12304 \/ 1Gbps &#061; 12.304us&#xff1b;<\/li>\n<li>\u5e27\u901f\u7387 \u2248 81.3 Kpps\u3002<\/li>\n<\/ul>\n<p>\u8fd9\u4e24\u4e2a\u6570\u5b57\u5728\u505a\u6d41\u91cf\u6d4b\u8bd5\u65f6\u662f\u57fa\u51c6\u3002<\/p>\n<h3>9. \u6700\u5c0f\u5e27\u586b\u5145\u4e0e\u957f\u5ea6\u5904\u7406<\/h3>\n<h4>9.1 \u4e3a\u4ec0\u4e48\u9700\u8981\u586b\u5145<\/h4>\n<p>\u4ee5\u592a\u7f51\u6700\u65e9\u4f7f\u7528 CSMA\/CD&#xff08;\u8f7d\u6ce2\u76d1\u542c\u591a\u8def\u8bbf\u95ee\/\u51b2\u7a81\u68c0\u6d4b&#xff09;&#xff0c;\u8981\u6c42\u53d1\u9001\u7aef\u5728\u53d1\u9001\u8fc7\u7a0b\u4e2d\u80fd\u68c0\u6d4b\u5230\u51b2\u7a81\u3002\u4e3a\u4e86\u4fdd\u8bc1\u51b2\u7a81\u4fe1\u53f7\u80fd\u4f20\u56de\u53d1\u9001\u7aef&#xff0c;\u5e27\u5fc5\u987b\u8db3\u591f\u957f&#xff1a;<\/p>\n<ul>\n<li>\u6700\u5927\u7f51\u7edc\u76f4\u5f84 2500m&#xff08;5 \u6bb5\u4e2d\u7ee7&#xff09;&#xff1b;<\/li>\n<li>\u5f80\u8fd4\u4f20\u64ad\u5ef6\u8fdf\u7ea6 51.2us&#xff1b;<\/li>\n<li>\u5343\u5146\u4e0b 51.2us \u00d7 1Gbps &#061; 51200 bit &#061; 6400 \u5b57\u8282&#xff1f;\u4e0d\u5bf9&#xff0c;\u8fd9\u662f\u767e\u5146\u7684\u8ba1\u7b97\u3002<\/li>\n<\/ul>\n<p>\u5b9e\u9645\u5343\u5146\u7684\u69fd\u65f6\u95f4&#xff08;slot time&#xff09;\u662f 512 \u5b57\u8282\u65f6\u95f4&#xff08;4096 bit time&#xff09;&#xff0c;\u4f46\u56e0\u4e3a\u5343\u5146\u4f7f\u7528\u8f7d\u6ce2\u6269\u5c55&#xff08;carrier extension&#xff09;&#xff0c;\u6700\u5c0f\u5e27\u4ecd\u7136\u662f 64 \u5b57\u8282\u3002\u5bf9\u4e8e\u5c0f\u4e8e 64 \u5b57\u8282\u7684\u5e27&#xff0c;MAC \u5c42\u8981\u586b\u5145\u5230 64 \u5b57\u8282\u3002<\/p>\n<h4>9.2 \u586b\u5145\u7684\u5b9e\u73b0<\/h4>\n<p>\u586b\u5145\u53d1\u751f\u5728 Payload \u4e4b\u540e\u3001FCS \u4e4b\u524d\u3002\u586b\u5145\u5b57\u8282\u5185\u5bb9\u4efb\u610f&#xff08;\u901a\u5e38\u586b 0&#xff09;&#xff0c;\u63a5\u6536\u7aef\u6839\u636e Type\/Length \u5b57\u6bb5\u5224\u65ad\u771f\u5b9e\u8d1f\u8f7d\u957f\u5ea6\u3002<\/p>\n<p>\/\/ \u53d1\u9001\u65f6\u8ba1\u7b97\u5b9e\u9645\u53d1\u9001\u957f\u5ea6<br \/>\nwire [10:0] payload_len_padded &#061; (tx_len &lt; 11&#039;d46) ? 11&#039;d46 : tx_len;<br \/>\nwire [10:0] frame_len &#061; payload_len_padded &#043; 11&#039;d14;<\/p>\n<p>\u5982\u679c tx_len &lt; 46&#xff0c;\u53d1\u9001\u72b6\u6001\u673a\u5728 Payload \u7ed3\u675f\u540e\u7ee7\u7eed\u8f93\u51fa 0 \u76f4\u5230 46 \u5b57\u8282&#xff0c;\u7136\u540e\u8ba1\u7b97 FCS\u3002\u6ce8\u610f FCS \u8981\u8986\u76d6\u586b\u5145\u5b57\u8282\u3002<\/p>\n<h4>9.3 \u63a5\u6536\u7aef\u7684\u957f\u5ea6\u5904\u7406<\/h4>\n<p>\u63a5\u6536\u7aef\u6536\u5230\u5e27\u540e&#xff0c;\u6839\u636e Type\/Length \u5b57\u6bb5\u5224\u65ad&#xff1a;<\/p>\n<ul>\n<li>\u5982\u679c\u5b57\u6bb5\u503c \u2265 0x0600&#xff0c;\u662f EtherType&#xff0c;\u8d1f\u8f7d\u957f\u5ea6 &#061; \u5e27\u957f &#8211; 14 &#8211; 4&#xff1b;<\/li>\n<li>\u5982\u679c\u5b57\u6bb5\u503c \u2264 0x05DC&#xff0c;\u662f\u957f\u5ea6\u5b57\u6bb5&#xff0c;\u8d1f\u8f7d\u957f\u5ea6 &#061; \u8be5\u503c&#xff0c;\u5269\u4f59\u7684\u662f\u586b\u5145\u3002<\/li>\n<\/ul>\n<p>\u5bf9\u4e8e EtherType \u5e27&#xff0c;\u4e0a\u5c42\u534f\u8bae&#xff08;\u5982 IP&#xff09;\u81ea\u5df1\u77e5\u9053\u771f\u5b9e\u957f\u5ea6&#xff08;IP \u5934\u91cc\u6709 Total Length&#xff09;&#xff0c;\u6240\u4ee5\u586b\u5145\u5b57\u8282\u4e0d\u5f71\u54cd\u89e3\u6790\u3002<\/p>\n<h3>10. VLAN \u6807\u7b7e\u4e0e\u6269\u5c55\u5e27\u683c\u5f0f<\/h3>\n<h4>10.1 802.1Q VLAN Tag<\/h4>\n<p>VLAN Tag \u63d2\u5165\u5728 SA \u548c Type \u4e4b\u95f4&#xff0c;\u5171 4 \u5b57\u8282&#xff1a;<\/p>\n<p>&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#043;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#043;&#8212;&#8211;&#043;<br \/>\n|   DA   |   SA   | TPID | TCI |  Type  | Payload | FCS |<br \/>\n| 6 Byte | 6 Byte |2Byte |2Byte| 2 Byte |   &#8230;   |4Byte|<br \/>\n&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#8212;&#8212;&#043;&#8212;&#8211;&#043;&#8212;&#8212;&#8211;&#043;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#061;&#043;&#8212;&#8211;&#043;<\/p>\n<ul>\n<li>TPID&#xff1a;Tag Protocol Identifier&#xff0c;\u56fa\u5b9a 0x8100&#xff1b;<\/li>\n<li>TCI&#xff1a;Tag Control Information&#xff0c;16 \u4f4d&#xff0c;\u5305\u542b&#xff1a;\n<ul>\n<li>PCP&#xff08;3 \u4f4d&#xff09;&#xff1a;\u4f18\u5148\u7ea7 0~7&#xff1b;<\/li>\n<li>DEI&#xff08;1 \u4f4d&#xff09;&#xff1a;\u4e22\u5f03 eligible \u6307\u793a&#xff1b;<\/li>\n<li>VID&#xff08;12 \u4f4d&#xff09;&#xff1a;VLAN ID&#xff0c;0~4095\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>\u5e26 VLAN Tag \u7684\u5e27\u6700\u5927\u957f\u5ea6 1522 \u5b57\u8282&#xff08;1518 &#043; 4&#xff09;\u3002<\/p>\n<h4>10.2 QinQ \u53cc\u6807\u7b7e<\/h4>\n<p>QinQ&#xff08;802.1ad&#xff09;\u5728 VLAN Tag \u5916\u9762\u518d\u5957\u4e00\u5c42&#xff1a;<\/p>\n<p>DA | SA | TPID&#061;0x88A8 | TCI | TPID&#061;0x8100 | TCI | Type | Payload | FCS<\/p>\n<p>\u5916\u5c42 TPID \u662f 0x88A8&#xff0c;\u5185\u5c42\u662f 0x8100\u3002\u6700\u5927\u5e27\u957f 1526 \u5b57\u8282\u3002<\/p>\n<h4>10.3 FPGA \u4e2d\u7684 VLAN \u5904\u7406<\/h4>\n<p>\u5982\u679c FPGA \u53ea\u505a\u900f\u4f20&#xff0c;\u4e0d\u9700\u8981\u89e3\u6790 VLAN&#xff0c;\u76f4\u63a5\u628a\u6574\u4e2a\u5e27\u5f53\u8d1f\u8f7d\u5904\u7406\u5373\u53ef\u3002\u5982\u679c\u9700\u8981\u8bc6\u522b VLAN&#xff0c;\u8981\u5728 Type \u5b57\u6bb5\u4f4d\u7f6e\u5224\u65ad\u662f\u5426\u4e3a 0x8100 \u6216 0x88A8&#xff0c;\u5982\u679c\u662f\u5219\u8df3\u8fc7 4 \u5b57\u8282\u7ee7\u7eed\u8bfb Type\u3002<\/p>\n<p>\/\/ \u7b80\u5316\u7684 VLAN \u8bc6\u522b<br \/>\nreg [15:0] type_field;<br \/>\nreg        is_vlan;<br \/>\nreg [15:0] vlan_id;<\/p>\n<p>always &#064;(posedge clk) begin<br \/>\n    if (byte_cnt &#061;&#061; 11&#039;d12)<br \/>\n        type_field[15:8] &lt;&#061; gmii_rxd;<br \/>\n    if (byte_cnt &#061;&#061; 11&#039;d13) begin<br \/>\n        type_field[7:0] &lt;&#061; gmii_rxd;<br \/>\n        is_vlan &lt;&#061; (type_field[15:8] &#061;&#061; 8&#039;h81) &amp;&amp; (gmii_rxd &#061;&#061; 8&#039;h00);<br \/>\n    end<br \/>\nend<\/p>\n<h3>11. \u5b8c\u6574\u9876\u5c42\u96c6\u6210\u4e0e\u4eff\u771f<\/h3>\n<h4>11.1 \u9876\u5c42\u6a21\u5757<\/h4>\n<p>module eth_top (<br \/>\n    input  wire        clk_125m,<br \/>\n    input  wire        rst_n,<\/p>\n<p>    \/\/ \u7528\u6237\u53d1\u9001\u63a5\u53e3<br \/>\n    input  wire        user_tx_req,<br \/>\n    input  wire [15:0] user_tx_len,<br \/>\n    output wire        user_tx_busy,<br \/>\n    output wire        user_tx_done,<\/p>\n<p>    \/\/ \u7528\u6237\u63a5\u6536\u63a5\u53e3<br \/>\n    output wire        user_rx_valid,<br \/>\n    output wire        user_rx_done,<br \/>\n    output wire [10:0] user_rx_len,<br \/>\n    output wire [47:0] user_rx_da,<br \/>\n    output wire [47:0] user_rx_sa,<br \/>\n    output wire [15:0] user_rx_type,<\/p>\n<p>    \/\/ GMII<br \/>\n    output wire [7:0]  gmii_txd,<br \/>\n    output wire        gmii_tx_en,<br \/>\n    output wire        gmii_tx_er,<br \/>\n    input  wire [7:0]  gmii_rxd,<br \/>\n    input  wire        gmii_rx_dv,<br \/>\n    input  wire        gmii_rx_er<br \/>\n);<\/p>\n<p>    \/\/ \u53d1\u9001\u5e27\u7f13\u5b58<br \/>\n    wire [10:0] tx_rd_addr;<br \/>\n    wire [7:0]  tx_rd_data;<br \/>\n    wire        tx_rd_en;<\/p>\n<p>    \/\/ \u63a5\u6536\u5e27\u7f13\u5b58<br \/>\n    wire [10:0] rx_wr_addr;<br \/>\n    wire [7:0]  rx_wr_data;<br \/>\n    wire        rx_wr_en;<\/p>\n<p>    eth_tx u_tx (<br \/>\n        .clk        (clk_125m),<br \/>\n        .rst_n      (rst_n),<br \/>\n        .tx_req     (user_tx_req),<br \/>\n        .tx_len     (user_tx_len),<br \/>\n        .tx_busy    (user_tx_busy),<br \/>\n        .tx_done    (user_tx_done),<br \/>\n        .rd_addr    (tx_rd_addr),<br \/>\n        .rd_data    (tx_rd_data),<br \/>\n        .rd_en      (tx_rd_en),<br \/>\n        .gmii_txd   (gmii_txd),<br \/>\n        .gmii_tx_en (gmii_tx_en),<br \/>\n        .gmii_tx_er (gmii_tx_er)<br \/>\n    );<br \/>\n\u5982\u679c\u9700\u8981\u7cfb\u7edf\u5b66\u4e60FPGA&#xff0c;\u8fd9\u91cc\u6709\u4e00\u4efd\u6574\u7406\u7684FPGA\u6c47\u603b\u8bfe\u7a0b\u8d44\u6599&#xff0c;\u5305\u542bBD\u6559\u7a0b\u3001Vivado\u6559\u7a0b\u3001IP \u6838\u6559\u7a0b\u7b49&#xff0c;\u6709\u9700\u8981\u7684\u670b\u53cb\u53ef\u4ee5\u4fdd\u5b58&#xff1a;\u94fe\u63a5: https:\/\/pan.baidu.com\/s\/1pIFS8GEYu_jH1np4ZLG2Kw?pwd&#061;wbbw \u63d0\u53d6\u7801: wbbw \u6574\u7406\u4e0d\u6613&#xff0c;\u5c3d\u5feb\u4fdd\u5b58<br \/>\n    eth_rx u_rx (<br \/>\n        .clk        (clk_125m),<br \/>\n        .rst_n      (rst_n),<br \/>\n        .gmii_rxd   (gmii_rxd),<br \/>\n        .gmii_rx_dv (gmii_rx_dv),<br \/>\n        .gmii_rx_er (gmii_rx_er),<br \/>\n        .rx_valid   (user_rx_valid),<br \/>\n        .rx_done    (user_rx_done),<br \/>\n        .rx_len     (user_rx_len),<br \/>\n        .rx_da      (user_rx_da),<br \/>\n        .rx_sa      (user_rx_sa),<br \/>\n        .rx_type    (user_rx_type),<br \/>\n        .wr_addr    (rx_wr_addr),<br \/>\n        .wr_data    (rx_wr_data),<br \/>\n        .wr_en      (rx_wr_en),<br \/>\n        .err_crc    (),<br \/>\n        .err_len    ()<br \/>\n    );<\/p>\n<p>endmodule<\/p>\n<h4>11.2 \u4eff\u771f\u6d4b\u8bd5\u5e73\u53f0<\/h4>\n<p>&#096;timescale 1ns \/ 1ps<\/p>\n<p>module tb_eth;<\/p>\n<p>    reg         clk;<br \/>\n    reg         rst_n;<br \/>\n    reg         tx_req;<br \/>\n    reg  [15:0] tx_len;<br \/>\n    wire        tx_busy;<br \/>\n    wire        tx_done;<\/p>\n<p>    wire [7:0]  gmii_txd;<br \/>\n    wire        gmii_tx_en;<br \/>\n    wire        gmii_tx_er;<\/p>\n<p>    \/\/ \u73af\u56de&#xff1a;\u53d1\u9001\u76f4\u63a5\u63a5\u63a5\u6536<br \/>\n    wire [7:0]  gmii_rxd   &#061; gmii_txd;<br \/>\n    wire        gmii_rx_dv &#061; gmii_tx_en;<br \/>\n    wire        gmii_rx_er &#061; gmii_tx_er;<\/p>\n<p>    wire        rx_valid;<br \/>\n    wire        rx_done;<br \/>\n    wire [10:0] rx_len;<br \/>\n    wire [47:0] rx_da;<br \/>\n    wire [47:0] rx_sa;<br \/>\n    wire [15:0] rx_type;<\/p>\n<p>    eth_top u_dut (<br \/>\n        .clk_125m    (clk),<br \/>\n        .rst_n       (rst_n),<br \/>\n        .user_tx_req (tx_req),<br \/>\n        .user_tx_len (tx_len),<br \/>\n        .user_tx_busy(tx_busy),<br \/>\n        .user_tx_done(tx_done),<br \/>\n        .user_rx_valid(rx_valid),<br \/>\n        .user_rx_done (rx_done),<br \/>\n        .user_rx_len  (rx_len),<br \/>\n        .user_rx_da   (rx_da),<br \/>\n        .user_rx_sa   (rx_sa),<br \/>\n        .user_rx_type (rx_type),<br \/>\n        .gmii_txd    (gmii_txd),<br \/>\n        .gmii_tx_en  (gmii_tx_en),<br \/>\n        .gmii_tx_er  (gmii_tx_er),<br \/>\n        .gmii_rxd    (gmii_rxd),<br \/>\n        .gmii_rx_dv  (gmii_rx_dv),<br \/>\n        .gmii_rx_er  (gmii_rx_er)<br \/>\n    );<\/p>\n<p>    \/\/ 125MHz \u65f6\u949f<br \/>\n    initial clk &#061; 0;<br \/>\n    always #4 clk &#061; ~clk;   \/\/ 8ns \u5468\u671f &#061; 125MHz<\/p>\n<p>    initial begin<br \/>\n        rst_n  &#061; 0;<br \/>\n        tx_req &#061; 0;<br \/>\n        tx_len &#061; 0;<br \/>\n        #100;<br \/>\n        rst_n &#061; 1;<br \/>\n        #100;<\/p>\n<p>        \/\/ \u53d1\u9001\u4e00\u5e27 64 \u5b57\u8282\u8d1f\u8f7d<br \/>\n        &#064;(posedge clk);<br \/>\n        tx_req &lt;&#061; 1;<br \/>\n        tx_len &lt;&#061; 16&#039;d64;<br \/>\n        &#064;(posedge clk);<br \/>\n        tx_req &lt;&#061; 0;<\/p>\n<p>        \/\/ \u7b49\u5f85\u53d1\u9001\u5b8c\u6210<br \/>\n        wait (tx_done);<br \/>\n        #1000;<\/p>\n<p>        \/\/ \u68c0\u67e5\u63a5\u6536\u7ed3\u679c<br \/>\n        if (rx_valid &amp;&amp; rx_len &#061;&#061; 11&#039;d82)   \/\/ 64 &#043; 14 &#043; 4<br \/>\n            $display(&#034;PASS: frame received, len&#061;%0d&#034;, rx_len);<br \/>\n        else<br \/>\n            $display(&#034;FAIL: rx_valid&#061;%b, len&#061;%0d&#034;, rx_valid, rx_len);<\/p>\n<p>        $finish;<br \/>\n    end<\/p>\n<p>endmodule<\/p>\n<h4>11.3 \u4eff\u771f\u8981\u70b9<\/h4>\n<p>\u73af\u56de\u6d4b\u8bd5&#xff1a;\u628a gmii_txd \u76f4\u63a5\u63a5\u5230 gmii_rxd&#xff0c;gmii_tx_en \u63a5\u5230 gmii_rx_dv&#xff0c;\u53ef\u4ee5\u9a8c\u8bc1\u6536\u53d1\u72b6\u6001\u673a\u7684\u914d\u5408\u3002\u6ce8\u610f\u5b9e\u9645\u4e2d\u63a5\u6536\u7aef\u6709\u5ef6\u8fdf&#xff0c;\u73af\u56de\u65f6\u63a5\u6536\u72b6\u6001\u673a\u4f1a\u5728\u53d1\u9001\u7684\u540c\u65f6\u542f\u52a8&#xff0c;\u9700\u8981\u786e\u8ba4\u524d\u5bfc\u7801\u68c0\u6d4b\u903b\u8f91\u80fd\u6b63\u786e\u5904\u7406\u3002<\/p>\n<p>CRC \u9a8c\u8bc1&#xff1a;\u7528\u4e00\u4e2a\u5df2\u77e5\u7684\u5e27&#xff08;\u6bd4\u5982 Wireshark \u6293\u5230\u7684\u771f\u5b9e\u5e27&#xff09;\u4f5c\u4e3a\u8f93\u5165&#xff0c;\u68c0\u67e5\u8ba1\u7b97\u51fa\u7684 FCS \u662f\u5426\u4e0e\u6293\u5305\u4e00\u81f4\u3002\u8fd9\u662f\u9a8c\u8bc1 CRC \u5b9e\u73b0\u6700\u76f4\u63a5\u7684\u65b9\u6cd5\u3002<\/p>\n<p>\u8fb9\u754c\u6d4b\u8bd5&#xff1a;\u5206\u522b\u6d4b\u8bd5 46 \u5b57\u8282&#xff08;\u6700\u5c0f\u8d1f\u8f7d&#xff09;\u30011500 \u5b57\u8282&#xff08;\u6700\u5927\u8d1f\u8f7d&#xff09;\u30011518 \u5b57\u8282&#xff08;\u6700\u5927\u5e27&#xff09;\u4e09\u79cd\u60c5\u51b5\u3002<\/p>\n<h3>12. \u5e38\u89c1\u9519\u8bef\u6e05\u5355<\/h3>\n<h4>12.1 \u524d\u5bfc\u7801\u9519\u8bef<\/h4>\n<ul>\n<li>\u9519\u8bef&#xff1a;\u524d\u5bfc\u7801\u53ea\u53d1\u4e86 6 \u4e2a 0x55\u3002\u540e\u679c&#xff1a;\u90e8\u5206 PHY \u65e0\u6cd5\u9501\u5b9a&#xff0c;\u5e27\u4e22\u5931\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;\u524d\u5bfc\u7801\u7528\u4e86 0xAA\u3002\u540e\u679c&#xff1a;\u4f4d\u6a21\u5f0f\u53cd\u4e86&#xff0c;\u63a5\u6536\u7aef\u68c0\u6d4b\u4e0d\u5230\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;SFD \u7528\u4e86 0xD5 \u4f46\u53d1\u9001\u65f6 LSB\/MSB \u641e\u53cd&#xff0c;\u53d8\u6210 0xAB\u3002\u540e\u679c&#xff1a;\u63a5\u6536\u7aef\u8ba4\u4e3a\u524d\u5bfc\u7801\u8fd8\u6ca1\u7ed3\u675f\u3002<\/li>\n<\/ul>\n<h4>12.2 \u5b57\u8282\u5e8f\u9519\u8bef<\/h4>\n<ul>\n<li>\u9519\u8bef&#xff1a;MAC \u5730\u5740\u6309\u5c0f\u7aef\u53d1\u9001&#xff0c;00:1A:2B:3C:4D:5E \u53d1\u6210 5E:4D:3C:2B:1A:00\u3002\u540e\u679c&#xff1a;\u4ea4\u6362\u673a\u5b66\u4e0d\u5230\u6b63\u786e MAC&#xff0c;\u5e27\u88ab\u4e22\u5f03\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;EtherType 0x0800 \u53d1\u6210 0x0008\u3002\u540e\u679c&#xff1a;\u4e0a\u5c42\u534f\u8bae\u6808\u8bc6\u522b\u4e0d\u4e86 IP \u5305\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;FCS \u4f4e\u5b57\u8282\u5148\u53d1\u3002\u540e\u679c&#xff1a;\u63a5\u6536\u7aef CRC \u6821\u9a8c\u5931\u8d25&#xff0c;\u5e27\u88ab\u4e22\u5f03\u3002<\/li>\n<\/ul>\n<h4>12.3 CRC \u9519\u8bef<\/h4>\n<ul>\n<li>\u9519\u8bef&#xff1a;\u521d\u503c\u7528\u4e86 0 \u800c\u4e0d\u662f 0xFFFFFFFF\u3002\u540e\u679c&#xff1a;FCS \u5168\u9519\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;\u5fd8\u8bb0\u6700\u7ec8\u5f02\u6216 0xFFFFFFFF\u3002\u540e\u679c&#xff1a;FCS \u4e0e\u6807\u51c6\u5dee\u4e00\u4e2a\u56fa\u5b9a\u503c\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;CRC \u8986\u76d6\u8303\u56f4\u5305\u542b\u4e86\u524d\u5bfc\u7801\u548c SFD\u3002\u540e\u679c&#xff1a;FCS \u9519\u8bef\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;CRC \u8986\u76d6\u8303\u56f4\u6f0f\u4e86\u586b\u5145\u5b57\u8282\u3002\u540e\u679c&#xff1a;\u5c0f\u5e27\u7684 FCS \u9519\u8bef\u3002<\/li>\n<\/ul>\n<h4>12.4 \u65f6\u5e8f\u9519\u8bef<\/h4>\n<ul>\n<li>\u9519\u8bef&#xff1a;tx_en \u6bd4 txd \u665a\u4e00\u62cd\u3002\u540e\u679c&#xff1a;\u7b2c\u4e00\u4e2a\u5b57\u8282\u4e22\u5931\u6216\u9519\u4f4d\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;IFG \u4e0d\u8db3 12 \u4e2a\u5468\u671f\u3002\u540e\u679c&#xff1a;\u80cc\u9760\u80cc\u53d1\u9001\u65f6\u63a5\u6536\u7aef\u4e22\u5e27\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;FCS \u8ba1\u7b97\u5b8c\u6210\u524d\u5c31\u5207\u6362\u5230\u53d1\u9001\u72b6\u6001\u3002\u540e\u679c&#xff1a;FCS \u5b57\u8282\u662f\u65e7\u503c\u3002<\/li>\n<\/ul>\n<h4>12.5 \u957f\u5ea6\u9519\u8bef<\/h4>\n<ul>\n<li>\u9519\u8bef&#xff1a;\u6700\u5c0f\u5e27\u6ca1\u586b\u5145\u5230 64 \u5b57\u8282\u3002\u540e\u679c&#xff1a;\u4ea4\u6362\u673a\u53ef\u80fd\u4e22\u5f03&#xff08; runt frame&#xff09;\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;\u957f\u5ea6\u5b57\u6bb5\u7edf\u8ba1\u5305\u542b\u4e86 FCS\u3002\u540e\u679c&#xff1a;\u4e0a\u5c42\u89e3\u6790\u9519\u4f4d\u3002<\/li>\n<li>\u9519\u8bef&#xff1a;\u6700\u5927\u5e27\u8d85\u8fc7 1518 \u5b57\u8282\u4f46\u6ca1\u534f\u5546\u5de8\u578b\u5e27\u3002\u540e\u679c&#xff1a;\u88ab\u4e22\u5f03\u3002<\/li>\n<\/ul>\n<h3>13. \u8c03\u8bd5\u624b\u6bb5\u4e0e\u5de5\u5177<\/h3>\n<h4>13.1 \u7528 Wireshark \u6293\u5305\u9a8c\u8bc1<\/h4>\n<p>\u6700\u76f4\u63a5\u7684\u65b9\u6cd5&#xff1a;FPGA \u53d1\u9001\u5e27&#xff0c;PC \u7528 Wireshark \u6293\u5305\u3002\u5982\u679c Wireshark \u663e\u793a \u201cMalformed Packet\u201d \u6216 \u201cBad FCS\u201d&#xff0c;\u8bf4\u660e\u5e27\u683c\u5f0f\u6709\u95ee\u9898\u3002Wireshark \u53ef\u4ee5\u663e\u793a\u6bcf\u4e2a\u5b57\u6bb5\u7684\u5341\u516d\u8fdb\u5236\u503c&#xff0c;\u9010\u5b57\u6bb5\u5bf9\u6bd4\u3002<\/p>\n<h4>13.2 \u7528 ILA \u89c2\u5bdf GMII \u4fe1\u53f7<\/h4>\n<p>Xilinx Vivado \u7684 ILA \u53ef\u4ee5\u6293\u53d6 gmii_txd\u3001gmii_tx_en \u7684\u6ce2\u5f62\u3002\u89e6\u53d1\u6761\u4ef6\u8bbe\u4e3a gmii_tx_en \u4e0a\u5347\u6cbf&#xff0c;\u89c2\u5bdf\u524d\u5bfc\u7801\u3001SFD\u3001\u6570\u636e\u3001FCS \u7684\u5b57\u8282\u5e8f\u5217\u662f\u5426\u7b26\u5408\u9884\u671f\u3002<\/p>\n<h4>13.3 \u7528\u73af\u56de\u6a21\u5f0f\u81ea\u6d4b<\/h4>\n<p>PHY \u82af\u7247\u901a\u5e38\u652f\u6301\u5185\u90e8\u73af\u56de&#xff08;loopback&#xff09;&#xff0c;MAC \u53d1\u9001\u7684\u5e27\u76f4\u63a5\u56de\u5230 MAC \u63a5\u6536\u3002\u8fd9\u6837\u53ef\u4ee5\u6392\u9664\u5916\u90e8\u94fe\u8def\u95ee\u9898&#xff0c;\u4e13\u6ce8\u8c03\u8bd5 MAC \u903b\u8f91\u3002<\/p>\n<h4>13.4 \u7528\u5df2\u77e5\u5e27\u505a\u9ec4\u91d1\u53c2\u8003<\/h4>\n<p>\u4ece Wireshark \u5bfc\u51fa\u4e00\u4e2a\u771f\u5b9e\u5e27\u7684\u5341\u516d\u8fdb\u5236\u6570\u636e&#xff0c;\u4f5c\u4e3a\u6d4b\u8bd5\u5e73\u53f0\u7684\u8f93\u5165&#xff0c;\u5bf9\u6bd4 FPGA \u8ba1\u7b97\u51fa\u7684 FCS \u4e0e\u6293\u5305\u4e2d\u7684 FCS\u3002\u5982\u679c\u4e0d\u4e00\u81f4&#xff0c;\u9010\u4f4d\u6392\u67e5 CRC \u5b9e\u73b0\u3002<\/p>\n<h3>14. \u6027\u80fd\u4f18\u5316\u4e0e\u5de5\u7a0b\u5b9e\u8df5<\/h3>\n<h4>14.1 \u6d41\u6c34\u7ebf\u8bbe\u8ba1<\/h4>\n<p>\u53d1\u9001\u72b6\u6001\u673a\u7684\u6570\u636e\u901a\u8def\u53ef\u4ee5\u6d41\u6c34\u5316&#xff1a;\u5730\u5740\u751f\u6210\u3001BRAM \u8bfb\u3001CRC \u8ba1\u7b97\u3001GMII \u8f93\u51fa\u5404\u5360\u4e00\u7ea7&#xff0c;\u63d0\u9ad8\u65f6\u5e8f\u4f59\u91cf\u3002\u4f46\u8981\u6ce8\u610f\u5404\u7ea7\u4e4b\u95f4\u7684\u63e1\u624b\u548c\u6c14\u6ce1\u5904\u7406\u3002<\/p>\n<h4>14.2 \u591a\u5e27\u7f13\u5b58\u4e0e\u4e52\u4e53<\/h4>\n<p>\u9ad8\u541e\u5410\u573a\u666f\u4e0b&#xff0c;\u5355\u5e27\u7f13\u5b58\u4e0d\u591f\u7528\u3002\u53ef\u4ee5\u7528\u4e52\u4e53\u7f13\u51b2&#xff1a;\u4e00\u4e2a\u7f13\u5b58\u53d1\u9001\u65f6&#xff0c;\u53e6\u4e00\u4e2a\u7f13\u5b58\u63a5\u6536\u4e0a\u5c42\u6570\u636e\u3002\u5207\u6362\u65f6\u8981\u6ce8\u610f\u5e27\u8fb9\u754c\u5bf9\u9f50\u3002<\/p>\n<h4>14.3 \u65f6\u949f\u57df crossing<\/h4>\n<p>GMII \u7684 rx_clk \u662f\u4ece PHY \u6062\u590d\u7684\u65f6\u949f&#xff0c;\u548c FPGA \u7cfb\u7edf\u65f6\u949f\u4e0d\u540c\u6e90\u3002\u63a5\u6536\u6570\u636e\u8981\u8de8\u65f6\u949f\u57df\u5230\u7cfb\u7edf\u65f6\u949f\u57df&#xff0c;\u7528\u5f02\u6b65 FIFO\u3002\u53d1\u9001\u65b9\u5411 tx_clk \u901a\u5e38\u7531 FPGA \u63d0\u4f9b&#xff0c;\u548c\u7cfb\u7edf\u65f6\u949f\u540c\u6e90&#xff0c;\u4e0d\u9700\u8981 CDC\u3002<\/p>\n<h4>14.4 \u8d44\u6e90\u4f30\u7b97<\/h4>\n<p>\u4e00\u4e2a\u57fa\u672c\u7684\u5343\u5146 MAC&#xff08;\u53d1\u9001 &#043; \u63a5\u6536 &#043; CRC&#xff09;\u5728 Xilinx 7 \u7cfb\u5217\u4e0a\u5927\u7ea6\u5360\u7528&#xff1a;<\/p>\n<ul>\n<li>LUT&#xff1a;800~1200&#xff1b;<\/li>\n<li>FF&#xff1a;600~900&#xff1b;<\/li>\n<li>BRAM&#xff1a;2~4 \u5757&#xff08;\u5e27\u7f13\u5b58&#xff09;&#xff1b;<\/li>\n<li>\u65f6\u5e8f&#xff1a;125MHz \u4e0b WNS \u5bb9\u6613\u6ee1\u8db3\u3002<\/li>\n<\/ul>\n<p>\u5982\u679c\u52a0 VLAN \u89e3\u6790\u3001\u591a\u961f\u5217\u3001\u7edf\u8ba1\u8ba1\u6570\u5668&#xff0c;\u8d44\u6e90\u4f1a\u7ffb\u500d\u3002<\/p>\n<h3>15. \u603b\u7ed3<\/h3>\n<p>\u4ee5\u592a\u7f51\u5e27\u683c\u5f0f\u7684\u6838\u5fc3\u5c31\u4e09\u53e5\u8bdd&#xff1a;<\/p>\n<li>\u524d\u5bfc\u7801 7\u00d70x55 &#043; SFD 0xD5&#xff0c;\u7136\u540e\u662f\u5927\u7aef\u5b57\u8282\u5e8f\u7684 DA\/SA\/Type\/Payload\/FCS&#xff1b;<\/li>\n<li>FCS \u662f CRC-32&#xff0c;\u8986\u76d6 DA \u5230 Payload&#xff08;\u542b\u586b\u5145&#xff09;&#xff0c;\u521d\u503c\u5168 1&#xff0c;\u53cd\u5c04&#xff0c;\u6700\u7ec8\u5f02\u6216\u5168 1&#xff0c;\u9ad8\u5b57\u8282\u5148\u53d1&#xff1b;<\/li>\n<li>\u6700\u5c0f\u5e27 64 \u5b57\u8282&#xff08;\u4e0d\u542b\u524d\u5bfc\u7801&#xff09;&#xff0c;IFG 12 \u5b57\u8282\u65f6\u95f4&#xff0c;\u5343\u5146\u4e0b 8 \u4f4d\u6570\u636e 125MHz\u3002<\/li>\n<p>\u628a\u8fd9\u4e09\u70b9\u843d\u5b9e\u5230 RTL&#xff0c;\u5c31\u662f\u672c\u6587\u7684\u53d1\u9001\u72b6\u6001\u673a\u548c\u63a5\u6536\u72b6\u6001\u673a\u3002\u8c03\u8bd5\u65f6\u4f18\u5148\u7528 Wireshark \u6293\u5305\u5bf9\u6bd4&#xff0c;\u7528 ILA \u770b\u6ce2\u5f62&#xff0c;\u7528\u73af\u56de\u6392\u9664\u94fe\u8def\u95ee\u9898\u3002<\/p>\n<p>\u5e27\u683c\u5f0f\u4e0d\u96be&#xff0c;\u96be\u5728\u7ec6\u8282\u3002\u524d\u5bfc\u7801\u5c11\u4e00\u4e2a\u5b57\u8282\u3001FCS \u5b57\u8282\u5e8f\u53cd\u4e86\u3001CRC \u521d\u503c\u9519\u4e86&#xff0c;\u4efb\u4f55\u4e00\u4e2a\u90fd\u4f1a\u8ba9\u5e27\u5728\u94fe\u8def\u4e0a\u6d88\u5931\u5f97\u65e0\u5f71\u65e0\u8e2a\u3002\u628a\u672c\u6587\u7684\u4ee3\u7801\u8dd1\u901a&#xff0c;\u628a\u6bcf\u4e2a\u5b57\u6bb5\u7684\u5b57\u8282\u5e8f\u548c\u65f6\u5e8f\u641e\u6e05\u695a&#xff0c;\u5343\u5146\u4ee5\u592a\u7f51\u5c31\u4e0d\u518d\u662f\u9ed1\u76d2\u3002<\/p>\n<h3>16. \u5e38\u89c1\u9519\u8bef\u6e05\u5355\u4e0e\u8c03\u8bd5\u624b\u6bb5<\/h3>\n<p>\u524d\u9762\u7b2c 12 \u7ae0\u6309\u300c\u524d\u5bfc\u7801 \/ \u5b57\u8282\u5e8f \/ CRC \/ \u65f6\u5e8f \/ \u957f\u5ea6\u300d\u4e94\u7c7b\u505a\u4e86\u5b9a\u6027\u5f52\u7eb3&#xff0c;\u4f46\u771f\u6b63\u5728\u677f\u5b50\u4e0a\u8c03\u4e0d\u901a\u65f6&#xff0c;\u5de5\u7a0b\u5e08\u9700\u8981\u7684\u662f\u53ef\u6267\u884c\u7684\u6392\u67e5\u8def\u5f84&#xff1a;\u770b\u5230\u4ec0\u4e48\u73b0\u8c61\u3001\u5bf9\u5e94\u54ea\u6761\u6839\u56e0\u3001\u7528\u4ec0\u4e48\u624b\u6bb5\u5b9a\u4f4d\u3001\u600e\u4e48\u6539\u3002\u672c\u8282\u628a\u5343\u5146\u4ee5\u592a\u7f51 FPGA \u8c03\u8bd5\u4e2d\u6700\u9ad8\u9891\u7684\u95ee\u9898\u6574\u7406\u6210\u4e00\u5f20\u901f\u67e5\u8868&#xff0c;\u6bcf\u6761\u90fd\u7ed9\u51fa\u300c\u73b0\u8c61 \/ \u6839\u56e0 \/ \u5b9a\u4f4d\u65b9\u6cd5 \/ \u4fee\u590d\u65b9\u5f0f\u300d\u56db\u5217&#xff0c;\u5efa\u8bae\u6253\u5370\u51fa\u6765\u8d34\u5728\u5de5\u4f4d\u4e0a\u3002<br \/>\n\u5982\u679c\u9700\u8981\u7cfb\u7edf\u5b66\u4e60FPGA&#xff0c;\u8fd9\u91cc\u6709\u4e00\u4efd\u6574\u7406\u7684FPGA\u6c47\u603b\u8bfe\u7a0b\u8d44\u6599&#xff0c;\u5305\u542bBD\u6559\u7a0b\u3001Vivado\u6559\u7a0b\u3001IP \u6838\u6559\u7a0b\u7b49&#xff0c;\u6709\u9700\u8981\u7684\u670b\u53cb\u53ef\u4ee5\u4fdd\u5b58&#xff1a;\u94fe\u63a5: https:\/\/pan.baidu.com\/s\/1pIFS8GEYu_jH1np4ZLG2Kw?pwd&#061;wbbw \u63d0\u53d6\u7801: wbbw \u6574\u7406\u4e0d\u6613&#xff0c;\u5c3d\u5feb\u4fdd\u5b58<\/p>\n<h4>16.1 \u9ad8\u9891\u95ee\u9898\u901f\u67e5\u8868<\/h4>\n<table>\n<tr>#\u95ee\u9898\u73b0\u8c61\u6839\u56e0\u5b9a\u4f4d\u65b9\u6cd5\u4fee\u590d\u65b9\u5f0f<\/tr>\n<tbody>\n<tr>\n<td>1<\/td>\n<td>FCS \u5b57\u8282\u5e8f\u53cd\u4e86<\/td>\n<td>Wireshark \u663e\u793a \u201cBad FCS\u201d \u6216 \u201cMalformed Packet\u201d&#xff1b;\u63a5\u6536\u7aef err_crc \u6301\u7eed\u62c9\u9ad8&#xff1b;\u7528 ILA \u770b FCS \u56db\u5b57\u8282\u4e0e Wireshark \u8ba1\u7b97\u503c\u300c\u6574\u4f53\u5012\u5e8f\u300d<\/td>\n<td>\u628a CRC \u7ed3\u679c\u7684\u4f4e\u5b57\u8282 crc_out[7:0] \u5148\u53d1&#xff0c;\u800c\u4ee5\u592a\u7f51\u8981\u6c42\u9ad8\u5b57\u8282 crc_out[31:24] \u5148\u53d1<\/td>\n<td>\u6293\u4e00\u5e27&#xff0c;\u628a ILA \u4e0a FCS \u56db\u5b57\u8282\u4e0e Wireshark \u7684 \u201cFrame check sequence\u201d \u9010\u5b57\u8282\u5bf9\u6bd4&#xff1b;\u82e5\u5b8c\u5168\u9006\u5e8f\u5373\u4e3a\u672c\u6761<\/td>\n<td>\u53d1\u9001\u72b6\u6001\u673a S_FCS \u6309 [31:24]\u2192[23:16]\u2192[15:8]\u2192[7:0] \u987a\u5e8f\u8f93\u51fa&#xff1b;\u63a5\u6536\u7aef\u6bd4\u8f83\u65f6\u6309 {fcs_buf[0],fcs_buf[1],fcs_buf[2],fcs_buf[3]} \u62fc\u63a5<\/td>\n<\/tr>\n<tr>\n<td>2<\/td>\n<td>\u524d\u5bfc\u7801\u5c11\u53d1\u4e00\u4e2a 0x55<\/td>\n<td>\u90e8\u5206 PHY \u94fe\u8def\u6307\u793a\u706f\u6b63\u5e38\u4f46\u6536\u4e0d\u5230\u5e27&#xff1b;Wireshark \u6293\u4e0d\u5230\u4efb\u4f55\u5305&#xff1b;\u67d0\u4e9b PHY \u80fd\u6536\u3001\u67d0\u4e9b\u4e0d\u80fd&#xff08;\u5bf9 CDR \u9501\u5b9a\u65f6\u95f4\u654f\u611f&#xff09;<\/td>\n<td>pre_cnt \u8ba1\u6570\u8303\u56f4\u5199\u6210 0~5&#xff08;6 \u4e2a\u5b57\u8282&#xff09;\u6216\u72b6\u6001\u673a\u8fdb\u5165 S_PREAMBLE \u9996\u62cd\u6709\u6c14\u6ce1&#xff0c;\u5b9e\u9645\u53ea\u53d1\u51fa 6 \u4e2a 0x55<\/td>\n<td>ILA \u89e6\u53d1 gmii_tx_en \u4e0a\u5347\u6cbf&#xff0c;\u6570 txd&#061;&#061;0x55 \u7684\u8fde\u7eed\u5468\u671f\u6570&#xff0c;\u5e94\u4e3a 7&#xff1b;\u540c\u65f6\u786e\u8ba4 tx_en \u62c9\u9ad8\u9996\u62cd txd \u5c31\u662f 0x55<\/td>\n<td>pre_cnt \u6539\u4e3a 0~6 \u5171 7 \u62cd&#xff1b;S_IDLE\u2192S_PREAMBLE \u8f6c\u79fb\u5f53\u62cd\u5373\u8f93\u51fa 0x55 \u5e76\u62c9\u9ad8 tx_en&#xff0c;\u4e0d\u7559\u7a7a\u62cd<\/td>\n<\/tr>\n<tr>\n<td>3<\/td>\n<td>IFG \u4e0d\u8db3 12 \u5468\u671f<\/td>\n<td>\u5355\u5e27\u6536\u53d1\u6b63\u5e38&#xff0c;\u80cc\u9760\u80cc\u8fde\u7eed\u53d1\u9001\u65f6\u4e22\u5e27\u7387\u968f\u901f\u7387\u4e0a\u5347&#xff1b;\u4ea4\u6362\u673a\u7aef\u53e3\u7edf\u8ba1 FCS Error \/ Alignment Error \u589e\u957f<\/td>\n<td>ifg_cnt \u4e0a\u9650\u5199\u6210 10 \u6216 11 \u4f46\u8ba1\u6570\u8d77\u70b9\u665a\u4e00\u62cd&#xff0c;\u5b9e\u9645\u53ea\u6709 10~11 \u4e2a\u7a7a\u95f2\u5468\u671f&#xff1b;\u6216 IFG \u671f\u95f4 tx_en \u672a\u5b8c\u5168\u62c9\u4f4e<\/td>\n<td>ILA \u6293\u8fde\u7eed\u4e24\u5e27&#xff0c;\u6d4b\u91cf\u524d\u4e00\u5e27 FCS \u672b\u5b57\u8282\u5230\u4e0b\u4e00\u5e27\u9996\u4e2a 0x55 \u4e4b\u95f4\u7684 tx_en&#061;&#061;0 \u5468\u671f\u6570&#xff0c;\u5e94 \u2265 12<\/td>\n<td>ifg_cnt \u4ece 0 \u8ba1\u5230 11 \u5171 12 \u62cd&#xff0c;\u4e14\u4ece tx_en \u62c9\u4f4e\u90a3\u4e00\u62cd\u5f00\u59cb\u8ba1\u6570&#xff1b;IFG \u671f\u95f4\u5f3a\u5236 tx_en&#061;0\u3001txd \u53ef\u7f6e 0<\/td>\n<\/tr>\n<tr>\n<td>4<\/td>\n<td>tx_en \u6709\u6c14\u6ce1<\/td>\n<td>\u5e27\u88ab\u622a\u65ad\u6216\u957f\u5ea6\u5f02\u5e38&#xff1b;Wireshark \u62a5 \u201cShort Frame\u201d&#xff1b;\u63a5\u6536\u7aef rx_len \u6bd4\u9884\u671f\u5c0f<\/td>\n<td>\u72b6\u6001\u673a\u5728 S_DATA \u4e2d\u56e0 BRAM \u8bfb\u5ef6\u8fdf\u672a\u5bf9\u9f50&#xff0c;\u63d2\u5165\u4e86 tx_en&#061;0 \u7684\u7b49\u5f85\u5468\u671f&#xff1b;\u6216 tx_en \u7531\u7ec4\u5408\u903b\u8f91\u4ea7\u751f&#xff0c;\u51fa\u73b0\u6bdb\u523a<\/td>\n<td>ILA \u6293 gmii_tx_en&#xff0c;\u68c0\u67e5\u4e00\u5e27\u5185\u662f\u5426\u4e3a\u8fde\u7eed\u9ad8\u7535\u5e73&#xff08;\u4e2d\u95f4\u4e0d\u5141\u8bb8\u6709\u4f4e\u7535\u5e73&#xff09;&#xff1b;\u7edf\u8ba1\u9ad8\u7535\u5e73\u5468\u671f\u6570\u662f\u5426\u7b49\u4e8e\u5e27\u957f<\/td>\n<td>\u7528\u9884\u53d6&#xff08;prefetch&#xff09;\u65b9\u5f0f\u63d0\u524d\u4e00\u62cd\u7ed9\u5730\u5740&#xff0c;\u4fdd\u8bc1 rd_data \u4e0e tx_en \u540c\u62cd\u5bf9\u9f50&#xff1b;tx_en \u5fc5\u987b\u5bc4\u5b58\u5668\u8f93\u51fa&#xff0c;\u7981\u6b62\u7ec4\u5408\u4ea7\u751f<\/td>\n<\/tr>\n<tr>\n<td>5<\/td>\n<td>RGMII skew \u672a\u52a0\u5bfc\u81f4\u91c7\u6837\u9519\u4f4d<\/td>\n<td>\u94fe\u8def up \u4f46\u8bef\u7801\u7387\u9ad8&#xff1b;\u5c0f\u6d41\u91cf\u5076\u53d1\u4e22\u5305&#xff0c;\u5927\u6d41\u91cf\u51e0\u4e4e\u5168\u4e22&#xff1b;\u6362\u4e00\u5757\u677f\u5b50\u73b0\u8c61\u4e0d\u540c&#xff08;\u8d70\u7ebf\u957f\u5ea6\u5dee\u5f02&#xff09;<\/td>\n<td>RGMII \u7684 TXC \u76f8\u5bf9 TXD \u9700\u8981 1.5~2ns \u5ef6\u8fdf&#xff0c;PCB \u672a\u505a\u7b49\u957f\u7ed5\u7ebf\u4e14 FPGA \u4fa7\u672a\u52a0 ODELAY&#xff0c;\u91c7\u6837\u70b9\u843d\u5728\u6570\u636e\u8df3\u53d8\u6cbf<\/td>\n<td>\u7528\u793a\u6ce2\u5668\u6d4b TXC \u4e0e TXD \u76f8\u4f4d\u5173\u7cfb&#xff1b;\u6216\u5728 FPGA \u5185\u7528 IDELAY \u626b\u63cf tap \u503c&#xff0c;\u89c2\u5bdf\u8bef\u7801\u7387\u968f tap \u53d8\u5316\u7684\u300c\u6d74\u76c6\u66f2\u7ebf\u300d<\/td>\n<td>\u53d1\u9001\u4fa7\u52a0 ODELAY&#xff08;Xilinx 7 \u7cfb\u5217\u7ea6 tap \u503c\u5bf9\u5e94 1.5~2ns&#xff09;&#xff0c;\u63a5\u6536\u4fa7\u52a0 IDELAY \u5e76\u628a tap \u626b\u5230\u6d74\u76c6\u4e2d\u5fc3&#xff1b;\u6216 PCB \u4e0a\u5bf9 TXC \u505a\u5ef6\u8fdf\u7ed5\u7ebf<\/td>\n<\/tr>\n<tr>\n<td>6<\/td>\n<td>CRC \u521d\u503c \/ \u53cd\u5c04\u914d\u7f6e\u9519<\/td>\n<td>FCS \u4e0e\u6807\u51c6\u503c\u5dee\u4e00\u4e2a\u56fa\u5b9a\u504f\u79fb&#xff1b;\u6216\u6240\u6709\u5e27 FCS \u5168\u9519\u4f46\u957f\u5ea6\u3001\u5b57\u8282\u5e8f\u90fd\u5bf9<\/td>\n<td>\u521d\u503c\u7528\u4e86 0x00000000 \u800c\u975e 0xFFFFFFFF&#xff1b;\u6216\u6f0f\u4e86\u8f93\u5165\/\u8f93\u51fa\u53cd\u5c04&#xff08;\u5e94 LSB first&#xff09;&#xff1b;\u6216\u6f0f\u4e86\u6700\u7ec8\u5f02\u6216 0xFFFFFFFF<\/td>\n<td>\u7528\u56fa\u5b9a\u6d4b\u8bd5\u5411\u91cf&#xff08;\u5982 ASCII \u201c123456789\u201d \u7684 CRC-32 \u5e94\u4e3a 0xCBF43926&#xff09;\u5355\u72ec\u4eff\u771f CRC \u6a21\u5757&#xff0c;\u4e0e\u6807\u51c6\u503c\u5bf9\u6bd4<\/td>\n<td>\u521d\u503c 0xFFFFFFFF\u3001\u8f93\u5165\u8f93\u51fa\u5747\u53cd\u5c04&#xff08;\u591a\u9879\u5f0f\u7528 0xEDB88320&#xff09;\u3001\u6700\u7ec8\u5f02\u6216 0xFFFFFFFF&#xff0c;\u4e09\u8005\u7f3a\u4e00\u4e0d\u53ef<\/td>\n<\/tr>\n<tr>\n<td>7<\/td>\n<td>\u6700\u5c0f\u5e27\u672a\u586b\u5145\u5230 46 \u5b57\u8282<\/td>\n<td>\u5c0f\u5305&#xff08;\u5982 ARP\u3001TCP ACK&#xff09;\u88ab\u4ea4\u6362\u673a\u4e22\u5f03&#xff1b;Wireshark \u62a5 \u201cRunt Frame\u201d&#xff1b;\u5927\u5305\u6b63\u5e38<\/td>\n<td>\u53d1\u9001\u72b6\u6001\u673a\u76f4\u63a5\u6309 tx_len \u7ec4\u5e27&#xff0c;\u672a\u505a tx_len &lt; 46 \u65f6\u8865 0 \u7684\u5904\u7406&#xff1b;\u6216\u586b\u5145\u4e86\u4f46 FCS \u672a\u8986\u76d6\u586b\u5145\u5b57\u8282<\/td>\n<td>\u6293\u4e00\u4e2a\u77ed\u5305&#xff0c;\u770b\u7ebf\u4e0a\u5e27\u957f\u662f\u5426 &lt; 64 \u5b57\u8282&#xff1b;\u68c0\u67e5 CRC \u8ba1\u7b97\u662f\u5426\u5305\u542b\u4e86\u586b\u5145\u533a<\/td>\n<td>payload_len_padded &#061; (tx_len &lt; 46) ? 46 : tx_len&#xff1b;\u586b\u5145\u5b57\u8282&#xff08;\u901a\u5e38 0&#xff09;\u5fc5\u987b\u53c2\u4e0e CRC \u8ba1\u7b97&#xff0c;\u4e14\u5728 FCS \u4e4b\u524d\u53d1\u51fa<\/td>\n<\/tr>\n<tr>\n<td>8<\/td>\n<td>SFD \u5bf9\u9f50\u9519\u4f4d<\/td>\n<td>\u63a5\u6536\u7aef\u5076\u5c14\u628a\u6570\u636e\u9996\u5b57\u8282\u5f53\u6210 SFD&#xff0c;\u6216\u6574\u5e27\u504f\u79fb\u4e00\u4e2a\u5b57\u8282&#xff1b;rx_da \u89e3\u6790\u51fa\u660e\u663e\u9519\u8bef\u7684 MAC<\/td>\n<td>\u63a5\u6536\u72b6\u6001\u673a\u5728 8 \u4f4d\u901a\u8def\u4e0a\u6309\u5b57\u8282\u5339\u914d 0xD5&#xff0c;\u4f46\u524d\u5bfc\u7801\u56e0 PHY \u65f6\u949f\u6062\u590d\u4e22\u5931\u524d\u51e0\u5b57\u8282&#xff0c;\u5bfc\u81f4 0xD5 \u51fa\u73b0\u5728\u975e\u9884\u671f\u4f4d\u7f6e&#xff1b;\u6216\u4f4d\u5e8f&#xff08;LSB\/MSB&#xff09;\u7406\u89e3\u9519\u8bef<\/td>\n<td>ILA \u6293 rxd \u5e8f\u5217&#xff0c;\u4eba\u5de5\u6838\u5bf9 &#8230;0x55,0x55,0xD5,DA[0]&#8230; \u7684\u5b57\u8282\u8fb9\u754c&#xff1b;\u5bf9\u6bd4 rx_da \u4e0e\u53d1\u9001\u7aef DA<\/td>\n<td>\u63a5\u6536\u7aef\u76f4\u63a5\u68c0\u6d4b 0xD5 \u4f5c\u4e3a\u5e27\u8d77\u59cb&#xff08;\u4e0d\u5f3a\u5236\u5148\u89c1 7 \u4e2a 0x55&#xff09;&#xff1b;\u786e\u8ba4\u4ee5\u592a\u7f51 LSB first&#xff0c;0xD5 \u7ebf\u4e0a\u4f4d\u6d41\u4e3a 1010_1011<\/td>\n<\/tr>\n<tr>\n<td>9<\/td>\n<td>tx_en \u4e0e txd \u76f8\u4f4d\u9519\u4e00\u62cd<\/td>\n<td>\u9996\u5b57\u8282\u4e22\u5931&#xff0c;\u63a5\u6536\u7aef DA \u9996\u5b57\u8282\u53d8\u6210 0x55 \u6216 0xD5&#xff1b;\u6574\u5e27\u6570\u636e\u5de6\u79fb\u4e00\u5b57\u8282<\/td>\n<td>tx_en \u4e0e txd \u4e0d\u5728\u540c\u4e00\u62cd\u66f4\u65b0&#xff0c;tx_en \u665a\u4e00\u62cd\u62c9\u9ad8&#xff0c;\u5bfc\u81f4\u9996\u62cd txd \u4e0a\u7684 0x55 \u672a\u88ab\u91c7\u5230<\/td>\n<td>ILA \u540c\u65f6\u6293 tx_en \u4e0e txd&#xff0c;\u786e\u8ba4 tx_en \u4e0a\u5347\u6cbf\u90a3\u4e00\u62cd\u7684 txd \u662f\u5426\u4e3a 0x55<\/td>\n<td>tx_en \u4e0e txd \u5728\u540c\u4e00 always \u5757\u3001\u540c\u4e00\u65f6\u949f\u6cbf\u8d4b\u503c&#xff0c;\u4fdd\u8bc1\u4e25\u683c\u540c\u62cd<\/td>\n<\/tr>\n<tr>\n<td>10<\/td>\n<td>\u63a5\u6536\u7aef CRC \u6bd4\u8f83\u65f6\u5e8f\u9519<\/td>\n<td>err_crc \u968f\u673a\u8bef\u62a5&#xff0c;\u540c\u4e00\u5e27\u6709\u65f6\u901a\u8fc7\u6709\u65f6\u4e0d\u901a\u8fc7&#xff1b;\u4eff\u771f\u901a\u8fc7\u3001\u4e0a\u677f\u5931\u8d25<\/td>\n<td>crc_out \u6709 1~2 \u7ea7\u6d41\u6c34\u5ef6\u8fdf&#xff0c;\u5728 S_DONE \u6bd4\u8f83\u65f6 CRC \u5c1a\u672a\u7a33\u5b9a&#xff1b;\u6216 FCS \u56db\u5b57\u8282\u88ab\u8bef\u5582\u8fdb CRC<\/td>\n<td>\u4eff\u771f\u4e2d\u6253\u5370 crc_out \u4e0e fcs_buf \u7684\u65f6\u5e8f\u5173\u7cfb&#xff1b;\u68c0\u67e5 S_FCS \u72b6\u6001\u662f\u5426\u8bef\u4f7f\u80fd crc_en<\/td>\n<td>\u5728 S_FCS \u4e0e S_DONE \u4e4b\u95f4\u63d2\u5165\u7b49\u5f85\u5468\u671f&#xff0c;\u6216\u628a crc_out \u6253\u62cd\u5bf9\u9f50\u540e\u518d\u6bd4\u8f83&#xff1b;S_FCS \u72b6\u6001\u7981\u6b62\u4f7f\u80fd crc_en<\/td>\n<\/tr>\n<tr>\n<td>11<\/td>\n<td>\u5e27\u7f13\u5b58\u8bfb\u5ef6\u8fdf\u672a\u5bf9\u9f50<\/td>\n<td>\u6570\u636e\u6574\u4f53\u9519\u4f4d\u4e00\u4e2a\u5b57\u8282&#xff1b;\u6216\u9996\u5b57\u8282\u4e3a\u4e0a\u4e00\u5e27\u6b8b\u7559\u6570\u636e<\/td>\n<td>\u540c\u6b65\u8bfb BRAM \u6709\u4e00\u62cd\u8bfb\u5ef6\u8fdf&#xff0c;\u72b6\u6001\u673a\u6309\u300c\u5f53\u62cd\u7ed9\u5730\u5740\u5f53\u62cd\u53d6\u6570\u300d\u7f16\u5199&#xff0c;\u5b9e\u9645\u53d6\u5230\u7684\u662f\u4e0a\u4e00\u5730\u5740\u6570\u636e<\/td>\n<td>\u4eff\u771f\u4e2d\u89c2\u5bdf rd_addr \u4e0e rd_data \u7684\u5bf9\u5e94\u5173\u7cfb&#xff0c;\u786e\u8ba4\u662f\u5426\u5dee\u4e00\u62cd<\/td>\n<td>\u5730\u5740\u63d0\u524d\u4e00\u62cd\u7ed9\u51fa&#xff08;prefetch&#xff09;&#xff0c;\u6216\u628a tx_en\/txd \u6574\u4f53\u5ef6\u8fdf\u4e00\u62cd\u5bf9\u9f50<\/td>\n<\/tr>\n<tr>\n<td>12<\/td>\n<td>\u5de8\u578b\u5e27\u672a\u534f\u5546\u88ab\u4e22\u5f03<\/td>\n<td>\u5927\u5305&#xff08;&gt;1518 \u5b57\u8282&#xff09;\u5168\u90e8\u4e22\u5931&#xff0c;\u5c0f\u5305\u6b63\u5e38&#xff1b;\u4ea4\u6362\u673a\u7aef\u53e3\u7edf\u8ba1 Oversize \u589e\u957f<\/td>\n<td>\u53d1\u9001\u7aef\u53d1\u4e86 Jumbo \u5e27\u4f46\u94fe\u8def\u5bf9\u7aef \/ \u4ea4\u6362\u673a\u672a\u5f00\u542f Jumbo Frame \u652f\u6301<\/td>\n<td>\u6293\u5305\u786e\u8ba4\u5e27\u957f\u662f\u5426 &gt; 1518&#xff1b;\u67e5\u4ea4\u6362\u673a Jumbo \u914d\u7f6e<\/td>\n<td>\u4e24\u7aef\u540c\u65f6\u5f00\u542f Jumbo \u5e76\u7edf\u4e00 MTU&#xff1b;\u6216\u628a\u8d1f\u8f7d\u62c6\u5206\u5230\u591a\u4e2a\u6807\u51c6\u5e27<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>16.2 \u6309\u73b0\u8c61\u53cd\u67e5\u7684\u6392\u67e5\u987a\u5e8f<\/h4>\n<p>\u4e0a\u8868\u6309\u95ee\u9898\u5f52\u7c7b&#xff0c;\u5b9e\u9645\u8c03\u8bd5\u65f6\u66f4\u5e38\u89c1\u7684\u662f\u300c\u5148\u770b\u5230\u73b0\u8c61&#xff0c;\u518d\u53cd\u67e5\u6839\u56e0\u300d\u3002\u5efa\u8bae\u6309\u4e0b\u9762\u7684\u987a\u5e8f\u9010\u5c42\u6536\u655b&#xff0c;\u907f\u514d\u4e00\u4e0a\u6765\u5c31\u6000\u7591 CRC&#xff1a;<\/p>\n<p>#mermaid-svg-q6mk7ERFNSej9QSI{font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;font-size:16px;fill:#333;}@keyframes edge-animation-frame{from{stroke-dashoffset:0;}}@keyframes dash{to{stroke-dashoffset:0;}}#mermaid-svg-q6mk7ERFNSej9QSI .edge-animation-slow{stroke-dasharray:9,5!important;stroke-dashoffset:900;animation:dash 50s linear infinite;stroke-linecap:round;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-animation-fast{stroke-dasharray:9,5!important;stroke-dashoffset:900;animation:dash 20s linear infinite;stroke-linecap:round;}#mermaid-svg-q6mk7ERFNSej9QSI .error-icon{fill:#552222;}#mermaid-svg-q6mk7ERFNSej9QSI .error-text{fill:#552222;stroke:#552222;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-thickness-normal{stroke-width:1px;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-thickness-thick{stroke-width:3.5px;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-pattern-solid{stroke-dasharray:0;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-thickness-invisible{stroke-width:0;fill:none;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-pattern-dashed{stroke-dasharray:3;}#mermaid-svg-q6mk7ERFNSej9QSI .edge-pattern-dotted{stroke-dasharray:2;}#mermaid-svg-q6mk7ERFNSej9QSI .marker{fill:#333333;stroke:#333333;}#mermaid-svg-q6mk7ERFNSej9QSI .marker.cross{stroke:#333333;}#mermaid-svg-q6mk7ERFNSej9QSI svg{font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;font-size:16px;}#mermaid-svg-q6mk7ERFNSej9QSI p{margin:0;}#mermaid-svg-q6mk7ERFNSej9QSI .label{font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;color:#333;}#mermaid-svg-q6mk7ERFNSej9QSI .cluster-label text{fill:#333;}#mermaid-svg-q6mk7ERFNSej9QSI .cluster-label span{color:#333;}#mermaid-svg-q6mk7ERFNSej9QSI .cluster-label span p{background-color:transparent;}#mermaid-svg-q6mk7ERFNSej9QSI .label text,#mermaid-svg-q6mk7ERFNSej9QSI span{fill:#333;color:#333;}#mermaid-svg-q6mk7ERFNSej9QSI .node rect,#mermaid-svg-q6mk7ERFNSej9QSI .node circle,#mermaid-svg-q6mk7ERFNSej9QSI .node ellipse,#mermaid-svg-q6mk7ERFNSej9QSI .node polygon,#mermaid-svg-q6mk7ERFNSej9QSI .node path{fill:#ECECFF;stroke:#9370DB;stroke-width:1px;}#mermaid-svg-q6mk7ERFNSej9QSI .rough-node .label text,#mermaid-svg-q6mk7ERFNSej9QSI .node .label text,#mermaid-svg-q6mk7ERFNSej9QSI .image-shape .label,#mermaid-svg-q6mk7ERFNSej9QSI .icon-shape .label{text-anchor:middle;}#mermaid-svg-q6mk7ERFNSej9QSI .node .katex path{fill:#000;stroke:#000;stroke-width:1px;}#mermaid-svg-q6mk7ERFNSej9QSI .rough-node .label,#mermaid-svg-q6mk7ERFNSej9QSI .node .label,#mermaid-svg-q6mk7ERFNSej9QSI .image-shape .label,#mermaid-svg-q6mk7ERFNSej9QSI .icon-shape .label{text-align:center;}#mermaid-svg-q6mk7ERFNSej9QSI .node.clickable{cursor:pointer;}#mermaid-svg-q6mk7ERFNSej9QSI .root .anchor path{fill:#333333!important;stroke-width:0;stroke:#333333;}#mermaid-svg-q6mk7ERFNSej9QSI .arrowheadPath{fill:#333333;}#mermaid-svg-q6mk7ERFNSej9QSI .edgePath .path{stroke:#333333;stroke-width:2.0px;}#mermaid-svg-q6mk7ERFNSej9QSI .flowchart-link{stroke:#333333;fill:none;}#mermaid-svg-q6mk7ERFNSej9QSI .edgeLabel{background-color:rgba(232,232,232, 0.8);text-align:center;}#mermaid-svg-q6mk7ERFNSej9QSI .edgeLabel p{background-color:rgba(232,232,232, 0.8);}#mermaid-svg-q6mk7ERFNSej9QSI .edgeLabel rect{opacity:0.5;background-color:rgba(232,232,232, 0.8);fill:rgba(232,232,232, 0.8);}#mermaid-svg-q6mk7ERFNSej9QSI .labelBkg{background-color:rgba(232, 232, 232, 0.5);}#mermaid-svg-q6mk7ERFNSej9QSI .cluster rect{fill:#ffffde;stroke:#aaaa33;stroke-width:1px;}#mermaid-svg-q6mk7ERFNSej9QSI .cluster text{fill:#333;}#mermaid-svg-q6mk7ERFNSej9QSI .cluster span{color:#333;}#mermaid-svg-q6mk7ERFNSej9QSI div.mermaidTooltip{position:absolute;text-align:center;max-width:200px;padding:2px;font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;font-size:12px;background:hsl(80, 100%, 96.2745098039%);border:1px solid #aaaa33;border-radius:2px;pointer-events:none;z-index:100;}#mermaid-svg-q6mk7ERFNSej9QSI .flowchartTitleText{text-anchor:middle;font-size:18px;fill:#333;}#mermaid-svg-q6mk7ERFNSej9QSI rect.text{fill:none;stroke-width:0;}#mermaid-svg-q6mk7ERFNSej9QSI .icon-shape,#mermaid-svg-q6mk7ERFNSej9QSI .image-shape{background-color:rgba(232,232,232, 0.8);text-align:center;}#mermaid-svg-q6mk7ERFNSej9QSI .icon-shape p,#mermaid-svg-q6mk7ERFNSej9QSI .image-shape p{background-color:rgba(232,232,232, 0.8);padding:2px;}#mermaid-svg-q6mk7ERFNSej9QSI .icon-shape .label rect,#mermaid-svg-q6mk7ERFNSej9QSI .image-shape .label rect{opacity:0.5;background-color:rgba(232,232,232, 0.8);fill:rgba(232,232,232, 0.8);}#mermaid-svg-q6mk7ERFNSej9QSI .label-icon{display:inline-block;height:1em;overflow:visible;vertical-align:-0.125em;}#mermaid-svg-q6mk7ERFNSej9QSI .node .label-icon path{fill:currentColor;stroke:revert;stroke-width:revert;}#mermaid-svg-q6mk7ERFNSej9QSI :root{&#8211;mermaid-font-family:\\&#8221;trebuchet ms\\&#8221;,verdana,arial,sans-serif;}<span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u6293\u4e0d\u5230<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u65e0\u6ce2\u5f62<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u6709\u6ce2\u5f62<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/span><span class=\"edgeLabel\"><\/p>\n<p>\u80fd\u6293\u5230\u4f46\u62a5\u9519<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>Bad FCS<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>Runt \/ Short<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>Oversize<\/p>\n<p><\/span><span class=\"edgeLabel\"><\/p>\n<p>Malformed<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u73b0\u8c61: \u6536\u4e0d\u5230\u5305 \/ \u9519\u5e27<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>Wireshark \u80fd\u6293\u5230\u5e27\u5417?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>PHY \u94fe\u8def up \u4e14 ILA \u4e0a tx_en \u6709\u6ce2\u5f62?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5\u53d1\u9001\u72b6\u6001\u673a: tx_req \u63e1\u624b \/ \u72b6\u6001\u673a\u5361\u6b7b<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5\u524d\u5bfc\u7801 7\u00d70x55 \u4e0e SFD 0xD5 \u662f\u5426\u5b8c\u6574<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5 RGMII skew \/ GMII \u65f6\u5e8f\u7ea6\u675f<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u62a5\u9519\u7c7b\u578b?<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5 CRC \u521d\u503c\/\u53cd\u5c04\/\u5f02\u6216 \u4e0e FCS \u5b57\u8282\u5e8f<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5\u6700\u5c0f\u5e27\u586b\u5145\u4e0e tx_en \u6c14\u6ce1<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5\u5de8\u578b\u5e27\u534f\u5546\u4e0e\u957f\u5ea6\u5b57\u6bb5<\/p>\n<p><\/span><span class=\"nodeLabel\"><\/p>\n<p>\u67e5 DA\/SA\/Type \u5b57\u8282\u5e8f\u4e0e VLAN \u504f\u79fb<\/p>\n<p><\/span><\/p>\n<p>\u6392\u67e5\u7684\u6838\u5fc3\u539f\u5219\u662f\u4ece\u7269\u7406\u5c42\u5f80\u534f\u8bae\u5c42\u6536\u655b&#xff1a;\u5148\u786e\u8ba4\u94fe\u8def\u548c\u65f6\u5e8f&#xff08;skew\u3001tx_en \u6ce2\u5f62&#xff09;&#xff0c;\u518d\u786e\u8ba4\u5e27\u8fb9\u754c&#xff08;\u524d\u5bfc\u7801\u3001SFD\u3001IFG&#xff09;&#xff0c;\u6700\u540e\u624d\u67e5\u5b57\u6bb5\u5185\u5bb9&#xff08;\u5b57\u8282\u5e8f\u3001CRC\u3001\u957f\u5ea6&#xff09;\u3002\u7edd\u5927\u591a\u6570\u300c\u7384\u5b66\u4e22\u5305\u300d\u6700\u7ec8\u90fd\u843d\u5728\u524d\u4e24\u5c42\u3002<br \/>\n\u5982\u679c\u9700\u8981\u7cfb\u7edf\u5b66\u4e60FPGA&#xff0c;\u8fd9\u91cc\u6709\u4e00\u4efd\u6574\u7406\u7684FPGA\u6c47\u603b\u8bfe\u7a0b\u8d44\u6599&#xff0c;\u5305\u542bBD\u6559\u7a0b\u3001Vivado\u6559\u7a0b\u3001IP \u6838\u6559\u7a0b\u7b49&#xff0c;\u6709\u9700\u8981\u7684\u670b\u53cb\u53ef\u4ee5\u4fdd\u5b58&#xff1a;\u94fe\u63a5: https:\/\/pan.baidu.com\/s\/1pIFS8GEYu_jH1np4ZLG2Kw?pwd&#061;wbbw \u63d0\u53d6\u7801: wbbw \u6574\u7406\u4e0d\u6613&#xff0c;\u5c3d\u5feb\u4fdd\u5b58<\/p>\n<h4>16.3 \u4e09\u4e2a\u6700\u5bb9\u6613\u88ab\u5ffd\u7565\u7684\u7ec6\u8282<\/h4>\n<p>\u7b2c\u4e00&#xff0c;tx_en \u7684\u6c14\u6ce1\u6bd4\u60f3\u8c61\u4e2d\u66f4\u81f4\u547d\u3002 \u5f88\u591a\u5b9e\u73b0\u4e3a\u4e86\u7701\u4e00\u4e2a BRAM \u800c\u7528\u7ec4\u5408\u903b\u8f91\u76f4\u63a5\u8f93\u51fa tx_en&#xff0c;\u7efc\u5408\u540e\u51fa\u73b0\u6bdb\u523a\u6216\u4e0e txd \u4e0d\u540c\u62cd&#xff0c;\u63a5\u6536\u7aef\u4f1a\u628a\u8fd9\u4e00\u62cd\u5f53\u6210\u5e27\u7ed3\u675f&#xff0c;\u6574\u5e27\u88ab\u622a\u65ad\u3002tx_en \u5fc5\u987b\u5bc4\u5b58\u5668\u8f93\u51fa&#xff0c;\u4e14\u4e0e txd \u4e25\u683c\u540c\u62cd\u3002<\/p>\n<p>\u7b2c\u4e8c&#xff0c;CRC \u7684\u300c\u4e09\u4e2a\u53c2\u6570\u300d\u5fc5\u987b\u540c\u65f6\u6b63\u786e\u3002 \u521d\u503c\u3001\u53cd\u5c04\u3001\u6700\u7ec8\u5f02\u6216&#xff0c;\u4efb\u4f55\u4e00\u4e2a\u9519\u90fd\u4f1a\u8ba9 FCS \u5168\u9519&#xff0c;\u4f46\u9519\u8bef\u8868\u73b0\u4e0d\u540c&#xff1a;\u521d\u503c\u9519\u662f\u300c\u5dee\u4e00\u4e2a\u56fa\u5b9a\u504f\u79fb\u300d&#xff0c;\u53cd\u5c04\u9519\u662f\u300c\u5b8c\u5168\u5bf9\u4e0d\u4e0a\u300d&#xff0c;\u6f0f\u6700\u7ec8\u5f02\u6216\u662f\u300c\u5dee 0xFFFFFFFF\u300d\u3002\u7528\u56fa\u5b9a\u6d4b\u8bd5\u5411\u91cf\u5355\u72ec\u9a8c\u8bc1 CRC \u6a21\u5757&#xff0c;\u6bd4\u5728\u6574\u6761\u94fe\u8def\u4e0a\u731c\u8981\u5feb\u5f97\u591a\u3002<\/p>\n<p>\u7b2c\u4e09&#xff0c;RGMII \u7684 skew \u662f\u677f\u7ea7\u95ee\u9898&#xff0c;\u4e0d\u662f\u903b\u8f91\u95ee\u9898\u3002 \u540c\u4e00\u4efd RTL \u5728\u4e0d\u540c\u677f\u5b50\u4e0a\u8868\u73b0\u4e0d\u540c&#xff0c;\u51e0\u4e4e\u4e00\u5b9a\u662f skew \u6ca1\u8c03\u597d\u3002\u7528 IDELAY \u626b\u63cf tap \u503c\u753b\u8bef\u7801\u7387\u66f2\u7ebf&#xff0c;\u627e\u5230\u6d74\u76c6\u5e95\u90e8&#xff0c;\u6bd4\u53cd\u590d\u6539\u903b\u8f91\u6709\u6548\u5f97\u591a\u3002<\/p>\n<p>\u628a\u8fd9\u5f20\u8868\u548c\u8fd9\u5957\u6392\u67e5\u987a\u5e8f\u7528\u719f&#xff0c;\u5343\u5146\u4ee5\u592a\u7f51\u8c03\u8bd5\u5c31\u4ece\u300c\u78b0\u8fd0\u6c14\u300d\u53d8\u6210\u4e86\u300c\u6309\u56fe\u7d22\u9aa5\u300d\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"<p>1. \u4e3a\u4ec0\u4e48 FPGA \u5de5\u7a0b\u5e08\u5fc5\u987b\u5403\u900f\u4ee5\u592a\u7f51\u5e27\u683c\u5f0f<br \/>\n\u5728 FPGA \u4e0a\u505a\u5343\u5146\u4ee5\u592a\u7f51&#xff08;1000BASE-T \/ 1000BASE-X&#xff09;&#xff0c;\u5f88\u591a\u4eba\u7b2c\u4e00\u6b65\u5c31\u5361\u4f4f&#xff1a;PHY \u82af\u7247\u5df2\u7ecf\u94fe\u8def up&#xff0c;MAC \u4fa7\u4e5f\u6536\u5230\u4e86\u6570\u636e&#xff0c;\u4f46\u6293\u5305\u5de5\u5177\u91cc\u5168\u662f\u9519\u5e27&#xff0c;\u6216\u8005\u4e0a\u4f4d\u673a\u6839\u672c\u6536\u4e0d\u5230\u5305\u3002\u6392\u67e5\u5230\u6700\u540e&#xff0c;\u95ee\u9898\u5f80\u5f80\u4e0d\u5728\u65f6\u5e8f\u3001\u4e0d\u5728\u65f6\u949f\u57df&#xff0c;\u800c\u662f\u5e27\u683c\u5f0f\u7684\u67d0\u4e2a\u5b57\u6bb5\u5199\u9519\u4e86\u2014\u2014\u524d\u5bfc\u7801\u5c11\u4e86\u4e00\u4e2a\u5b57\u8282\u3001FCS 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