{"id":113967,"date":"2026-10-08T02:17:16","date_gmt":"2026-10-07T18:17:16","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/113967.html"},"modified":"2026-10-08T02:17:16","modified_gmt":"2026-10-07T18:17:16","slug":"%e7%a1%ac%e4%bb%b6%e7%94%bb%e5%b8%83%e4%b8%8a%e7%9a%84%e7%a5%9e%e7%bb%8f%e7%bd%91%e7%bb%9c%ef%bc%9afpga-%e5%a6%82%e4%bd%95%e7%94%a8%e5%8f%af%e9%87%8d%e6%9e%84%e9%80%bb%e8%be%91%e9%9b%95","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/113967.html","title":{"rendered":"\u786c\u4ef6\u753b\u5e03\u4e0a\u7684\u795e\u7ecf\u7f51\u7edc\uff1aFPGA \u5982\u4f55\u7528\u53ef\u91cd\u6784\u903b\u8f91\u201c\u96d5\u523b\u201dAI \u63a8\u7406"},"content":{"rendered":"<p>FPGA \u5b9e\u73b0\u795e\u7ecf\u7f51\u7edc&#xff0c;\u672c\u8d28\u4e0a\u662f\u628a\u795e\u7ecf\u7f51\u7edc\u7684\u201c\u8ba1\u7b97\u56fe\u201d\u6620\u5c04\u5230\u4e00\u5757\u53ef\u91cd\u6784\u7684\u786c\u4ef6\u753b\u5e03\u4e0a\u2014\u2014\u4f60\u53ef\u4ee5\u5728\u4e0a\u9762\u201c\u753b\u201d\u51fa\u4efb\u610f\u5f62\u72b6\u7684\u8ba1\u7b97\u5355\u5143\u3001\u4efb\u610f\u7cbe\u5ea6\u7684\u6570\u636e\u901a\u8def\u3001\u4efb\u610f\u6df1\u5ea6\u7684\u6d41\u6c34\u7ebf\u3002\u5b83\u4e0d\u662f GPU \u7684\u901a\u7528\u5e76\u884c&#xff0c;\u4e5f\u4e0d\u662f ASIC \u7684\u56fa\u5b9a\u7535\u8def&#xff0c;\u800c\u662f\u5728\u4e24\u8005\u4e4b\u95f4\u5360\u636e\u4e86\u4e00\u4e2a\u72ec\u7279\u751f\u6001\u4f4d&#xff1a;\u6bd4 GPU \u66f4\u7701\u7535\u3001\u6bd4 ASIC \u66f4\u7075\u6d3b&#xff0c;\u5c24\u5176\u9002\u5408\u8fb9\u7f18\u63a8\u7406\u3001\u4f4e\u5ef6\u8fdf\u3001\u6a21\u578b\u5feb\u901f\u8fed\u4ee3\u7684\u573a\u666f\u3002<\/p>\n<hr \/>\n<h3>\u4e00\u3001\u4e3a\u4ec0\u4e48\u662f FPGA&#xff1f;<\/h3>\n<h4>1.1 \u4e09\u79cd\u786c\u4ef6\u7684\u4e09\u89d2\u5173\u7cfb<\/h4>\n<p>\u7406\u89e3 FPGA \u7684\u4ef7\u503c&#xff0c;\u9700\u8981\u628a\u5b83\u653e\u5728 GPU \u548c ASIC \u7684\u5bf9\u6bd4\u4e2d\u770b&#xff1a;<\/p>\n<table>\n<tr>\u7ef4\u5ea6GPUFPGAASIC<\/tr>\n<tbody>\n<tr>\n<td>\u7075\u6d3b\u6027<\/td>\n<td>\u9ad8&#xff0c;\u7f16\u7a0b\u5373\u53ef<\/td>\n<td>\u6781\u9ad8&#xff0c;\u7535\u8def\u53ef\u91cd\u6784<\/td>\n<td>\u4f4e&#xff0c;\u6d41\u7247\u540e\u56fa\u5b9a<\/td>\n<\/tr>\n<tr>\n<td>\u80fd\u6548<\/td>\n<td>\u4e2d<\/td>\n<td>\u9ad8<\/td>\n<td>\u6781\u9ad8<\/td>\n<\/tr>\n<tr>\n<td>\u5ef6\u8fdf<\/td>\n<td>\u4e2d<\/td>\n<td>\u4f4e\u4e14\u786e\u5b9a<\/td>\n<td>\u6781\u4f4e<\/td>\n<\/tr>\n<tr>\n<td>\u5f00\u53d1\u6210\u672c<\/td>\n<td>\u4f4e<\/td>\n<td>\u4e2d<\/td>\n<td>\u6781\u9ad8<\/td>\n<\/tr>\n<tr>\n<td>\u9002\u5408\u9636\u6bb5<\/td>\n<td>\u8bad\u7ec3\/\u5927\u541e\u5410\u63a8\u7406<\/td>\n<td>\u8fb9\u7f18\u63a8\u7406\/\u5feb\u901f\u8fed\u4ee3<\/td>\n<td>\u5927\u89c4\u6a21\u91cf\u4ea7<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>FPGA \u5360\u636e\u7684\u662f\u201c\u4e2d\u95f4\u5730\u5e26\u201d&#xff1a;\u5b83\u4e0d\u50cf GPU \u90a3\u6837\u4e3a\u901a\u7528\u5e76\u884c\u727a\u7272\u80fd\u6548&#xff0c;\u4e5f\u4e0d\u50cf ASIC \u90a3\u6837\u4e00\u65e6\u6d41\u7247\u5c31\u65e0\u6cd5\u4fee\u6539\u3002\u5bf9\u4e8e\u6a21\u578b\u5feb\u901f\u8fed\u4ee3\u3001\u5c0f\u6279\u91cf\u90e8\u7f72\u3001\u6216\u8005\u9700\u8981\u5b9a\u5236\u6570\u636e\u901a\u8def\u7684\u573a\u666f&#xff0c;FPGA \u7684\u53ef\u91cd\u6784\u6027\u672c\u8eab\u5c31\u662f\u6838\u5fc3\u4ef7\u503c\u3002<\/p>\n<h4>1.2 \u4e0e GPU \u7684\u80fd\u6548\u5bf9\u6bd4<\/h4>\n<p>\u5728\u63a8\u7406\u573a\u666f\u4e2d&#xff0c;FPGA \u7684\u80fd\u6548\u901a\u5e38\u4f18\u4e8e GPU\u3002\u4e00\u9879\u57fa\u4e8e PYNQ-Z2 \u7684 CNN \u52a0\u901f\u5668\u7814\u7a76\u663e\u793a&#xff0c;\u5176\u80fd\u6548\u8fbe\u5230 114 GOP\/s\/W&#xff0c;\u76f8\u6bd4\u540c\u4e00\u5e73\u53f0\u4e0a ARM \u6838\u5fc3\u7684\u8f6f\u4ef6\u5b9e\u73b0\u63d0\u5347\u4e86 3.5 \u500d\u3002\u53e6\u4e00\u9879\u5de5\u4f5c\u5728 ZYNQ XC7Z045 \u4e0a\u8fbe\u5230\u4e86 102 Gops\/W \u7684\u80fd\u6548&#xff0c;\u529f\u8017\u6548\u7387\u76f8\u6bd4\u5176\u4ed6\u65b9\u6848\u63d0\u5347\u4e86\u8d85\u8fc7 38.7%\u3002<\/p>\n<h4>1.3 \u4e0e ASIC \u7684\u5b9a\u4f4d\u5dee\u5f02<\/h4>\n<p>ASIC \u7684\u80fd\u6548\u6700\u9ad8&#xff0c;\u4f46\u5b83\u7684\u975e\u7ecf\u5e38\u6027\u5de5\u7a0b\u6210\u672c\u6781\u9ad8&#xff0c;\u4e14\u6d41\u7247\u540e\u65e0\u6cd5\u4fee\u6539\u3002FPGA \u867d\u7136\u5355\u82af\u7247\u6210\u672c\u548c\u80fd\u6548\u4e0d\u5982 ASIC&#xff0c;\u4f46\u5b83\u5141\u8bb8\u5728\u90e8\u7f72\u540e\u91cd\u65b0\u914d\u7f6e&#xff0c;\u8fd9\u5bf9\u6a21\u578b\u9891\u7e41\u66f4\u65b0\u3001\u6216\u8005\u9700\u8981\u652f\u6301\u591a\u79cd\u7f51\u7edc\u67b6\u6784\u7684\u573a\u666f\u81f3\u5173\u91cd\u8981\u3002<\/p>\n<hr \/>\n<h3>\u4e8c\u3001FPGA \u7684\u786c\u4ef6\u57fa\u7840<\/h3>\n<h4>2.1 \u53ef\u91cd\u6784\u7684\u903b\u8f91\u753b\u5e03<\/h4>\n<p>FPGA \u7684\u6838\u5fc3\u662f\u4e00\u5927\u7247\u53ef\u914d\u7f6e\u903b\u8f91\u5757\u548c\u53ef\u7f16\u7a0b\u4e92\u8fde\u3002\u4f60\u53ef\u4ee5\u628a\u5b83\u4eec\u60f3\u8c61\u6210\u4e50\u9ad8\u79ef\u6728&#xff1a;\u6bcf\u4e2a\u903b\u8f91\u5757\u53ef\u4ee5\u5b9e\u73b0\u7b80\u5355\u7684\u7ec4\u5408\u903b\u8f91\u6216\u65f6\u5e8f\u903b\u8f91&#xff0c;\u4e92\u8fde\u51b3\u5b9a\u4e86\u8fd9\u4e9b\u5757\u4e4b\u95f4\u5982\u4f55\u8fde\u63a5\u3002\u901a\u8fc7\u914d\u7f6e\u6bd4\u7279\u6d41&#xff0c;\u4f60\u53ef\u4ee5\u5b9a\u4e49\u4efb\u610f\u6570\u5b57\u7535\u8def\u3002<\/p>\n<h4>2.2 \u5173\u952e\u786c\u4ef6\u8d44\u6e90<\/h4>\n<table>\n<tr>\u8d44\u6e90\u4f5c\u7528\u795e\u7ecf\u7f51\u7edc\u4e2d\u7684\u7528\u9014<\/tr>\n<tbody>\n<tr>\n<td>LUT<\/td>\n<td>\u67e5\u627e\u8868&#xff0c;\u5b9e\u73b0\u4efb\u610f\u903b\u8f91\u51fd\u6570<\/td>\n<td>\u6fc0\u6d3b\u51fd\u6570\u3001\u63a7\u5236\u903b\u8f91\u3001\u5c0f\u89c4\u6a21\u4e58\u6cd5<\/td>\n<\/tr>\n<tr>\n<td>DSP<\/td>\n<td>\u6570\u5b57\u4fe1\u53f7\u5904\u7406\u5355\u5143&#xff0c;\u786c\u4ef6\u4e58\u6cd5\u5668<\/td>\n<td>\u5377\u79ef\u3001\u77e9\u9635\u4e58\u6cd5<\/td>\n<\/tr>\n<tr>\n<td>BRAM<\/td>\n<td>\u5757\u72b6\u5b58\u50a8\u5668&#xff0c;\u7247\u4e0a\u5b58\u50a8<\/td>\n<td>\u6743\u91cd\u7f13\u5b58\u3001\u7279\u5f81\u56fe\u7f13\u5b58<\/td>\n<\/tr>\n<tr>\n<td>URAM<\/td>\n<td>\u8d85\u5927\u5bb9\u91cf\u7247\u4e0a\u5b58\u50a8&#xff08;\u90e8\u5206\u578b\u53f7&#xff09;<\/td>\n<td>\u5927\u6a21\u578b\u6743\u91cd\u5b58\u50a8<\/td>\n<\/tr>\n<tr>\n<td>DSP48<\/td>\n<td>\u589e\u5f3a\u578b DSP&#xff0c;\u652f\u6301\u4e58\u7d2f\u52a0<\/td>\n<td>\u5377\u79ef\u6838\u5fc3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>FPGA \u7684\u5e76\u884c\u6027\u6765\u81ea\u8fd9\u4e9b\u8d44\u6e90\u7684\u7a7a\u95f4\u5206\u5e03&#xff1a;\u4f60\u53ef\u4ee5\u5728\u540c\u4e00\u65f6\u523b\u8ba9\u6570\u767e\u4e2a DSP \u540c\u65f6\u505a\u4e58\u6cd5&#xff0c;\u8ba9\u6570\u5341\u4e2a BRAM \u540c\u65f6\u63d0\u4f9b\u6570\u636e&#xff0c;\u8ba9\u6d41\u6c34\u7ebf\u5404\u7ea7\u540c\u65f6\u5de5\u4f5c\u3002<\/p>\n<hr \/>\n<h3>\u4e09\u3001\u6838\u5fc3\u8bbe\u8ba1\u65b9\u6cd5\u8bba<\/h3>\n<h4>3.1 \u6570\u636e\u6d41\u67b6\u6784<\/h4>\n<p>FPGA \u795e\u7ecf\u7f51\u7edc\u52a0\u901f\u5668\u6700\u6838\u5fc3\u7684\u8bbe\u8ba1\u6a21\u5f0f\u662f\u6570\u636e\u6d41\u3002\u4e0e CPU \u7684\u6307\u4ee4\u6d41\u4e0d\u540c&#xff0c;\u6570\u636e\u6d41\u67b6\u6784\u4e2d&#xff0c;\u6570\u636e\u50cf\u6c34\u6d41\u4e00\u6837\u7a7f\u8fc7\u4e00\u7cfb\u5217\u8ba1\u7b97\u5355\u5143&#xff0c;\u6bcf\u4e2a\u5355\u5143\u5728\u6570\u636e\u5230\u8fbe\u65f6\u7acb\u5373\u5904\u7406&#xff0c;\u65e0\u9700\u7b49\u5f85\u6307\u4ee4\u3002<\/p>\n<p>\u5178\u578b\u7684\u6570\u636e\u6d41\u6a21\u5f0f\u5305\u62ec&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u8109\u52a8\u9635\u5217&#xff1a;\u8ba1\u7b97\u5355\u5143\u6309\u7f51\u683c\u6392\u5217&#xff0c;\u6570\u636e\u4ece\u8fb9\u7f18\u6d41\u5165\u3001\u5bf9\u89d2\u6d41\u51fa&#xff0c;\u6bcf\u4e2a\u5355\u5143\u505a\u4e58\u7d2f\u52a0\u540e\u4f20\u7ed9\u90bb\u5c45\u3002\u8fd9\u79cd\u7ed3\u6784\u5728 CNN \u5377\u79ef\u4e2d\u975e\u5e38\u9ad8\u6548\u3002<\/p>\n<\/li>\n<li>\n<p>\u6d41\u5f0f\u6570\u636e\u6d41&#xff1a;\u5c42\u4e0e\u5c42\u4e4b\u95f4\u76f4\u63a5\u6d41\u5f0f\u8fde\u63a5&#xff0c;\u4e2d\u95f4\u7ed3\u679c\u4e0d\u5199\u56de\u5916\u90e8\u5b58\u50a8\u3002<\/p>\n<\/li>\n<li>\n<p>\u5c42\u95f4\u878d\u5408&#xff1a;\u628a\u76f8\u90bb\u7684\u8ba1\u7b97\u5bc6\u96c6\u5c42\u7d27\u5bc6\u8026\u5408&#xff0c;\u5728\u4e00\u4e2a\u6d41\u6c34\u7ebf\u4e2d\u987a\u5e8f\u6267\u884c&#xff0c;\u51cf\u5c11\u7247\u5916\u8bbf\u5b58\u3002<\/p>\n<\/li>\n<\/ul>\n<h4>3.2 \u5e76\u884c\u7b56\u7565<\/h4>\n<p>FPGA \u53ef\u4ee5\u5728\u591a\u4e2a\u7ef4\u5ea6\u4e0a\u5e76\u884c&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u8f93\u51fa\u901a\u9053\u5e76\u884c&#xff1a;\u540c\u65f6\u8ba1\u7b97\u591a\u4e2a\u8f93\u51fa\u901a\u9053\u3002<\/p>\n<\/li>\n<li>\n<p>\u8f93\u5165\u901a\u9053\u5e76\u884c&#xff1a;\u540c\u65f6\u5904\u7406\u591a\u4e2a\u8f93\u5165\u901a\u9053\u3002<\/p>\n<\/li>\n<li>\n<p>\u7a7a\u95f4\u5e76\u884c&#xff1a;\u540c\u65f6\u8ba1\u7b97\u591a\u4e2a\u8f93\u51fa\u50cf\u7d20\u3002<\/p>\n<\/li>\n<li>\n<p>\u6d41\u6c34\u7ebf\u5e76\u884c&#xff1a;\u4e0d\u540c\u5c42\u6216\u540c\u4e00\u5c42\u7684\u4e0d\u540c\u9636\u6bb5\u91cd\u53e0\u6267\u884c\u3002<\/p>\n<\/li>\n<\/ul>\n<p>\u5e76\u884c\u5ea6\u7684\u9009\u62e9\u9700\u8981\u5728\u8d44\u6e90\u5360\u7528\u3001\u541e\u5410\u91cf\u3001\u529f\u8017\u4e4b\u95f4\u6743\u8861\u3002<\/p>\n<h4>3.3 \u5faa\u73af\u5c55\u5f00\u4e0e\u6d41\u6c34\u7ebf<\/h4>\n<p>\u5728 HLS&#xff08;\u9ad8\u5c42\u6b21\u7efc\u5408&#xff09;\u4e2d&#xff0c;\u5faa\u73af\u5c55\u5f00\u548c\u6d41\u6c34\u7ebf\u662f\u6700\u57fa\u672c\u7684\u4f18\u5316\u624b\u6bb5\u3002\u5c55\u5f00\u8ba9\u591a\u4e2a\u8fed\u4ee3\u5e76\u884c\u6267\u884c&#xff0c;\u6d41\u6c34\u7ebf\u8ba9\u4e0d\u540c\u8fed\u4ee3\u7684\u9636\u6bb5\u91cd\u53e0\u3002\u4e8c\u8005\u7684\u7ec4\u5408\u53ef\u4ee5\u663e\u8457\u63d0\u5347\u541e\u5410\u91cf\u3002<\/p>\n<h4>3.4 \u7cbe\u5ea6\u5b9a\u5236<\/h4>\n<p>FPGA \u6700\u72ec\u7279\u7684\u4f18\u52bf\u4e4b\u4e00\u662f\u4efb\u610f\u7cbe\u5ea6\u7b97\u672f\u3002\u4f60\u53ef\u4ee5\u4e3a\u6bcf\u4e00\u5c42\u3001\u751a\u81f3\u6bcf\u4e00\u4e2a\u5f20\u91cf\u5355\u72ec\u5b9a\u4e49\u4f4d\u5bbd&#xff1a;\u6574\u6570\u90e8\u5206\u51e0\u4f4d\u3001\u5c0f\u6570\u90e8\u5206\u51e0\u4f4d\u3001\u662f\u5426\u6709\u7b26\u53f7\u30028 \u4f4d\u5b9a\u70b9\u52a0\u6cd5\u5668\u7684\u80fd\u8017\u4ec5\u4e3a 32 \u4f4d\u7248\u672c\u7684 33%&#xff0c;8 \u4f4d\u4e58\u6cd5\u5668\u66f4\u662f\u4ec5\u7528 6.45% \u7684\u80fd\u91cf\u3002\u8fd9\u79cd\u7ec6\u7c92\u5ea6\u7684\u7cbe\u5ea6\u63a7\u5236\u662f GPU \u548c ASIC \u90fd\u96be\u4ee5\u505a\u5230\u7684\u3002<\/p>\n<hr \/>\n<h3>\u56db\u3001\u6a21\u578b\u538b\u7f29\u4e0e\u786c\u4ef6\u534f\u540c<\/h3>\n<h4>4.1 \u91cf\u5316<\/h4>\n<p>\u91cf\u5316\u662f\u628a\u6d6e\u70b9\u6743\u91cd\u548c\u6fc0\u6d3b\u503c\u8f6c\u6362\u4e3a\u4f4e\u4f4d\u5bbd\u5b9a\u70b9\u6570\u7684\u8fc7\u7a0b\u3002\u5e38\u89c1\u7684\u91cf\u5316\u7b56\u7565\u5305\u62ec&#xff1a;<\/p>\n<ul>\n<li>\n<p>\u8bad\u7ec3\u540e\u91cf\u5316&#xff1a;\u6a21\u578b\u8bad\u7ec3\u5b8c\u6210\u540e\u76f4\u63a5\u8f6c\u6362\u3002<\/p>\n<\/li>\n<li>\n<p>\u91cf\u5316\u611f\u77e5\u8bad\u7ec3&#xff1a;\u5728\u8bad\u7ec3\u4e2d\u6a21\u62df\u91cf\u5316\u8bef\u5dee&#xff0c;\u7cbe\u5ea6\u635f\u5931\u66f4\u5c0f\u3002<\/p>\n<\/li>\n<\/ul>\n<p>\u91cf\u5316\u4e0d\u4ec5\u51cf\u5c11\u5b58\u50a8\u548c\u5e26\u5bbd&#xff0c;\u8fd8\u8ba9\u8ba1\u7b97\u5355\u5143\u66f4\u5c0f\u3001\u66f4\u5feb\u3001\u66f4\u7701\u7535\u3002<\/p>\n<h4>4.2 \u526a\u679d<\/h4>\n<p>\u526a\u679d\u53bb\u9664\u4e0d\u91cd\u8981\u7684\u6743\u91cd\u6216\u795e\u7ecf\u5143&#xff0c;\u51cf\u5c11\u8ba1\u7b97\u91cf\u3002\u4f46\u526a\u679d\u4ea7\u751f\u7684\u975e\u7ed3\u6784\u5316\u7a00\u758f&#xff08;\u96f6\u503c\u4e0d\u89c4\u5219\u5206\u5e03&#xff09;\u7ed9 FPGA \u786c\u4ef6\u5e26\u6765\u6311\u6218&#xff1a;\u4e0d\u89c4\u5219\u7684\u6570\u636e\u8bbf\u95ee\u6a21\u5f0f\u96be\u4ee5\u9ad8\u6548\u5229\u7528\u5e76\u884c\u8d44\u6e90\u3002<\/p>\n<p>\u89e3\u51b3\u65b9\u6848\u5305\u62ec\u7ed3\u6784\u5316\u526a\u679d&#xff08;\u6309\u901a\u9053\u6216\u5757\u526a\u679d&#xff09;\u548c\u786c\u4ef6\u611f\u77e5\u7684\u526a\u679d\u7b56\u7565&#xff0c;\u8ba9\u7a00\u758f\u6a21\u5f0f\u4e0e\u786c\u4ef6\u6570\u636e\u6d41\u5339\u914d\u3002<\/p>\n<h4>4.3 \u91cf\u5316&#043;\u526a\u679d\u7684\u8054\u5408\u6548\u679c<\/h4>\n<p>\u4e00\u9879\u57fa\u4e8e hls4ml \u7684 CNN \u7814\u7a76\u663e\u793a&#xff0c;\u91cf\u5316&#043;\u526a\u679d\u7684\u7ec4\u5408\u4f7f DSP \u8d44\u6e90\u5229\u7528\u7387\u964d\u4f4e\u4e86 63%&#xff0c;\u800c\u5206\u7c7b\u7cbe\u5ea6\u635f\u5931\u6781\u5c0f\u3002\u672a\u538b\u7f29\u6a21\u578b\u5728 MNIST \u4e0a\u8fbe\u5230 99.24% \u7684\u6d4b\u8bd5\u51c6\u786e\u7387\u3002\u53e6\u4e00\u9879\u7814\u7a76\u5b9e\u73b0\u4e86 8 \u4f4d\u91cf\u5316\u300150% \u526a\u679d\u7684 CNN \u76f4\u63a5\u90e8\u7f72\u5230 Artix-7 FPGA \u4e0a\u3002<\/p>\n<h4>4.4 \u7b97\u6cd5-\u786c\u4ef6\u534f\u540c\u8bbe\u8ba1<\/h4>\n<p>\u6700\u6709\u6548\u7684\u4f18\u5316\u4e0d\u662f\u5148\u8bbe\u8ba1\u6a21\u578b\u518d\u60f3\u786c\u4ef6&#xff0c;\u800c\u662f\u6a21\u578b\u548c\u786c\u4ef6\u4e00\u8d77\u8bbe\u8ba1\u3002CoDAC \u6846\u67b6\u628a\u526a\u679d\u3001\u91cf\u5316\u548c\u786c\u4ef6\u4f18\u5316\u7edf\u4e00\u5728\u4e00\u4e2a AutoML \u95ed\u73af\u4e2d&#xff0c;\u8ba9\u786c\u4ef6\u53cd\u9988\u9a71\u52a8\u6a21\u578b\u538b\u7f29\u7b56\u7565\u7684\u8c03\u6574\u3002<\/p>\n<hr \/>\n<h3>\u4e94\u3001\u5de5\u5177\u94fe\u4e0e\u6846\u67b6<\/h3>\n<h4>5.1 HLS&#xff1a;\u4ece C\/C&#043;&#043; \u5230\u786c\u4ef6<\/h4>\n<p>\u9ad8\u5c42\u6b21\u7efc\u5408\u8ba9\u8f6f\u4ef6\u5f00\u53d1\u8005\u7528 C\/C&#043;&#043; \u63cf\u8ff0\u7b97\u6cd5&#xff0c;\u5de5\u5177\u81ea\u52a8\u751f\u6210 RTL\u3002Vitis HLS \u662f Xilinx&#xff08;AMD&#xff09;\u7684\u4e3b\u6d41 HLS \u5de5\u5177&#xff0c;\u652f\u6301 C\/C&#043;&#043; \u5230 HDL \u7684\u8f6c\u6362\u3002<\/p>\n<h4>5.2 hls4ml&#xff1a;\u79d1\u5b66\u8ba1\u7b97\u4e2d\u7684\u6807\u51c6\u5de5\u5177<\/h4>\n<p>hls4ml \u662f\u7c92\u5b50\u7269\u7406\u548c\u79d1\u5b66\u8ba1\u7b97\u9886\u57df\u6700\u6d41\u884c\u7684 FPGA \u795e\u7ecf\u7f51\u7edc\u90e8\u7f72\u5de5\u5177\u3002\u5b83\u4ece Keras\/TensorFlow\/PyTorch \u6a21\u578b\u76f4\u63a5\u751f\u6210 HLS \u4ee3\u7801&#xff0c;\u652f\u6301\u5b9a\u70b9\u91cf\u5316&#xff0c;\u5e76\u81ea\u52a8\u5904\u7406\u6d41\u6c34\u7ebf\u548c\u5e76\u884c\u5316\u3002\u5927\u91cf\u8fb9\u7f18 AI \u7814\u7a76\u90fd\u57fa\u4e8e hls4ml \u6784\u5efa\u3002<\/p>\n<h4>5.3 FINN&#xff1a;\u4e8c\u503c\u795e\u7ecf\u7f51\u7edc\u4e13\u7528<\/h4>\n<p>FINN \u662f Xilinx \u5f00\u53d1\u7684\u4e8c\u503c\u795e\u7ecf\u7f51\u7edc\u6846\u67b6&#xff0c;\u4e13\u95e8\u9488\u5bf9 1 \u4f4d\u6743\u91cd\u548c\u6fc0\u6d3b\u7684\u7f51\u7edc\u3002\u5b83\u7684\u6570\u636e\u6d41\u67b6\u6784\u5145\u5206\u5229\u7528\u4e86\u4e8c\u503c\u7f51\u7edc\u7684\u6781\u4f4e\u8ba1\u7b97\u590d\u6742\u5ea6&#xff0c;\u5728\u6781\u4f4e\u529f\u8017\u4e0b\u5b9e\u73b0\u9ad8\u901f\u63a8\u7406\u3002<\/p>\n<h4>5.4 Py2C \/ Py2RTL&#xff1a;\u4ece Python \u5230 RTL<\/h4>\n<p>Py2C \u662f\u4e00\u4e2a\u81ea\u52a8\u5316\u6846\u67b6&#xff0c;\u628a AI \u6a21\u578b\u4ece Python \u8f6c\u6362\u4e3a C&#xff0c;\u518d\u4e0e Vitis HLS \u96c6\u6210\u5f62\u6210 Py2RTL \u6d41\u7a0b&#xff0c;\u652f\u6301 VGG\u3001ResNet\u3001InceptionNet\u3001YOLO \u7b49\u591a\u79cd\u67b6\u6784&#xff0c;\u5e76\u5141\u8bb8\u7528\u6237\u7075\u6d3b\u8c03\u6574\u7cbe\u5ea6\u53c2\u6570\u3002<\/p>\n<h4>5.5 Spiker&#043;&#xff1a;\u8109\u51b2\u795e\u7ecf\u7f51\u7edc<\/h4>\n<p>Spiker&#043; \u662f\u4e00\u4e2a\u5f00\u6e90\u6846\u67b6&#xff0c;\u7528\u4e8e\u751f\u6210\u4f18\u5316\u7684 SNN \u52a0\u901f\u5668\u3002\u5b83\u652f\u6301\u7f51\u7edc\u62d3\u6251\u3001\u795e\u7ecf\u5143\u6a21\u578b\u548c\u91cf\u5316\u7684\u9ad8\u5c42\u63cf\u8ff0&#xff0c;\u81ea\u52a8\u751f\u6210\u53ef\u90e8\u7f72\u7684 HDL\u3002<\/p>\n<hr \/>\n<h3>\u516d\u3001\u5178\u578b\u5e94\u7528\u573a\u666f<\/h3>\n<h4>6.1 \u8fb9\u7f18 AI \u63a8\u7406<\/h4>\n<p>\u8fd9\u662f FPGA \u6700\u6838\u5fc3\u7684\u5e94\u7528\u573a\u666f\u3002\u8fb9\u7f18\u8bbe\u5907\u9762\u4e34\u529f\u8017\u3001\u5ef6\u8fdf\u3001\u9690\u79c1\u4e09\u91cd\u7ea6\u675f&#xff0c;FPGA \u5728\u8fd9\u4e09\u70b9\u4e0a\u90fd\u6709\u4f18\u52bf\u3002<\/p>\n<ul>\n<li>\n<p>\u56fe\u50cf\u8bc6\u522b&#xff1a;MNIST \u4e0a\u7684 CNN \u52a0\u901f\u5668\u5728 PYNQ-Z2 \u4e0a\u8fbe\u5230 96% \u51c6\u786e\u7387&#xff0c;\u5cf0\u503c\u529f\u8017\u4ec5 1.82W\u3002<\/p>\n<\/li>\n<li>\n<p>\u8111\u80bf\u7624\u8bca\u65ad&#xff1a;AlexNet \u5728 ZCU102 \u4e0a\u90e8\u7f72&#xff0c;\u8bad\u7ec3\u51c6\u786e\u7387 97.8%&#xff0c;\u65f6\u5e8f\u5ef6\u8fdf\u4ec5 7.215 ns\u3002<\/p>\n<\/li>\n<li>\n<p>\u8239\u8236\u8bc6\u522b&#xff1a;Zynq-7020 \u4e0a\u7684 VHDL CNN \u52a0\u901f\u5668\u7528\u4e8e\u5d4c\u5165\u5f0f\u6d77\u4e8b\u8239\u8236\u8bc6\u522b\u3002<\/p>\n<\/li>\n<li>\n<p>\u5fc3\u810f\u8d85\u58f0&#xff1a;8 \u4f4d\u91cf\u5316\u300150% \u526a\u679d\u7684 CNN \u90e8\u7f72\u5728 Artix-7 \u4e0a&#xff0c;\u7528\u4e8e\u6025\u8bca\u548c\u8d44\u6e90\u6709\u9650\u8bca\u6240\u7684\u5e8a\u65c1\u5fc3\u8870\u7b5b\u67e5\u3002<\/p>\n<\/li>\n<\/ul>\n<h4>6.2 \u8109\u51b2\u795e\u7ecf\u7f51\u7edc<\/h4>\n<p>SNN \u7684\u4e8b\u4ef6\u9a71\u52a8\u548c\u7a00\u758f\u6fc0\u6d3b\u7279\u6027\u4e0e FPGA \u7684\u53ef\u91cd\u6784\u6027\u5929\u7136\u5339\u914d\u3002FPGA \u88ab\u8ba4\u4e3a\u662f SNN \u52a0\u901f\u7684\u7406\u60f3\u5019\u9009\u5e73\u53f0&#xff0c;\u5728\u80fd\u6548\u4e0a\u4f18\u4e8e CPU \u548c GPU\u3002<\/p>\n<ul>\n<li>\n<p>\u591a\u6838\u795e\u7ecf\u5f62\u6001\u67b6\u6784&#xff1a;\u5728 FPGA \u4e0a\u90e8\u7f72&#xff0c;\u652f\u6301\u6df1\u5ea6 SNN \u8bad\u7ec3&#xff0c;\u5728\u4ea4\u901a\u6807\u5fd7\u8bc6\u522b\u4e0a\u8fbe\u5230 94.75% \u51c6\u786e\u7387&#xff0c;\u6301\u7eed\u5b66\u4e60\u4f7f\u6df7\u5408\u65b0\u65e7\u6570\u636e\u7684\u63a8\u7406\u51c6\u786e\u7387\u63d0\u5347\u4e86 17.97%\u3002<\/p>\n<\/li>\n<li>\n<p>XOR-Spikformer&#xff1a;\u8109\u51b2 Transformer \u7684 FPGA \u52a0\u901f\u5668&#xff0c;\u5cf0\u503c\u541e\u5410 288 GSOP\/s&#xff0c;\u80fd\u6548 57.67 GSOP\/W&#xff0c;\u4ec5\u4f7f\u7528 47.2K LUT \u548c 63 BRAM&#xff0c;\u96f6 DSP\u3002<\/p>\n<\/li>\n<li>\n<p>\u65e0\u4e58\u6cd5\u5668 SNN&#xff1a;\u5728 ZCU104 \u4e0a\u9a8c\u8bc1\u7684\u53ef\u8bad\u7ec3 SNN&#xff0c;\u901a\u8fc7\u654f\u611f\u566a\u58f0\u9608\u503c\u673a\u5236\u4fdd\u6301\u4e86\u566a\u58f0\u9c81\u68d2\u6027\u3002<\/p>\n<\/li>\n<\/ul>\n<h4>6.3 \u79d1\u5b66\u8ba1\u7b97\u4e0e\u5b9e\u65f6\u4fe1\u53f7\u5904\u7406<\/h4>\n<ul>\n<li>\n<p>SAR \u56fe\u50cf\u8bc6\u522b&#xff1a;\u5168\u6d41\u6c34\u7ebf SNN \u52a0\u901f\u5668&#xff0c;\u541e\u5410 2069 GOPS&#xff0c;\u4ec5\u7528 185K LUT \u548c 78 DSP\u3002<\/p>\n<\/li>\n<li>\n<p>ECG \u4fe1\u53f7\u5206\u7c7b&#xff1a;FPGA \u4e0a\u7684 DNN \u7528\u4e8e\u5fc3\u7535\u56fe\u5206\u7c7b&#xff0c;\u662f\u533b\u7597\u8fb9\u7f18\u8bbe\u5907\u7684\u5178\u578b\u5e94\u7528\u3002<\/p>\n<\/li>\n<li>\n<p>\u76f4\u6d41\u4e32\u8054\u7535\u5f27\u6545\u969c\u68c0\u6d4b&#xff1a;hls4ml \u5de5\u5177\u6d41\u90e8\u7f72\u6df1\u5ea6\u5b66\u4e60\u6a21\u578b&#xff0c;\u7528\u4e8e\u5b9e\u65f6\u6545\u969c\u68c0\u6d4b\u3002<\/p>\n<\/li>\n<\/ul>\n<h4>6.4 \u751f\u6210\u5f0f AI \u4e0e Transformer<\/h4>\n<p>FPGA \u4e5f\u5728\u5411 Transformer \u63a8\u7406\u5ef6\u4f38\u3002\u4e00\u9879\u7814\u7a76\u663e\u793a&#xff0c;FPGA \u5728 Transformer \u63a8\u7406\u4e0a\u7684\u80fd\u6548\u901a\u5e38\u4f18\u4e8e GPU \u57fa\u7ebf\u3002<\/p>\n<hr \/>\n<h3>\u4e03\u3001\u6311\u6218\u4e0e\u5c40\u9650<\/h3>\n<h4>7.1 \u5f00\u53d1\u95e8\u69db\u9ad8<\/h4>\n<p>FPGA \u5f00\u53d1\u4f20\u7edf\u4e0a\u9700\u8981\u786c\u4ef6\u8bbe\u8ba1\u4e13\u4e1a\u77e5\u8bc6&#xff0c;\u5b66\u4e60\u66f2\u7ebf\u9661\u5ced\u3002\u867d\u7136 HLS \u5de5\u5177\u964d\u4f4e\u4e86\u95e8\u69db&#xff0c;\u4f46\u8981\u5b9e\u73b0\u63a5\u8fd1\u624b\u5199 RTL \u7684\u6548\u7387&#xff0c;\u4ecd\u7136\u9700\u8981\u7406\u89e3\u6d41\u6c34\u7ebf\u3001\u6570\u636e\u6d41\u3001\u8d44\u6e90\u7ea6\u675f\u7b49\u786c\u4ef6\u6982\u5ff5\u3002<\/p>\n<h4>7.2 \u5de5\u5177\u94fe\u6210\u719f\u5ea6<\/h4>\n<p>HLS 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