{"id":112670,"date":"2026-10-04T14:09:01","date_gmt":"2026-10-04T06:09:01","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/112670.html"},"modified":"2026-10-04T14:09:01","modified_gmt":"2026-10-04T06:09:01","slug":"%e8%8a%af%e5%8f%82%e8%b0%8b39ddr5-sdram-%e7%94%b5%e8%b7%af%e8%ae%be%e8%ae%a1%e6%8c%87%e5%8d%97","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/112670.html","title":{"rendered":"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357"},"content":{"rendered":"<h4>\u9002\u7528\u8303\u56f4<\/h4>\n<ul>\n<li>\u672c\u6587\u9488\u5bf9\u00a0DDR5 SDRAM&#xff08;JESD79-5 \u7cfb\u5217&#xff09;\u7684\u786c\u4ef6\u7535\u8def\u8bbe\u8ba1&#xff0c;\u8986\u76d6\u9897\u7c92&#xff08;down \/ \u677f\u8f7d&#xff09;\u4e0e\u6a21\u7ec4&#xff08;UDIMM\u3001SODIMM\u3001RDIMM\u3001LRDIMM&#xff09;\u4e24\u7c7b\u843d\u5730\u5f62\u6001&#xff0c;\u901f\u7387\u8986\u76d6\u00a03200 ~ 8800 MT\/s\u3002<\/li>\n<li>\u9002\u7528\u5bf9\u8c61&#xff1a;\u670d\u52a1\u5668 \/ PC \/ \u8fb9\u7f18\u8ba1\u7b97 \/ \u9ad8\u7aef\u5d4c\u5165\u5f0f\u4e3b\u63a7&#xff08;Intel\u3001AMD\u3001\u98de\u817e\u3001\u6d77\u5149\u3001NXP\u3001\u745e\u8428\u3001TI\u3001SoC FPGA \u7b49&#xff09;\u7684\u4e3b\u5b58\u63a5\u53e3\u539f\u7406\u8bbe\u8ba1\u3001PCB Layout\u3001\u7535\u6e90\u5b8c\u6574\u6027\u3001\u4fe1\u53f7\u5b8c\u6574\u6027\u4e0e\u91cf\u4ea7\u8c03\u8bd5\u3002<\/li>\n<li>\u5185\u5bb9\u5305\u542b&#xff1a;\u89c4\u683c\u5bf9\u6bd4\u3001\u5c01\u88c5\u7403\u4f4d\u3001\u4fe1\u53f7\u5b9a\u4e49\u3001CA \u547d\u4ee4\u603b\u7ebf\u534f\u8bae\u3001\u7535\u6e90\u4e0e On-DIMM PMIC\u3001\u5178\u578b\u7535\u8def&#xff08;\u5185\u8054\u539f\u7406\u56fe&#xff09;\u3001\u5b50\u901a\u9053\u67b6\u6784\u4e0e\u8bad\u7ec3\u3001Layout \u89c4\u8303\u3001SI \u4e0e\u7aef\u63a5\u3001ESD \u4e0e\u53ef\u9760\u6027\u3001\u710a\u63a5\u751f\u4ea7\u3001\u6545\u969c\u6392\u67e5\u3001\u68c0\u67e5\u6e05\u5355\u4e0e BOM\u3002<\/li>\n<li>\u4e0d\u5305\u542b&#xff1a;\u4e3b\u63a7\u4fa7\u5185\u5b58\u63a7\u5236\u5668\u5fae\u67b6\u6784\u3001BIOS\/UEFI MRC \u6e90\u7801\u3001\u5b8c\u6574 JEDEC \u5bc4\u5b58\u5668\u4f4d\u5b9a\u4e49\u3002<\/li>\n<\/ul>\n<p>\u53c2\u6570\u6548\u529b\u58f0\u660e<\/p>\n<p>\u5168\u6587\u6240\u6709\u7535\u538b\u3001\u7535\u6d41\u3001\u65f6\u5e8f\u3001\u963b\u6297\u3001\u7aef\u63a5\u503c\u5747\u4e3a\u5de5\u7a0b\u5178\u578b\u503c\u6216\u91cf\u7ea7\u53c2\u8003\u3002\u6700\u7ec8\u8bbe\u8ba1\u4e00\u5f8b\u4ee5\u76ee\u6807\u578b\u53f7 datasheet\u3001\u76ee\u6807\u4e3b\u63a7 DDR \u63a7\u5236\u5668\u8bbe\u8ba1\u6307\u5357&#xff08;PDG \/ Design Guide&#xff09;\u4e0e JEDEC JESD79-5 \u4e3a\u51c6&#xff1b;\u4e0d\u540c\u5382\u5546&#xff08;Micron \/ Samsung \/ SK hynix \/ CXMT&#xff09;\u3001\u4e0d\u540c\u5bc6\u5ea6\u3001\u4e0d\u540c\u901f\u7387\u6863\u7684\u6570\u503c\u5b58\u5728\u660e\u663e\u5dee\u5f02\u3002\u6587\u4e2d\u51e1\u51fa\u73b0\u300c\u5178\u578b\u300d\u300c\u7ea6\u300d\u300c\u5efa\u8bae\u300d\u5747\u8868\u793a\u8be5\u503c\u9700\u6309\u5b9e\u9645\u5668\u4ef6\u590d\u6838\u3002<\/p>\n<h4>\u672c\u7cfb\u5217\u5176\u4ed6\u6587\u6863<\/h4>\n<table>\n<tr>\u6587\u6863\u5668\u4ef6\u7c7b\u578b\u5173\u6ce8\u91cd\u70b9<\/tr>\n<tbody>\n<tr>\n<td>SPI NOR \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>\u4e32\u884c NOR Flash<\/td>\n<td>Quad\/QPI \u63d0\u901f\u3001dummy cycles\u3001XIP\u3001DPD \u4f4e\u529f\u8017<\/td>\n<\/tr>\n<tr>\n<td>SPI NAND \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>\u4e32\u884c NAND Flash<\/td>\n<td>\u9875\/\u5757\u7ba1\u7406\u3001\u7247\u5185 ECC\u3001\u574f\u5757\u8868\u3001\u4e3b\u673a FTL<\/td>\n<\/tr>\n<tr>\n<td>\u5e76\u884cNAND (PPI NAND) \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>8\/16 \u4f4d\u5e76\u884c NAND<\/td>\n<td>\u5bbd\u603b\u7ebf\u65f6\u5e8f\u3001ECC \u5f15\u64ce\u300140&#043; \u5f15\u811a Layout<\/td>\n<\/tr>\n<tr>\n<td>eMMC \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>eMMC 5.0\/5.1<\/td>\n<td>HS200\/HS400\u30011.8 V VCCQ\u3001DS \u9009\u901a\u4e0e\u7b49\u957f<\/td>\n<\/tr>\n<tr>\n<td>SD NAND \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>\u8d34\u7247\u5f0f SD NAND<\/td>\n<td>SPI\/SDIO \u53cc\u6a21\u5f0f\u3001\u65e0\u4f11\u7720\u6307\u4ee4\u3001VCC \u8d1f\u8f7d\u5f00\u5173\u65ad\u7535<\/td>\n<\/tr>\n<tr>\n<td>NAND MCP \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>\u591a\u82af\u7247\u5408\u5c01\u5b58\u50a8<\/td>\n<td>\u591a die \u4e0e\u591a CE\u3001\u53cc\u7535\u6e90\u8f68\u3001HDI \u6247\u51fa<\/td>\n<\/tr>\n<tr>\n<td>\u5e76\u884cNOR (PPI NOR) \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>\u5e76\u884c NOR Flash<\/td>\n<td>\u5f02\u6b65\u8bfb\u65f6\u5e8f\u3001XIP\u3001\u7b49\u5f85\u5468\u671f\u3001\u603b\u7ebf\u6269\u5c55<\/td>\n<\/tr>\n<tr>\n<td>PSRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>\u4f2a\u9759\u6001 RAM<\/td>\n<td>OPI\/HyperBus\u3001\u5237\u65b0\u4e0e\u5ef6\u8fdf\u5468\u671f\u3001XIP \u4e0e\u5e27\u7f13\u5b58<\/td>\n<\/tr>\n<tr>\n<td>DDR2 \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>DDR2 SDRAM<\/td>\n<td>SSTL_18\u3001T \u5206\u652f\u62d3\u6251\u3001VTT \u7aef\u63a5\u3001ODT<\/td>\n<\/tr>\n<tr>\n<td>DDR3 \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>DDR3 \/ DDR3L<\/td>\n<td>Fly-by \u62d3\u6251\u3001write leveling\u3001\u52a8\u6001 ODT<\/td>\n<\/tr>\n<tr>\n<td>DDR4 \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>DDR4 SDRAM<\/td>\n<td>POD12\u3001bank group\u3001DBI\u30012D \u8bad\u7ec3<\/td>\n<\/tr>\n<tr>\n<td>DDR5 \u7535\u8def\u8bbe\u8ba1\u6307\u5357\u00a0\u672c\u6587<\/td>\n<td>DDR5 SDRAM<\/td>\n<td>\u53cc\u5b50\u901a\u9053\u3001On-DIMM PMIC\u3001DFE\u3001\u540c\u5e27 ECC<\/td>\n<\/tr>\n<tr>\n<td>EEPROM \u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/td>\n<td>EEPROM<\/td>\n<td>I\u00b2C\/SPI \u63a5\u53e3\u3001\u4e0a\u62c9\u7535\u963b\u4e0e\u603b\u7ebf\u7535\u5bb9\u3001\u9875\u5199\u4e0e\u5199\u4fdd\u62a4<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>\u5feb\u901f\u51b3\u7b56&#xff1a;DDR4 \/ DDR5 \/ LPDDR5 \/ GDDR \u600e\u4e48\u9009<\/h4>\n<p>\u56db\u7c7b\u6613\u5931\u6027\u5b58\u50a8\u5668\u7684\u5b9a\u4f4d\u5dee\u5f02<\/p>\n<table>\n<tr>\u7ef4\u5ea6DDR4DDR5&#xff08;\u672c\u6587&#xff09;LPDDR5 \/ LPDDR5XGDDR6 \/ GDDR6X<\/tr>\n<tbody>\n<tr>\n<td>\u5b9a\u4f4d<\/td>\n<td>\u4e0a\u4e00\u4ee3\u901a\u7528\u4e3b\u5b58<\/td>\n<td>\u901a\u7528\u4e3b\u5b58 \/ \u670d\u52a1\u5668\u4e3b\u5b58<\/td>\n<td>\u79fb\u52a8\u4e0e\u4f4e\u529f\u8017 SoC \u4e3b\u5b58<\/td>\n<td>\u663e\u5361 \/ AI \u52a0\u901f\u9ad8\u5e26\u5bbd\u663e\u5b58<\/td>\n<\/tr>\n<tr>\n<td>\u4f9b\u7535<\/td>\n<td>VDD\/VDDQ 1.2 V&#xff0c;VPP 2.5 V<\/td>\n<td>VDD\/VDDQ 1.1 V&#xff0c;VPP 1.8 V<\/td>\n<td>VDD1 1.05 V \/ VDD2 0.9 V \/ VDDQ 0.5 V<\/td>\n<td>VDD 1.35 V&#xff0c;VDDQ 1.35 V&#xff08;\u968f\u5382\u5546&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u901a\u9053\u5f62\u6001<\/td>\n<td>\u5355 64 bit&#xff08;&#043;8 ECC &#061; 72&#xff09;<\/td>\n<td>\u53cc 32 bit \u5b50\u901a\u9053&#xff08;\u5404 &#043;8 ECC &#061; 40\u00d72&#xff09;<\/td>\n<td>\u6bcf die 16 bit&#xff0c;\u591a die \u7ec4\u901a\u9053<\/td>\n<td>\u6bcf\u9897\u7c92 32 bit&#xff0c;\u591a\u9897\u7c92\u5e76\u884c<\/td>\n<\/tr>\n<tr>\n<td>\u901f\u7387<\/td>\n<td>1600~3200 MT\/s<\/td>\n<td>3200~8800&#043; MT\/s<\/td>\n<td>5500~10700 MT\/s&#xff08;X \u6863&#xff09;<\/td>\n<td>14~24 Gbps\/pin<\/td>\n<\/tr>\n<tr>\n<td>\u7535\u6e90\u67b6\u6784<\/td>\n<td>\u4e3b\u677f VRM<\/td>\n<td>On-DIMM PMIC&#xff08;\u6a21\u7ec4&#xff09;<\/td>\n<td>PMIC &#043; \u4e3b\u63a7\u5185 DVFS<\/td>\n<td>\u591a\u76f8 VRM &#043; \u663e\u5b58\u7535\u6e90\u5c42<\/td>\n<\/tr>\n<tr>\n<td>\u6210\u672c \/ \u529f\u8017\u654f\u611f<\/td>\n<td>\u6210\u672c\u6700\u4f4e\u3001\u751f\u6001\u6210\u719f<\/td>\n<td>\u5e26\u5bbd\u4e0e\u5bb9\u91cf\u5bc6\u5ea6\u6700\u9ad8<\/td>\n<td>\u6bcf bit \u529f\u8017\u6700\u4f4e<\/td>\n<td>\u5e26\u5bbd\u4f18\u5148\u3001\u529f\u8017\u4e0e\u6210\u672c\u6700\u9ad8<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u51b3\u7b56\u4e00\u53e5\u8bdd&#xff1a;\u9700\u8981\u5927\u5bb9\u91cf &#043; \u9ad8\u5e26\u5bbd &#043; \u670d\u52a1\u5668 RAS \u7279\u6027\u2192 DDR5&#xff1b;\u9700\u8981\u7535\u6c60\u7eed\u822a &#043; \u5c0f\u4f53\u79ef\u2192 LPDDR5\/LPDDR5X&#xff08;\u542b LPCAMM2&#xff09;&#xff1b;\u9700\u8981\u6781\u81f4\u5e26\u5bbd\u2192 GDDR6\/GDDR7&#xff1b;\u6210\u672c\u4f18\u5148\u4e14\u901f\u7387 \u22643200\u2192 DDR4\u3002DDR5 \u7684\u4ee3\u4ef7\u662f\u7535\u6e90\u67b6\u6784\u53d8\u66f4&#xff08;PMIC&#xff09;\u3001\u8bad\u7ec3\u590d\u6742\u5ea6\u4e0a\u5347\u3001Layout \u4e0e SI \u95e8\u69db\u663e\u8457\u63d0\u9ad8&#xff0c;\u82e5\u4e3b\u63a7\u4e0d\u652f\u6301 DDR5 PHY&#xff0c;\u4efb\u4f55\u4f18\u5316\u90fd\u65e0\u6cd5\u5f25\u8865\u3002<\/p>\n<h4>\u672c\u6587\u901f\u89c8&#xff1a;DDR5 \u76f8\u5bf9 DDR4 \u7684\u4e5d\u5904\u672c\u8d28\u53d8\u5316<\/h4>\n<li>\u7535\u538b\u4e0b\u63a2&#xff1a;VDD\/VDDQ \u7531 1.2 V \u964d\u4e3a 1.1 V&#xff0c;VPP \u7531 2.5 V \u964d\u4e3a 1.8 V&#xff0c;AC \u566a\u58f0\u5bb9\u9650\u66f4\u7d27&#xff08;\u00b13% \u91cf\u7ea7&#xff09;\u3002<\/li>\n<li>\u7535\u6e90\u8c03\u8282\u4e0b\u6c89\u5230\u5185\u5b58\u6761&#xff1a;\u6a21\u7ec4\u4e0a\u96c6\u6210 PMIC&#xff08;\u8f93\u5165 5 V \u6216 12 V&#xff09;&#xff0c;\u4e3b\u677f\u4e0d\u518d\u76f4\u63a5\u4f9b\u7ed9 1.1 V\u3002<\/li>\n<li>\u901a\u9053\u62c6\u5206&#xff1a;\u5355\u4e2a DIMM \u62c6\u6210\u4e24\u4e2a\u72ec\u7acb\u7684 32 bit \u5b50\u901a\u9053&#xff08;\u5404\u542b 8 bit \u6821\u9a8c&#xff09;&#xff0c;\u5e76\u884c\u5ea6\u7ffb\u500d\u3002<\/li>\n<li>\u547d\u4ee4\u5730\u5740\u4e32\u884c\u5316&#xff1a;RAS#\/CAS#\/WE#\/ACT# \u53d6\u6d88&#xff0c;\u5168\u90e8\u547d\u4ee4\u7531 CA \u603b\u7ebf\u5728 1~2 \u4e2a\u65f6\u949f\u5185\u4e32\u884c\u4f20\u8f93\u3002<\/li>\n<li>\u7a81\u53d1\u957f\u5ea6\u7ffb\u500d&#xff1a;BL16&#xff08;burst chop \u4e3a BC8&#xff09;&#xff0c;\u9884\u53d6\u7531 8n \u53d8 16n\u3002<\/li>\n<li>Bank \u6570\u7ffb\u500d&#xff1a;8 bank group \u00d7 4 bank &#061; 32 bank&#xff0c;\u914d\u5408 Same-Bank Refresh \u964d\u4f4e\u5237\u65b0\u5f00\u9500\u3002<\/li>\n<li>\u5747\u8861\u4e0e\u8bad\u7ec3\u590d\u6742\u5316&#xff1a;\u5f15\u5165 DFE\u3001\u5185\u90e8 VREF \u8bad\u7ec3\u3001DCA&#xff08;\u5360\u7a7a\u6bd4\u8c03\u6574&#xff09;\u3001CA \u8bad\u7ec3\u3001Loopback \u53cd\u9988\u8bad\u7ec3\u3002<\/li>\n<li>\u5237\u65b0\u7c92\u5ea6\u7ec6\u5316&#xff1a;All-Bank Refresh \/ Same-Bank Refresh&#xff08;REFsb&#xff09;&#043; RFM\/ARFM \u884c\u9524\u6291\u5236\u3002<\/li>\n<li>\u7ba1\u7406\u603b\u7ebf\u5347\u7ea7&#xff1a;SPD Hub &#043; PMIC &#043; TS \u901a\u8fc7 I2C\/I3C&#xff08;HSCL\/HSDA&#xff09;\u7edf\u4e00\u7ba1\u7406&#xff0c;\u652f\u6301\u9065\u6d4b\u3002<\/li>\n<h3>1 \u00b7 \u5668\u4ef6\u57fa\u7840<\/h3>\n<p>\u672c\u8282\u7ed9\u51fa DDR5 \u4e0e DDR4 \u7684\u89c4\u683c\u5bf9\u7167\u3001\u5c01\u88c5\u4e0e\u7403\u4f4d\u5206\u533a\u3001\u4ee5\u53ca\u8bbe\u8ba1\u5fc5\u987b\u9075\u5b88\u7684\u5173\u952e\u7535\u6c14\u53c2\u6570\u3002\u4efb\u4f55\u4e00\u6761\u4e0d\u6ee1\u8db3&#xff0c;\u540e\u7eed Layout \u4e0e\u8bad\u7ec3\u90fd\u65e0\u6cd5\u6551\u56de\u3002<\/p>\n<h4 id=\"s1-1\">1.1 \u89c4\u683c\u5bf9\u6bd4&#xff1a;DDR4 vs DDR5<\/h4>\n<table>\n<tr>\u9879\u76eeDDR4DDR5\u8bbe\u8ba1\u5f71\u54cd<\/tr>\n<tbody>\n<tr>\n<td>VDD \/ VDDQ<\/td>\n<td>1.2 V&#xff08;\u00b13% \/ \u00b15% \u4f9d\u6863\u4f4d&#xff09;<\/td>\n<td>1.1 V&#xff08;AC \u566a\u58f0\u5178\u578b \u00b13%&#xff09;<\/td>\n<td>\u566a\u58f0\u9884\u7b97\u4ece 36 mV \u538b\u5230 33 mV&#xff0c;PDN \u8bbe\u8ba1\u96be\u5ea6\u4e0a\u5347<\/td>\n<\/tr>\n<tr>\n<td>VPP&#xff08;\u5b57\u7ebf\u5347\u538b&#xff09;<\/td>\n<td>2.5 V<\/td>\n<td>1.8 V<\/td>\n<td>\u53ef\u76f4\u63a5\u7531 PMIC \u4e00\u8def\u8f93\u51fa\u4f9b\u7ed9&#xff0c;\u65e0\u9700\u72ec\u7acb\u5347\u538b<\/td>\n<\/tr>\n<tr>\n<td>VDD \u7535\u6e90\u6765\u6e90<\/td>\n<td>\u4e3b\u677f VRM \/ DC-DC<\/td>\n<td>\u6a21\u7ec4\u4e0a PMIC&#xff08;\u677f\u8f7d\u65b9\u6848\u9700\u81ea\u5efa&#xff09;<\/td>\n<td>\u4e3b\u677f\u53ea\u9001 5 V \u6216 12 V&#xff0c;\u9700\u91cd\u65b0\u89c4\u5212\u7535\u6e90\u5c42<\/td>\n<\/tr>\n<tr>\n<td>\u6570\u636e\u901f\u7387<\/td>\n<td>1600~3200 MT\/s<\/td>\n<td>3200~8800&#043; MT\/s<\/td>\n<td>Nyquist \u4ece 1.6 GHz \u5347\u5230 4.4 GHz&#xff0c;\u677f\u6750\u4e0e\u6b8b\u6869\u5fc5\u987b\u5347\u7ea7<\/td>\n<\/tr>\n<tr>\n<td>\u65f6\u949f\u9891\u7387<\/td>\n<td>\u901f\u7387 \/ 2&#xff08;\u6700\u9ad8 1.6 GHz&#xff09;<\/td>\n<td>\u901f\u7387 \/ 2&#xff08;\u6700\u9ad8 4.4 GHz&#xff09;<\/td>\n<td>CK \u6296\u52a8\u8981\u6c42\u66f4\u4e25&#xff0c;\u5dee\u5206 80 \u03a9 \u4e0e\u5bf9\u79f0\u5e03\u7ebf\u662f\u786c\u6307\u6807<\/td>\n<\/tr>\n<tr>\n<td>\u901a\u9053\u7ed3\u6784<\/td>\n<td>1 \u00d7 64 bit&#xff08;ECC \u65f6 72 bit&#xff09;<\/td>\n<td>2 \u00d7 32 bit \u5b50\u901a\u9053&#xff08;\u5404\u5e26 8 bit \u6821\u9a8c&#xff09;<\/td>\n<td>\u4e24\u4e2a\u5b50\u901a\u9053\u53ef\u72ec\u7acb\u5e76\u53d1&#xff0c;\u5e03\u7ebf\u9700\u4e24\u4e24\u5bf9\u79f0<\/td>\n<\/tr>\n<tr>\n<td>\u7a81\u53d1\u957f\u5ea6<\/td>\n<td>BL8 \/ BC4<\/td>\n<td>BL16 \/ BC8<\/td>\n<td>\u4e00\u6b21\u8bbf\u95ee 64 B&#xff08;\u5355\u5b50\u901a\u9053 32 B&#xff09;&#xff0c;\u7f13\u5b58\u884c\u5229\u7528\u7387\u63d0\u9ad8<\/td>\n<\/tr>\n<tr>\n<td>\u9884\u53d6<\/td>\n<td>8n<\/td>\n<td>16n<\/td>\n<td>\u63a7\u5236\u5668\u8c03\u5ea6\u7c92\u5ea6\u53d8\u5316&#xff0c;tCCD \u7b49\u53c2\u6570\u968f\u4e4b\u6539\u53d8<\/td>\n<\/tr>\n<tr>\n<td>Bank \u7ed3\u6784<\/td>\n<td>4 BG \u00d7 4 &#061; 16 bank<\/td>\n<td>8 BG \u00d7 4 &#061; 32 bank<\/td>\n<td>\u5e76\u53d1\u5ea6\u7ffb\u500d&#xff0c;tFAW \/ tRRD \u7ea6\u675f\u9700\u91cd\u65b0\u6838\u7b97<\/td>\n<\/tr>\n<tr>\n<td>\u547d\u4ee4\u5730\u5740<\/td>\n<td>ADDR &#043; RAS#\/CAS#\/WE#\/ACT#<\/td>\n<td>CA[13:0] 14 bit \u4e32\u884c\u603b\u7ebf<\/td>\n<td>\u547d\u4ee4\u5f15\u811a\u51cf\u5c11\u7ea6 20 \u4e2a&#xff0c;\u4f46 CA \u9700 1T\/2T \u8bad\u7ec3<\/td>\n<\/tr>\n<tr>\n<td>\u7247\u5185 ECC<\/td>\n<td>\u65e0&#xff08;\u90e8\u5206\u5382\u5546\u79c1\u6709&#xff09;<\/td>\n<td>\u6709&#xff08;on-die ECC&#xff0c;\u900f\u660e&#xff0c;\u4e0d\u5360\u5f15\u811a&#xff09;<\/td>\n<td>\u9635\u5217\u53ef\u9760\u6027\u63d0\u5347&#xff0c;\u4f46\u4e0d\u7b49\u4e8e\u7cfb\u7edf\u7ea7 SECDED<\/td>\n<\/tr>\n<tr>\n<td>\u7cfb\u7edf\u7ea7 ECC<\/td>\n<td>x72 \u6a21\u7ec4&#xff08;64&#043;8&#xff09;<\/td>\n<td>\u6bcf\u5b50\u901a\u9053 32&#043;8&#xff0c;\u53cc\u901a\u9053\u5171 80 bit \u94fe\u8def<\/td>\n<td>\u300c\u540c\u5e27 ECC\u300d&#xff1a;\u6821\u9a8c\u4e0e\u6570\u636e\u540c\u5e27\u4f20\u8f93&#xff0c;\u4e0d\u6269\u5c55\u5916\u90e8\u6570\u636e\u5bbd\u5ea6<\/td>\n<\/tr>\n<tr>\n<td>\u5747\u8861<\/td>\n<td>CTLE&#xff08;\u63a7\u5236\u5668\u4fa7&#xff09;\u3001\u65e0 DFE<\/td>\n<td>\u63a7\u5236\u5668 CTLE\/DFE &#043; DRAM \u4fa7 DFE<\/td>\n<td>\u8bad\u7ec3\u9879\u589e\u52a0&#xff0c;\u4e0a\u7535\u8bad\u7ec3\u65f6\u95f4\u663e\u8457\u53d8\u957f<\/td>\n<\/tr>\n<tr>\n<td>ODT<\/td>\n<td>RTT_NOM \/ RTT_WR \/ RTT_PARK<\/td>\n<td>RTT_NOM_RD \/ RTT_NOM_WR \/ RTT_WR \/ RTT_PARK<\/td>\n<td>\u8bfb\u5199\u7aef\u63a5\u53ef\u5206\u522b\u8bbe\u7f6e&#xff0c;\u5199\u773c\u56fe\u8c03\u8bd5\u7a7a\u95f4\u66f4\u5927<\/td>\n<\/tr>\n<tr>\n<td>ZQ \u6821\u51c6\u7535\u963b<\/td>\n<td>240 \u03a9 \u00b11%<\/td>\n<td>240 \u03a9 \u00b11%&#xff08;\u4f4e\u5bc4\u751f\u5e03\u5c40&#xff09;<\/td>\n<td>\u5fc5\u987b\u9760\u8fd1 ZQ \u5f15\u811a&#xff0c;\u8d70\u7ebf \u2264 5 mm&#xff0c;\u7981\u6b62\u8fc7\u5b54<\/td>\n<\/tr>\n<tr>\n<td>\u5237\u65b0<\/td>\n<td>All-Bank Refresh<\/td>\n<td>All-Bank &#043; Same-Bank&#xff08;REFsb&#xff09;<\/td>\n<td>\u5237\u65b0\u53ef\u53ea\u9488\u5bf9\u90e8\u5206 bank&#xff0c;\u964d\u4f4e\u6027\u80fd\u6296\u52a8<\/td>\n<\/tr>\n<tr>\n<td>\u544a\u8b66 \/ \u8bad\u7ec3\u5f15\u811a<\/td>\n<td>ALERT_n&#xff08;\u90e8\u5206&#xff09;\u3001PARITY<\/td>\n<td>ALERT_n\u3001TEN\u3001Loopback \u53cd\u9988<\/td>\n<td>\u7ba1\u7406\u4fa7\u9700\u589e\u52a0\u4e0a\u62c9\u4e0e\u6d4b\u8bd5\u70b9<\/td>\n<\/tr>\n<tr>\n<td>\u6a21\u7ec4\u7ba1\u7406<\/td>\n<td>SPD EEPROM&#xff08;I2C&#xff09;<\/td>\n<td>SPD Hub &#043; PMIC &#043; TS&#xff08;I2C\/I3C&#xff09;<\/td>\n<td>\u9700 3.3 V \u7ba1\u7406\u7535\u6e90\u4e0e\u4e0a\u62c9&#xff0c;\u652f\u6301\u9065\u6d4b\u4e0e\u70ed\u8282\u6d41<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u6700\u5bb9\u6613\u8e29\u7684\u5751&#xff1a;\u628a DDR5 \u5f53\u300c\u66f4\u5feb\u7684 DDR4\u300d\u6765\u753b<\/p>\n<p>DDR5 \u4e0d\u662f DDR4 \u7684\u63d0\u901f\u7248\u3002\u82e5\u6cbf\u7528 DDR4 \u7684\u7535\u6e90\u6811&#xff08;\u4e3b\u677f\u76f4\u4f9b 1.1 V \u7ed9\u63d2\u69fd&#xff09;\u3001\u6cbf\u7528 DDR4 \u7684 1.6 GHz \u8d70\u7ebf\u89c4\u5219\u3001\u6216\u7528 DDR4 \u7684\u7b49\u957f\u516c\u5dee&#xff08;\u00b125 mil \u7ec4\u95f4&#xff09;&#xff0c;\u5728 6400 MT\/s \u4e0a\u5927\u6982\u7387\u8868\u73b0\u4e3a\u8bad\u7ec3\u5931\u8d25\u3001\u53ea\u80fd\u964d\u901f\u5230 3600\/4000\u3001\u6216\u9ad8\u6e29\u73af\u5883\u968f\u673a ECC \u62a5\u9519\u3002\u7535\u6e90\u67b6\u6784\u3001\u53e0\u5c42\u677f\u6750\u3001\u7b49\u957f\u516c\u5dee\u3001\u8bad\u7ec3\u9879\u56db\u7c7b\u5fc5\u987b\u540c\u6b65\u5347\u7ea7\u3002<\/p>\n<h4 id=\"s1-2\">1.2 \u5c01\u88c5\u4e0e\u7403\u4f4d\u5b9a\u4e49<\/h4>\n<table>\n<tr>\u5f62\u6001\u5c01\u88c5\u5178\u578b\u5c3a\u5bf8\u7403\u8ddd \/ \u7403\u6570\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>DDR5 \u9897\u7c92 x8<\/td>\n<td>FBGA-82<\/td>\n<td>9.0 \u00d7 11.0 mm&#xff08;\u5178\u578b&#xff09;<\/td>\n<td>0.8 mm \/ 82 ball<\/td>\n<td>\u677f\u8f7d&#xff08;down&#xff09;\u65b9\u6848\u4e3b\u6d41&#xff1b;\u5355\u9897 x8&#xff0c;\u9700 4 \u9897\u7ec4 32 bit \u5b50\u901a\u9053<\/td>\n<\/tr>\n<tr>\n<td>DDR5 \u9897\u7c92 x16<\/td>\n<td>FBGA-102<\/td>\n<td>9.0 \u00d7 14.0 mm&#xff08;\u5178\u578b&#xff09;<\/td>\n<td>0.8 mm \/ 102 ball<\/td>\n<td>2 \u9897\u7ec4 32 bit&#xff1b;\u7403\u6570\u5c11\u3001\u5e03\u5c40\u53cb\u597d&#xff0c;\u4f46\u53ef\u9009\u578b\u53f7\u5c11<\/td>\n<\/tr>\n<tr>\n<td>DDR5 \u9897\u7c92 x4<\/td>\n<td>FBGA-82 \/ 96<\/td>\n<td>9.0 \u00d7 11.0 mm&#xff08;\u5178\u578b&#xff09;<\/td>\n<td>0.8 mm<\/td>\n<td>\u591a\u89c1\u4e8e\u670d\u52a1\u5668\u9ad8\u5bc6\u5ea6 RDIMM&#xff08;8 \u9897\u7ec4 32 bit&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>UDIMM \/ RDIMM<\/td>\n<td>288 pin \u91d1\u624b\u6307<\/td>\n<td>133.35 \u00d7 31.25 mm<\/td>\n<td>0.85 mm pin pitch<\/td>\n<td>\u53cc\u9762\u5b50\u901a\u9053\u5206\u533a&#xff0c;\u4e2d\u90e8\u5361\u53e3\u9632\u5446<\/td>\n<\/tr>\n<tr>\n<td>SODIMM<\/td>\n<td>262 pin \u91d1\u624b\u6307<\/td>\n<td>69.6 \u00d7 30.0 mm<\/td>\n<td>0.5 mm pin pitch<\/td>\n<td>\u7b14\u8bb0\u672c \/ \u8fb9\u7f18\u8bbe\u5907&#xff0c;\u540c\u6837\u53cc 40 bit \u5b50\u901a\u9053<\/td>\n<\/tr>\n<tr>\n<td>CAMM2 \/ LPCAMM2<\/td>\n<td>\u538b\u7f29\u8fde\u63a5\u5668&#xff08;LGA \u5f0f&#xff09;<\/td>\n<td>\u7ea6 78 \u00d7 30 mm<\/td>\n<td>0.85 mm \u7f51\u683c<\/td>\n<td>\u66f4\u4f4e\u9ad8\u5ea6\u3001\u66f4\u77ed\u8d70\u7ebf&#xff0c;\u53ef\u8dd1\u66f4\u9ad8\u901f\u7387&#xff1b;\u9700\u4e13\u7528\u8fde\u63a5\u5668<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>DDR5 \u5c01\u88c5\u4e0e 288 pin \u6a21\u7ec4\u4fe1\u53f7\u5206\u533a&#xff08;\u793a\u610f&#xff09;\u2460 DDR5 \u9897\u7c92 FBGA-82&#xff08;x8&#xff0c;0.8 mm \u7403\u8ddd&#xff09;A19.0 mm&#xff08;\u5217\u65b9\u5411&#xff09;\u7403\u4f4d\u5206\u533a\u56fe\u4f8bDQ[7:0] \/ DQS_t\u00b7DQS_c \/ DM_n&#xff08;\u6570\u636e\u7ec4&#xff0c;8 \u4f4d &#043; 1 \u5bf9\u9009\u901a &#043; 1 \u63a9\u7801&#xff09;CA[13:0] \/ CS_n \/ CK_t\u00b7CK_c&#xff08;\u547d\u4ee4\u5730\u5740\u4e0e\u65f6\u949f&#xff0c;\u4e32\u884c\u5316\u547d\u4ee4&#xff09;VDD \/ VDDQ 1.1 V&#xff08;\u4e3b\u7535\u6e90\u4e0e I\/O \u7535\u6e90&#xff0c;\u6570\u91cf\u6700\u591a&#xff09;VSS \/ VSSQ&#xff08;\u5730&#xff0c;\u4e0e\u7535\u6e90\u7403 1:1 \u4ea4\u9519\u5e03\u7f6e\u964d\u4f4e\u56de\u8def\u7535\u611f&#xff09;VPP 1.8 V \/ ZQ \/ ALERT_n \/ RESET_n \/ TEN \/ Loopback \/ NC\u2461 288 pin UDIMM \/ RDIMM \u91d1\u624b\u6307\u5206\u533a&#xff08;\u6b63\u53cd\u9762\u5408\u8ba1&#xff09;\u5361\u53e3 Notch&#xff08;\u9632\u5446&#xff09;VDD \/ VDDQ \/ VSS&#xff08;1.1 V \u4e3b\u7535\u6e90\u4e0e\u5730&#xff09;\u2248 120 pinVPP 1.8 V&#xff08;\u7531 On-DIMM PMIC \u4ea7\u751f&#xff0c;\u677f\u4e0a\u4e0d\u518d\u76f4\u4f9b&#xff09;\u2248 12 pinCK_A_t \/ CK_A_c&#xff08;\u5b50\u901a\u9053 A \u5dee\u5206\u65f6\u949f&#xff09;2 pinCA_A[13:0] &#043; CS_A_n&#xff08;\u5b50\u901a\u9053 A \u547d\u4ee4\u5730\u5740\u603b\u7ebf&#xff09;15 pinDQ_A[31:0] &#043; DQS_A_t\/c \u00d74 &#043; DM_A_n \u00d74&#xff08;\u6570\u636e\u7ec4&#xff09;52 pinCB_A[7:0]&#xff08;\u5b50\u901a\u9053 A \u6821\u9a8c\u4f4d&#xff0c;\u4e0e 32 bit \u6570\u636e\u540c\u5e27&#xff09;8 pinCK_B \/ CA_B[13:0] \/ CS_B_n&#xff08;\u5b50\u901a\u9053 B \u547d\u4ee4\u65f6\u949f&#xff0c;\u5b8c\u5168\u72ec\u7acb&#xff09;17 pinDQ_B[31:0] &#043; DQS_B_t\/c \u00d74 &#043; DM_B_n \u00d74&#xff08;\u6570\u636e\u7ec4&#xff09;52 pinCB_B[7:0]&#xff08;\u5b50\u901a\u9053 B \u6821\u9a8c\u4f4d&#xff09;8 pinALERT_n \/ RESET_n \/ TEN \/ Loopback&#xff08;\u5f00\u6f0f\u9700\u4e0a\u62c9&#xff09;\u2248 6 pinHSCL \/ HSDA&#xff08;I2C\/I3C \u7ba1\u7406\u603b\u7ebf \u2192 SPD Hub &#043; PMIC &#043; TS&#xff09;2 pinSA0~SA2 \/ \u4fdd\u7559 \/ \u673a\u68b0\u68c0\u6d4b&#xff08;\u5730\u5740\u9009\u62e9\u4e0e\u5728\u4f4d\u68c0\u6d4b&#xff09;\u2248 6 pin\u25b6 UDIMM \/ SODIMM&#xff1a;\u4e3b\u63a7\u76f4\u8fde\u9897\u7c92&#xff08;\u4ec5\u5730\u5740\u65f6\u949f\u8d70 Fly-by&#xff09;&#xff1b;\u25b6 RDIMM&#xff1a;CK \/ CA \/ CS \u7ecf RCD \u5bc4\u5b58\u518d\u9a71\u52a8&#xff1b;LRDIMM \u53e6\u52a0 DB \u7f13\u51b2 DQ\u3002\u25b6 \u4e24\u4e2a\u5b50\u901a\u9053\u5404\u81ea\u72ec\u7acb\u8bad\u7ec3&#xff0c;\u4e3b\u63a7\u5fc5\u987b\u5206\u522b\u5b8c\u6210 write\/read leveling \u4e0e VREF\u3002\u6ce8&#xff1a;pin \u6570\u4e0e\u5206\u7ec4\u4e3a\u793a\u610f&#xff0c;\u786e\u5207\u5206\u5e03\u4ee5 JEDEC \u6a21\u7ec4\u89c4\u8303\u4e0e\u76ee\u6807\u578b\u53f7 datasheet \u4e3a\u51c6\u3002<\/p>\n<p>\u56fe 1-1\u3000DDR5 \u9897\u7c92 FBGA-82 \u7403\u4f4d\u5206\u533a&#xff08;\u542b A1 \u6807\u8bb0&#xff09;\u4e0e 288 pin \u6a21\u7ec4\u4fe1\u53f7\u5206\u533a&#xff1a;\u4e24\u4e2a\u5b50\u901a\u9053\u5404 40 bit&#xff08;32 DQ &#043; 8 CB&#xff09;&#xff0c;\u547d\u4ee4\u4e0e\u65f6\u949f\u5b8c\u5168\u72ec\u7acb<\/p>\n<h4 id=\"s1-3\">1.3 \u5173\u952e\u7535\u6c14\u53c2\u6570<\/h4>\n<table>\n<tr>\u53c2\u6570\u7b26\u53f7\u5178\u578b\u503c \/ \u8303\u56f4\u8bf4\u660e\u4e0e\u8bbe\u8ba1\u7ea6\u675f<\/tr>\n<tbody>\n<tr>\n<td>\u6838\u5fc3 \/ I\/O \u7535\u538b<\/td>\n<td>VDD \/ VDDQ<\/td>\n<td>1.1 V&#xff08;AC \u566a\u58f0 \u00b13% \u91cf\u7ea7&#xff09;<\/td>\n<td>\u542b DC \u8bef\u5dee &#043; \u7eb9\u6ce2 &#043; \u566a\u58f0\u7684\u603b\u5bb9\u5dee\u6309\u76ee\u6807\u578b\u53f7&#xff1b;1.1 V \u4e0b 33 mV \u662f\u5168\u90e8\u9884\u7b97<\/td>\n<\/tr>\n<tr>\n<td>\u5b57\u7ebf\u5347\u538b<\/td>\n<td>VPP<\/td>\n<td>1.8 V&#xff08;\u00b15% \u91cf\u7ea7&#xff09;<\/td>\n<td>\u7535\u6d41\u5f88\u5c0f&#xff08;mA \u7ea7&#xff09;&#xff0c;\u4f46\u5bf9\u566a\u58f0\u654f\u611f&#xff0c;\u9700\u72ec\u7acb\u53bb\u8026\u4e0e\u77ed\u8d70\u7ebf<\/td>\n<\/tr>\n<tr>\n<td>I\/O \u7535\u5e73\u6807\u51c6<\/td>\n<td>\u2014<\/td>\n<td>PODL&#xff08;\u7aef\u63a5\u5230 VDDQ&#xff09;<\/td>\n<td>\u4e0e DDR4 \u7684 POD12 \u540c\u4e3a\u4f2a\u5f00\u6f0f&#xff0c;\u9ad8\u7535\u5e73\u7531\u7aef\u63a5\u4e0a\u62c9\u5efa\u7acb<\/td>\n<\/tr>\n<tr>\n<td>\u8f93\u5165\u53c2\u8003\u7535\u538b<\/td>\n<td>VREF<\/td>\n<td>\u5185\u90e8\u751f\u6210&#xff0c;\u591a\u6863 MR \u53ef\u8c03<\/td>\n<td>DDR5 \u5185\u90e8 VREF \u8bad\u7ec3\u8303\u56f4\u66f4\u5bbd&#xff0c;\u9700\u6309\u8bad\u7ec3\u7ed3\u679c\u9501\u5b9a<\/td>\n<\/tr>\n<tr>\n<td>\u5dee\u5206\u65f6\u949f\u9891\u7387<\/td>\n<td>fCK<\/td>\n<td>1.6 ~ 4.4 GHz<\/td>\n<td>\u7b49\u4e8e\u6570\u636e\u901f\u7387\u7684\u4e00\u534a&#xff1b;\u6296\u52a8&#xff08;RMS&#xff09;\u8981\u6c42\u968f\u901f\u7387\u6536\u7d27<\/td>\n<\/tr>\n<tr>\n<td>CA \u603b\u7ebf\u901f\u7387<\/td>\n<td>\u2014<\/td>\n<td>SDR &#064; fCK&#xff08;1T \/ 2T \u547d\u4ee4&#xff09;<\/td>\n<td>\u547d\u4ee4\u5728 1 \u6216 2 \u4e2a CK \u5468\u671f\u5185\u4e32\u884c\u53d1\u5b8c<\/td>\n<\/tr>\n<tr>\n<td>\u5355\u7aef\u963b\u6297&#xff08;DQ \/ CA \/ DM&#xff09;<\/td>\n<td>Z0<\/td>\n<td>40 \u03a9 \u00b110%<\/td>\n<td>\u90e8\u5206\u5e73\u53f0\u4e3a 40 \u03a9&#xff1b;\u4ee5\u4e3b\u63a7 PDG \u4e3a\u51c6&#xff0c;\u4e0d\u53ef\u6cbf\u7528 DDR3 \u7684 50 \u03a9<\/td>\n<\/tr>\n<tr>\n<td>\u5dee\u5206\u963b\u6297&#xff08;CK \/ DQS&#xff09;<\/td>\n<td>Zdiff<\/td>\n<td>80 \u03a9 \u00b110%<\/td>\n<td>\u5dee\u5206\u5bf9\u5185\u7b49\u957f \u00b11~2 mil&#xff0c;\u7981\u6b62\u8de8\u5206\u5272<\/td>\n<\/tr>\n<tr>\n<td>ZQ \u6821\u51c6\u7535\u963b<\/td>\n<td>RZQ<\/td>\n<td>240 \u03a9 \u00b11%&#xff08;\u4f4e\u5bc4\u751f&#xff09;<\/td>\n<td>\u8d34\u88c5\u8ddd ZQ \u5f15\u811a \u2264 5 mm&#xff0c;\u8d70\u7ebf\u4e0d\u52a0\u8fc7\u5b54&#xff0c;\u5305\u5730\u5904\u7406<\/td>\n<\/tr>\n<tr>\n<td>\u7247\u5185\u7aef\u63a5<\/td>\n<td>RTT<\/td>\n<td>240 \/ 120 \/ 80 \/ 60 \/ 48 \/ 40 \/ 34 \u03a9 \u7b49<\/td>\n<td>DDR5 \u5c06 Nominal \u62c6\u4e3a RD \/ WR \u4e24\u7c7b&#xff0c;\u89c1\u7b2c 7 \u7ae0<\/td>\n<\/tr>\n<tr>\n<td>\u5237\u65b0\u95f4\u9694<\/td>\n<td>tREFI<\/td>\n<td>3.9 \u00b5s&#xff08;\u226485 \u00b0C&#xff09;<\/td>\n<td>DDR4 \u4e3a 7.8 \u00b5s&#xff1b;&gt;85 \u00b0C \u65f6\u5178\u578b\u6298\u534a\u4e3a 1.95 \u00b5s<\/td>\n<\/tr>\n<tr>\n<td>\u5237\u65b0\u547d\u4ee4\u5468\u671f<\/td>\n<td>tRFC1 \/ tRFC2 \/ tRFCsb<\/td>\n<td>\u7ea6 295 \/ 160 \/ 130 ns&#xff08;16 Gb \u91cf\u7ea7&#xff09;<\/td>\n<td>\u968f\u5bc6\u5ea6\u663e\u8457\u53d8\u5316&#xff1b;REFsb \u53ea\u5237\u65b0\u5355 bank&#xff0c;\u5ef6\u8fdf\u6700\u77ed<\/td>\n<\/tr>\n<tr>\n<td>\u5de5\u4f5c\u6e29\u5ea6&#xff08;\u9897\u7c92&#xff09;<\/td>\n<td>Tcase<\/td>\n<td>0 ~ 85 \u00b0C&#xff08;\u5546\u4e1a&#xff09;&#xff1b;-40 ~ 95 \u00b0C&#xff08;\u5de5\u6e29\/\u8f66\u89c4&#xff09;<\/td>\n<td>&gt;85 \u00b0C \u89e6\u53d1 2\u00d7 \u5237\u65b0\u7387\u4e0e\u70ed\u8282\u6d41&#xff0c;\u5e26\u5bbd\u4e0b\u964d<\/td>\n<\/tr>\n<tr>\n<td>\u5b58\u50a8\u6e29\u5ea6<\/td>\n<td>Tstg<\/td>\n<td>-55 ~ 100 \u00b0C<\/td>\n<td>\u8fd0\u8f93\u4e0e\u4ed3\u50a8\u9700\u63a7\u5236\u6e7f\u5ea6&#xff08;MSL \u7ba1\u63a7&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>ALERT_n \u4e0a\u62c9<\/td>\n<td>\u2014<\/td>\n<td>\u5178\u578b 4.7 ~ 10 k\u03a9 \u5230 1.1 V \u6216\u7ba1\u7406\u7535\u6e90<\/td>\n<td>\u5f00\u6f0f\u8f93\u51fa&#xff0c;\u591a\u5668\u4ef6\u7ebf\u4e0e&#xff1b;\u4e0a\u62c9\u7535\u6e90\u57df\u4ee5 datasheet \u4e3a\u51c6<\/td>\n<\/tr>\n<tr>\n<td>RESET_n<\/td>\n<td>\u2014<\/td>\n<td>\u4f4e\u6709\u6548&#xff0c;\u4e0a\u7535\u671f\u95f4\u9700\u4fdd\u6301\u4f4e \u2265 \u89c4\u5b9a\u65f6\u95f4<\/td>\n<td>\u677f\u8f7d\u65b9\u6848\u5efa\u8bae 1~10 k\u03a9 \u4e0b\u62c9 &#043; \u4e3b\u63a7 GPIO \u53ef\u63a7\u4e0a\u62c9<\/td>\n<\/tr>\n<tr>\n<td>ESD \u7b49\u7ea7<\/td>\n<td>HBM \/ CDM<\/td>\n<td>HBM \u2265 1000 V&#xff1b;CDM \u2265 250 V&#xff08;\u5178\u578b&#xff09;<\/td>\n<td>\u9ad8\u901f\u5f15\u811a ESD \u5668\u4ef6\u7ed3\u7535\u5bb9\u9700 \u2264 0.3 pF \u7ea7\u6216\u5e72\u8106\u4e0d\u52a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u4e0a\u8868\u4e2d\u7684\u963b\u6297\u3001\u7aef\u63a5\u4e0e\u65f6\u5e8f\u503c\u4f1a\u968f\u4ee3\u9645\u4e0e\u5382\u5546\u4fee\u8ba2\u800c\u53d8&#xff1b;\u4e3b\u63a7\u63d0\u4f9b\u7684 PDG&#xff08;Processor Design Guide \/ DDR Design Guide&#xff09;\u4f18\u5148\u7ea7\u9ad8\u4e8e\u672c\u6587&#xff0c;\u51b2\u7a81\u65f6\u4ee5 PDG \u4e3a\u51c6\u3002<\/p>\n<h3>2 \u00b7 \u63a5\u53e3\u4e0e\u534f\u8bae<\/h3>\n<p>DDR5 \u6700\u5927\u7684\u534f\u8bae\u53d8\u5316\u662f\u300c\u547d\u4ee4\u5730\u5740\u4e32\u884c\u5316\u300d&#xff1a;\u4f20\u7edf RAS#\/CAS#\/WE#\/ACT# \u5f15\u811a\u88ab\u53d6\u6d88&#xff0c;\u6240\u6709\u547d\u4ee4\u7531 14 bit CA \u603b\u7ebf\u5728 1~2 \u4e2a CK \u5468\u671f\u5185\u4e32\u884c\u53d1\u9001\u3002\u8fd9\u4e00\u6539\u52a8\u628a\u5f15\u811a\u6570\u964d\u4e0b\u6765\u7684\u540c\u65f6&#xff0c;\u628a\u65f6\u5e8f\u7ea6\u675f\u4e0e\u8bad\u7ec3\u8d23\u4efb\u8f6c\u79fb\u5230\u4e86\u63a7\u5236\u5668\u4e0e Layout\u3002<\/p>\n<h4 id=\"s2-1\">2.1 \u5b8c\u6574\u4fe1\u53f7\u5b9a\u4e49<\/h4>\n<table>\n<tr>\u4fe1\u53f7\u65b9\u5411\u7c7b\u578b \/ \u7535\u5e73\u6570\u91cf&#xff08;x8 \u5355\u9897\u7c92&#xff09;\u529f\u80fd\u4e0e\u8bbe\u8ba1\u8981\u70b9<\/tr>\n<tbody>\n<tr>\n<td>CK_t \/ CK_c<\/td>\n<td>\u4e3b\u63a7\u2192DRAM<\/td>\n<td>\u5dee\u5206&#xff0c;80 \u03a9<\/td>\n<td>1 \u5bf9<\/td>\n<td>\u547d\u4ee4\u4e0e\u5730\u5740\u7684\u65f6\u5e8f\u57fa\u51c6&#xff1b;\u9891\u7387 &#061; \u901f\u7387\/2\u3002\u5dee\u5206\u5bf9\u5185\u7b49\u957f \u00b11~2 mil&#xff0c;\u7981\u6b62\u5728\u9014\u4e2d\u5206\u53c9<\/td>\n<\/tr>\n<tr>\n<td>CA[13:0]<\/td>\n<td>\u4e3b\u63a7\u2192DRAM<\/td>\n<td>\u5355\u7aef 40 \u03a9&#xff0c;SDR<\/td>\n<td>14<\/td>\n<td>\u547d\u4ee4 &#043; \u5730\u5740 &#043; Bank\/BG \u590d\u7528\u603b\u7ebf&#xff1b;\u90e8\u5206\u547d\u4ee4\u9700 2 \u4e2a CK&#xff08;2T&#xff09;\u3002\u7ec4\u5185\u7b49\u957f&#xff0c;Fly-by \u672b\u7aef\u7aef\u63a5<\/td>\n<\/tr>\n<tr>\n<td>CS_n<\/td>\n<td>\u4e3b\u63a7\u2192DRAM<\/td>\n<td>\u5355\u7aef 40 \u03a9<\/td>\n<td>1&#xff08;3DS \u4e3a CS_n_A \/ CS_n_B&#xff09;<\/td>\n<td>\u7247\u9009\u517c\u547d\u4ee4\u6709\u6548\u6027\u6307\u793a&#xff1b;\u591a rank \u65f6\u6bcf\u4e2a rank \u4e00\u6839&#xff0c;\u968f Fly-by \u987a\u5e8f\u6392\u5217<\/td>\n<\/tr>\n<tr>\n<td>DQ[7:0]&#xff08;x8&#xff09;<\/td>\n<td>\u53cc\u5411<\/td>\n<td>PODL \u5355\u7aef 40 \u03a9<\/td>\n<td>8<\/td>\n<td>\u6570\u636e\u4f4d&#xff1b;4 \u9897 x8 \u7ec4 32 bit \u5b50\u901a\u9053\u3002\u7ec4\u5185\u4e0e DQS \u7b49\u957f \u00b13~5 mil<\/td>\n<\/tr>\n<tr>\n<td>DQS_t \/ DQS_c<\/td>\n<td>\u53cc\u5411<\/td>\n<td>\u5dee\u5206 80 \u03a9<\/td>\n<td>1 \u5bf9 \/ \u5b57\u8282\u7ec4<\/td>\n<td>\u6570\u636e\u9009\u901a&#xff1b;\u8bfb\u5199\u53cc\u5411&#xff0c;\u8bfb\u65f6\u7531 DRAM \u53d1\u51fa&#xff08;\u4e0e DQ \u8fb9\u6cbf\u5bf9\u9f50\u2192\u4e3b\u63a7\u505a read leveling&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>DM_n&#xff08;x8\/x16&#xff09;<\/td>\n<td>\u4e3b\u63a7\u2192DRAM<\/td>\n<td>\u5355\u7aef 40 \u03a9<\/td>\n<td>1 \/ \u5b57\u8282\u7ec4<\/td>\n<td>\u5199\u6570\u636e\u63a9\u7801&#xff1b;x16 \u53ef\u80fd\u4e3a DM_n\/DBI_n \u590d\u7528\u3002\u4e0e\u540c\u7ec4 DQ \u7b49\u957f<\/td>\n<\/tr>\n<tr>\n<td>CB[7:0]&#xff08;\u6a21\u7ec4&#xff09;<\/td>\n<td>\u53cc\u5411<\/td>\n<td>PODL \u5355\u7aef 40 \u03a9<\/td>\n<td>8 \/ \u5b50\u901a\u9053<\/td>\n<td>\u6821\u9a8c\u4f4d&#xff08;check bits&#xff09;&#xff0c;\u4e0e 32 bit \u6570\u636e\u540c\u5e27\u4f20\u8f93&#xff0c;\u4f9b\u4e3b\u63a7\u505a SECDED\u3002\u677f\u8f7d\u65b9\u6848\u82e5\u4e3b\u63a7\u4e0d\u7528\u5219\u6309 NC\/\u63a5\u5730\u5904\u7406&#xff08;\u4f9d datasheet&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>ALERT_n<\/td>\n<td>DRAM\u2192\u4e3b\u63a7<\/td>\n<td>\u5f00\u6f0f\u8f93\u51fa&#xff0c;\u9700\u4e0a\u62c9<\/td>\n<td>1<\/td>\n<td>CRC \u9519\u8bef\u3001\u547d\u4ee4\/\u5730\u5740\u5947\u5076\u9519\u8bef\u3001\u6e29\u5ea6\u4e8b\u4ef6\u5171\u7528\u7684\u544a\u8b66\u7ebf\u3002\u4f4e\u6709\u6548&#xff0c;\u591a\u5668\u4ef6\u7ebf\u4e0e<\/td>\n<\/tr>\n<tr>\n<td>RESET_n<\/td>\n<td>\u4e3b\u63a7\u2192DRAM<\/td>\n<td>\u5355\u7aef&#xff0c;\u4f4e\u6709\u6548<\/td>\n<td>1<\/td>\n<td>\u4e0a\u7535\u4e0e\u5f02\u5e38\u6062\u590d\u590d\u4f4d&#xff1b;\u9700\u5728 VDD \u7a33\u5b9a\u540e\u4fdd\u6301\u4f4e\u7535\u5e73\u8db3\u591f\u65f6\u95f4\u518d\u91ca\u653e<\/td>\n<\/tr>\n<tr>\n<td>TEN<\/td>\n<td>\u4e3b\u63a7\u2192DRAM<\/td>\n<td>\u5355\u7aef&#xff0c;\u9ad8\u6709\u6548<\/td>\n<td>1<\/td>\n<td>\u6d4b\u8bd5 \/ \u8fde\u901a\u6027\u6d4b\u8bd5\u6a21\u5f0f\u4f7f\u80fd&#xff08;Test Enable&#xff09;\u3002\u6b63\u5e38\u8fd0\u884c\u65f6\u4fdd\u6301\u65e0\u6548\u7535\u5e73&#xff0c;\u5efa\u8bae\u9884\u7559\u4e0b\u62c9<\/td>\n<\/tr>\n<tr>\n<td>Loopback&#xff08;\u53cd\u9988\u8f93\u51fa&#xff09;<\/td>\n<td>DRAM\u2192\u4e3b\u63a7<\/td>\n<td>\u5355\u7aef \/ \u4e13\u7528\u53cd\u9988<\/td>\n<td>1~2&#xff08;\u4f9d\u578b\u53f7&#xff09;<\/td>\n<td>\u8bad\u7ec3\u53cd\u9988\u901a\u9053&#xff0c;\u628a DRAM \u5185\u90e8\u91c7\u6837\u5230\u7684\u65f6\u949f\/\u6570\u636e\u76f8\u4f4d\u56de\u4f20\u4e3b\u63a7&#xff0c;\u7528\u4e8e Loopback \u8bad\u7ec3\u4e0e DFE \u6536\u655b<\/td>\n<\/tr>\n<tr>\n<td>ZQ<\/td>\n<td>\u5916\u63a5\u7535\u963b<\/td>\n<td>\u6a21\u62df<\/td>\n<td>1<\/td>\n<td>\u5916\u63a5 240 \u03a9 \u00b11% \u7cbe\u5bc6\u7535\u963b&#xff0c;\u4f5c\u4e3a ODT \u4e0e\u9a71\u52a8\u5f3a\u5ea6\u6821\u51c6\u57fa\u51c6<\/td>\n<\/tr>\n<tr>\n<td>VDD \/ VDDQ<\/td>\n<td>\u7535\u6e90<\/td>\n<td>1.1 V<\/td>\n<td>\u591a\u7403<\/td>\n<td>\u6838\u5fc3\u4e0e I\/O \u7535\u6e90&#xff0c;\u901a\u5e38\u540c\u7535\u4f4d\u3001\u540c\u5c42\u94dc\u76ae&#xff0c;\u5206\u522b\u53bb\u8026<\/td>\n<\/tr>\n<tr>\n<td>VPP<\/td>\n<td>\u7535\u6e90<\/td>\n<td>1.8 V<\/td>\n<td>1~2 \u7403<\/td>\n<td>\u5b57\u7ebf\u5347\u538b&#xff1b;\u7535\u6d41\u5c0f\u4f46\u5bf9\u566a\u58f0\u654f\u611f&#xff0c;\u9760\u8fd1\u9897\u7c92\u653e\u7f6e 0.1 \u00b5F<\/td>\n<\/tr>\n<tr>\n<td>VSS \/ VSSQ<\/td>\n<td>\u5730<\/td>\n<td>0 V<\/td>\n<td>\u591a\u7403<\/td>\n<td>\u4e0e\u7535\u6e90\u7403\u4ea4\u9519&#xff0c;\u4fdd\u8bc1\u6bcf\u4e2a\u6570\u636e\u7403\u65c1\u6709\u56de\u6d41\u5730\u5b54<\/td>\n<\/tr>\n<tr>\n<td>HSCL \/ HSDA&#xff08;\u6a21\u7ec4&#xff09;<\/td>\n<td>\u53cc\u5411<\/td>\n<td>\u5f00\u6f0f&#xff0c;I2C \/ I3C<\/td>\n<td>2<\/td>\n<td>\u7ba1\u7406\u603b\u7ebf&#xff0c;\u6302 SPD Hub\u3001PMIC&#xff08;\u53ca\u6e29\u5ea6\u4f20\u611f\u5668&#xff09;\u3002\u9700\u5916\u90e8\u4e0a\u62c9&#xff0c;\u901f\u7387 100 kHz ~ 12.5 Mbps&#xff08;I3C SDR\/HDR&#xff09;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u4fe1\u53f7\u5c42\u9762\u7684\u4e24\u4e2a\u6613\u9519\u70b9<\/p>\n<p>\u2460\u00a0ALERT_n \u662f\u5f00\u6f0f&#xff0c;\u677f\u4e0a\u5fc5\u987b\u6709\u4e0a\u62c9&#xff1b;\u82e5\u591a rank \u5171\u7528\u4e00\u6839 ALERT_n&#xff0c;\u9700\u786e\u8ba4\u4e3b\u63a7\u80fd\u533a\u5206\u662f\u54ea\u4e00\u4e2a rank \u89e6\u53d1&#xff08;\u901a\u5e38\u9760\u9010\u4e2a rank \u67e5\u8be2 MR \u72b6\u6001\u4f4d&#xff09;\u3002\u2461\u00a0TEN \u4e0e Loopback \u5f15\u811a\u540d\u5728\u4e0d\u540c\u5382\u5546\u95f4\u547d\u540d\u4e0d\u5b8c\u5168\u4e00\u81f4&#xff08;\u90e8\u5206\u5382\u5546\u5199\u4f5c TEN \/ LBDQ \/ LB_DQS \u7b49&#xff09;&#xff0c;\u539f\u7406\u8bbe\u8ba1\u65f6\u52a1\u5fc5\u6309\u76ee\u6807 datasheet \u6821\u5bf9&#xff0c;\u4e0d\u8981\u7167\u6284\u53c2\u8003\u8bbe\u8ba1\u7684\u7f51\u7edc\u540d\u3002<\/p>\n<h4 id=\"s2-2\">2.2 CA \u603b\u7ebf&#xff1a;\u547d\u4ee4\u5982\u4f55\u88ab\u300c\u4e32\u884c\u5316\u300d<\/h4>\n<p>DDR5 \u7684\u547d\u4ee4\u7531 CA \u603b\u7ebf\u5728\u00a01 \u4e2a&#xff08;1T&#xff09;\u6216 2 \u4e2a&#xff08;2T&#xff09;CK \u5468\u671f\u5185\u4f20\u8f93\u3002\u7b2c\u4e00\u4e2a\u5468\u671f\u4f20\u8f93\u547d\u4ee4\u7801\u4e0e\u90e8\u5206\u5730\u5740&#xff0c;\u7b2c\u4e8c\u4e2a\u5468\u671f&#xff08;\u82e5\u9700\u8981&#xff09;\u4f20\u8f93\u5269\u4f59\u5730\u5740\u4e0e Bank\/Bank Group \u4f4d\u3002\u4e3b\u63a7\u4fa7\u901a\u8fc7 CA \u8bad\u7ec3&#xff08;CA Training&#xff09;\u786e\u5b9a\u91c7\u6837\u70b9&#xff0c;DRAM \u4fa7\u901a\u8fc7\u5185\u90e8 VREF \u4e0e&#xff08;\u90e8\u5206\u5668\u4ef6\u7684&#xff09;CA \u7aef\u63a5\u4fdd\u8bc1\u4fe1\u53f7\u8d28\u91cf\u3002<\/p>\n<table>\n<tr>\u547d\u4ee4CA \u5468\u671f\u6570\u627f\u8f7d\u5185\u5bb9\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>ACTIVATE&#xff08;ACT&#xff09;<\/td>\n<td>2T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; Row \u5730\u5740 &#043; BG\/Bank<\/td>\n<td>\u6253\u5f00\u4e00\u884c&#xff1b;DDR5 32 bank \u9700\u8981\u66f4\u591a Bank \u4f4d<\/td>\n<\/tr>\n<tr>\n<td>READ \/ WRITE<\/td>\n<td>1T \u6216 2T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; Column \u5730\u5740 &#043; BG\/Bank &#043; AP&#xff08;\u81ea\u52a8\u9884\u5145\u7535&#xff09;<\/td>\n<td>BL16 \u65f6\u5217\u5730\u5740\u6309 16 \u7a81\u53d1\u5bf9\u9f50<\/td>\n<\/tr>\n<tr>\n<td>PRECHARGE&#xff08;PRE&#xff09;<\/td>\n<td>1T \/ 2T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; Bank \u6216 All-Bank \u6807\u5fd7<\/td>\n<td>\u5173\u95ed\u884c&#xff0c;\u4e3a\u4e0b\u6b21 ACT \u505a\u51c6\u5907<\/td>\n<\/tr>\n<tr>\n<td>REFRESH&#xff08;REFab&#xff09;<\/td>\n<td>1T<\/td>\n<td>\u547d\u4ee4\u7801<\/td>\n<td>All-Bank Refresh&#xff0c;\u9700\u6ee1\u8db3 tRFC1<\/td>\n<\/tr>\n<tr>\n<td>REFRESH&#xff08;REFsb&#xff09;<\/td>\n<td>1T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; Bank \u5730\u5740<\/td>\n<td>Same-Bank Refresh&#xff0c;\u4ec5\u5237\u65b0\u6307\u5b9a bank&#xff0c;\u5176\u4f59 bank \u53ef\u7ee7\u7eed\u5de5\u4f5c<\/td>\n<\/tr>\n<tr>\n<td>MODE REGISTER WRITE\/READ&#xff08;MRW\/MRR&#xff09;<\/td>\n<td>2T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; MR \u5730\u5740 &#043; \u6570\u636e<\/td>\n<td>\u8bad\u7ec3\u671f\u95f4\u9ad8\u9891\u4f7f\u7528&#xff1b;\u5199 MR \u540e\u9700\u7b49\u5f85 tMRD \/ tMOD<\/td>\n<\/tr>\n<tr>\n<td>ZQ CALIBRATION<\/td>\n<td>1T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; Long\/Short \u6807\u5fd7<\/td>\n<td>\u4e0a\u7535\u9700 ZQCL&#xff08;\u957f\u6821\u51c6&#xff09;&#xff0c;\u9000\u51fa\u81ea\u5237\u65b0\u540e\u5e38\u7528 ZQCS<\/td>\n<\/tr>\n<tr>\n<td>MPC&#xff08;Multi-Purpose Command&#xff09;<\/td>\n<td>2T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; \u64cd\u4f5c\u7801<\/td>\n<td>\u627f\u8f7d\u8bad\u7ec3\u6a21\u5f0f\u8fdb\u5165\/\u9000\u51fa\u3001DFE \u4f7f\u80fd\u3001VREF \u8bbe\u7f6e\u3001Loopback \u4f7f\u80fd\u7b49<\/td>\n<\/tr>\n<tr>\n<td>RFM&#xff08;Refresh Management&#xff09;<\/td>\n<td>1T<\/td>\n<td>\u547d\u4ee4\u7801 &#043; Bank<\/td>\n<td>\u884c\u9524\u7f13\u89e3&#xff1a;\u5bf9\u9ad8\u9891\u6fc0\u6d3b\u533a\u57df\u53d1\u8d77\u989d\u5916\u5237\u65b0<\/td>\n<\/tr>\n<tr>\n<td>NOP \/ DESELECT<\/td>\n<td>1T<\/td>\n<td>\u2014<\/td>\n<td>CK \u8fb9\u6cbf\u91c7\u6837\u5230 CS_n \u65e0\u6548\u6216\u7a7a\u64cd\u4f5c\u7801<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h5>CA \u603b\u7ebf\u7684\u786c\u4ef6\u542b\u4e49<\/h5>\n<ul>\n<li>\u5f15\u811a\u6570\u4e0b\u964d&#xff1a;\u53d6\u6d88 RAS#\/CAS#\/WE#\/ACT#\/BA\/ADDR \u5206\u7acb\u5f15\u811a\u540e&#xff0c;x8 \u9897\u7c92\u7684\u5730\u5740\u547d\u4ee4\u7c7b\u5f15\u811a\u4ece DDR4 \u7684\u7ea6 25 \u6839\u964d\u5230 15 \u6839&#xff0c;\u4e3a\u7535\u6e90\u4e0e\u5730\u817e\u51fa\u7403\u4f4d&#xff08;\u8fd9\u4e5f\u662f DDR5 \u80fd\u5728 1.1 V \u4e0b\u4fdd\u6301\u7535\u6e90\u5b8c\u6574\u6027\u7684\u524d\u63d0\u4e4b\u4e00&#xff09;\u3002<\/li>\n<li>\u65f6\u5e8f\u4f59\u91cf\u4e0b\u964d&#xff1a;CA \u662f SDR \u4f46\u901f\u7387\u7b49\u4e8e fCK&#xff08;\u6700\u9ad8 4.4 GHz \u547d\u4ee4\u7387&#xff09;&#xff0c;\u5efa\u7acb\u4fdd\u6301\u7a97\u53e3\u6781\u5c0f&#xff0c;\u5fc5\u987b\u505a CA \u8bad\u7ec3&#xff08;VREF &#043; \u5ef6\u8fdf&#xff09;&#xff0c;\u4e14 CA \u8d70\u7ebf\u5fc5\u987b Fly-by \u7b49\u957f\u3001\u672b\u7aef\u7aef\u63a5\u3002<\/li>\n<li>2T \u547d\u4ee4\u964d\u4f4e\u6548\u7387&#xff1a;\u9ad8\u9891\u4e0b\u4e3b\u63a7\u5e38\u81ea\u52a8\u5207\u5230 2T \u547d\u4ee4\u65f6\u5e8f&#xff08;\u7c7b\u4f3c DDR \u7684 2T \u6a21\u5f0f&#xff09;&#xff0c;\u4f1a\u635f\u5931\u5c11\u91cf\u5e26\u5bbd&#xff0c;\u5c5e\u6b63\u5e38\u73b0\u8c61&#xff0c;\u4e0d\u8981\u8bef\u5224\u4e3a\u6545\u969c\u3002<\/li>\n<li>\u8c03\u8bd5\u96be\u5ea6\u4e0a\u5347&#xff1a;\u903b\u8f91\u5206\u6790\u4eea\u65e0\u6cd5\u50cf DDR3 \u90a3\u6837\u300c\u770b\u5f15\u811a\u77e5\u547d\u4ee4\u300d&#xff0c;\u5fc5\u987b\u4f7f\u7528\u652f\u6301 DDR5 CA \u89e3\u7801\u7684\u534f\u8bae\u5206\u6790\u4eea\u6216\u4f9d\u8d56\u4e3b\u63a7\u8bad\u7ec3\u65e5\u5fd7\u3002<\/li>\n<\/ul>\n<h4 id=\"s2-3\">2.3 BL16 \/ BC8\u3001\u5b50\u901a\u9053\u4e0e\u540c\u5e27 ECC<\/h4>\n<h5>\u7a81\u53d1\u957f\u5ea6 BL16 \u4e0e Burst Chop BC8<\/h5>\n<table>\n<tr>\u9879\u76ee\u6570\u503c \/ \u89c4\u5219\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u6807\u51c6\u7a81\u53d1\u957f\u5ea6<\/td>\n<td>BL16<\/td>\n<td>\u5355\u6b21\u8bfb\/\u5199\u4f20\u8f93 16 \u4e2a\u6570\u636e\u8282\u62cd&#xff0c;\u5728 DQ \u4e0a\u5360\u7528 8 \u4e2a CK \u5468\u671f&#xff08;DDR \u53cc\u6cbf&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>Burst Chop<\/td>\n<td>BC8<\/td>\n<td>\u534a\u7a81\u53d1&#xff0c;\u4f20\u8f93 8 \u4e2a\u8282\u62cd&#xff0c;\u7528\u4e8e\u4e0d\u6ee1 32 B \u7684\u8bbf\u95ee&#xff0c;\u51cf\u5c11\u65e0\u7528\u6570\u636e\u642c\u79fb<\/td>\n<\/tr>\n<tr>\n<td>\u5b50\u901a\u9053\u5355\u6b21\u4f20\u8f93\u91cf<\/td>\n<td>32 bit \u00d7 16 &#061; 64 B<\/td>\n<td>BL16 \u4e0b\u5355\u4e2a\u5b50\u901a\u9053\u4e00\u6b21\u7a81\u53d1 &#061; 64 B&#xff1b;\u4e24\u4e2a\u5b50\u901a\u9053\u5e76\u53d1 &#061; 128 B<\/td>\n<\/tr>\n<tr>\n<td>\u4e0e\u7f13\u5b58\u884c\u7684\u5bf9\u9f50<\/td>\n<td>64 B \u7f13\u5b58\u884c &#061; \u5355\u5b50\u901a\u9053 1 \u6b21 BL16<\/td>\n<td>\u8fd9\u662f DDR5 \u9009\u62e9 BL16 \u7684\u6838\u5fc3\u539f\u56e0&#xff1a;\u4e0e\u4e3b\u6d41 CPU 64 B \u7f13\u5b58\u884c\u5929\u7136\u5bf9\u9f50<\/td>\n<\/tr>\n<tr>\n<td>\u9884\u53d6<\/td>\n<td>16n<\/td>\n<td>\u9635\u5217\u4e00\u6b21\u8bfb\u51fa 16n&#xff0c;\u5bf9\u5916\u4ee5 BL16 \u5410\u51fa<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h5>\u540c\u5e27 ECC&#xff08;Same-Frame ECC&#xff09;\u4e0e\u7247\u4e0a ECC \u7684\u533a\u522b<\/h5>\n<table>\n<tr>\u7c7b\u578b\u4f4d\u7f6e\u4f4d\u5bbd\u5bf9\u7cfb\u7edf\u7684\u53ef\u89c1\u6027\u8bbe\u8ba1\u6ce8\u610f<\/tr>\n<tbody>\n<tr>\n<td>On-die ECC&#xff08;\u7247\u4e0a ECC&#xff09;<\/td>\n<td>DRAM \u9897\u7c92\u5185\u90e8<\/td>\n<td>\u5185\u90e8\u6821\u9a8c&#xff0c;\u4e0d\u5360\u7528\u4efb\u4f55\u5916\u90e8\u5f15\u811a<\/td>\n<td>\u5b8c\u5168\u900f\u660e&#xff0c;\u4e3b\u63a7\u65e0\u611f\u77e5<\/td>\n<td>\u63d0\u5347\u9635\u5217\u826f\u7387\u4e0e\u4fdd\u6301\u7279\u6027&#xff0c;\u4f46\u4e0d\u80fd\u66ff\u4ee3\u7cfb\u7edf\u7ea7 ECC&#xff1a;\u65e0\u6cd5\u68c0\u6d4b DQ \u94fe\u8def\u4e0a\u7684\u4f20\u8f93\u9519\u8bef<\/td>\n<\/tr>\n<tr>\n<td>\u540c\u5e27 ECC&#xff08;Link \/ Same-Frame ECC&#xff09;<\/td>\n<td>\u4e3b\u63a7 \u2194 DRAM \u94fe\u8def<\/td>\n<td>\u6bcf 32 bit \u6570\u636e\u914d 8 bit \u6821\u9a8c&#xff08;CB[7:0]&#xff09;<\/td>\n<td>\u4e3b\u63a7\u53ef\u89c1&#xff0c;\u9700 SECDED \u5f15\u64ce<\/td>\n<td>\u6821\u9a8c\u4f4d\u4e0e\u6570\u636e\u5728\u540c\u4e00\u5e27\u5185\u4f20\u8f93&#xff0c;\u4e0d\u989d\u5916\u589e\u52a0\u4f20\u8f93\u5468\u671f&#xff1b;\u4ee3\u4ef7\u662f\u6bcf\u5b50\u901a\u9053\u591a 8 \u6839\u7ebf<\/td>\n<\/tr>\n<tr>\n<td>\u4f20\u7edf ECC&#xff08;DDR4 x72&#xff09;<\/td>\n<td>\u6a21\u7ec4\u7ea7<\/td>\n<td>64 bit \u6570\u636e &#043; 8 bit ECC<\/td>\n<td>\u4e3b\u63a7\u53ef\u89c1<\/td>\n<td>\u9700\u8981\u628a\u603b\u7ebf\u6269\u5c55\u5230 72 bit&#xff0c;\u6240\u6709 DQ \u8d70\u7ebf\u4e0e\u9897\u7c92\u6570\u91cf\u589e\u52a0 1\/8<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u4e3a\u4ec0\u4e48 DDR5 \u8bf4\u300c\u4e0d\u6269\u5c55\u6570\u636e\u5bbd\u5ea6\u300d<\/p>\n<p>DDR5 \u7684 40 bit \u5b50\u901a\u9053\u4e2d&#xff0c;32 bit \u662f\u6570\u636e\u30018 bit \u662f\u6821\u9a8c\u3002\u76f8\u6bd4 DDR4 \u7684 72 bit&#xff08;64 \u6570\u636e &#043; 8 \u6821\u9a8c&#xff09;\u65b9\u6848&#xff0c;DDR5 \u7684\u6821\u9a8c\u4f4d\u6bd4\u4f8b\u662f DDR4 \u7684\u4e24\u500d&#xff08;32:8 \u800c\u975e 64:8&#xff09;&#xff0c;\u56e0\u6b64\u53ef\u4ee5\u5b9e\u73b0\u66f4\u5f3a\u7684\u7ea0\u9519&#xff08;\u90e8\u5206\u4e3b\u63a7\u53ef\u505a\u5230 SECDED \u4e4b\u5916\u518d\u68c0\u6d4b\u90e8\u5206\u591a\u6bd4\u7279\u9519\u8bef&#xff09;\u3002\u6240\u8c13\u300c\u4e0d\u6269\u5c55\u6570\u636e\u5bbd\u5ea6\u300d\u6307\u7684\u662f&#xff1a;\u6821\u9a8c\u4f4d\u4e0d\u4f5c\u4e3a\u72ec\u7acb\u7684\u4e00\u9897 x8 \u9897\u7c92\u6302\u5728\u603b\u7ebf\u4e0a\u6269\u5c55\u603b\u7ebf\u4f4d\u5bbd&#xff0c;\u800c\u662f\u4e0e\u6570\u636e\u540c\u5e27\u3001\u540c\u5b50\u901a\u9053\u3001\u540c\u7a81\u53d1\u4f20\u8f93&#xff0c;\u9897\u7c92\u4f4d\u5bbd\u4ecd\u662f x8\/x16&#xff0c;\u603b\u7ebf\u8c03\u5ea6\u4e0d\u56e0 ECC \u800c\u53d8\u590d\u6742\u3002\u82e5\u4e3b\u63a7\u4e0d\u4f7f\u7528 ECC&#xff0c;CB \u4f4d\u5e76\u975e\u7b80\u5355\u60ac\u7a7a\u2014\u2014\u9700\u6309\u4e3b\u63a7\u4e0e\u5668\u4ef6 datasheet \u5904\u7406&#xff08;\u5e38\u89c1\u505a\u6cd5\u4e3a\u63a5\u5730\u6216\u4fdd\u6301\u7aef\u63a5&#xff09;&#xff0c;\u5207\u52ff\u51ed\u7ecf\u9a8c\u60ac\u7a7a\u3002<\/p>\n<h4 id=\"s2-4\">2.4 \u5237\u65b0\u673a\u5236\u4e0e Same-Bank Refresh<\/h4>\n<table>\n<tr>\u5237\u65b0\u7c7b\u578b\u7c92\u5ea6\u5178\u578b\u5468\u671f\u6027\u80fd\u5f71\u54cd\u4f7f\u7528\u5efa\u8bae<\/tr>\n<tbody>\n<tr>\n<td>All-Bank Refresh&#xff08;REFab&#xff09;<\/td>\n<td>\u6574\u4e2a\u5668\u4ef6\u5168\u90e8 bank<\/td>\n<td>tRFC1&#xff08;\u2248295 ns &#064;16 Gb&#xff09;<\/td>\n<td>\u671f\u95f4\u6240\u6709 bank \u4e0d\u53ef\u8bbf\u95ee&#xff0c;\u5ef6\u8fdf\u5c16\u5cf0\u660e\u663e<\/td>\n<td>\u4e0a\u7535\u521d\u59cb\u5316\u3001\u7a7a\u95f2\u7a97\u53e3\u3001\u6216\u65e0\u6cd5\u505a\u7ec6\u7c92\u5ea6\u8c03\u5ea6\u65f6\u4f7f\u7528<\/td>\n<\/tr>\n<tr>\n<td>Same-Bank Refresh&#xff08;REFsb&#xff09;<\/td>\n<td>\u5355\u4e2a bank<\/td>\n<td>tRFCsb&#xff08;\u2248130 ns &#064;16 Gb&#xff09;<\/td>\n<td>\u4ec5\u76ee\u6807 bank \u963b\u585e&#xff0c;\u5176\u4f59 31 \u4e2a bank \u53ef\u7ee7\u7eed\u670d\u52a1<\/td>\n<td>\u4e1a\u52a1\u6001\u9996\u9009&#xff1b;\u4e3b\u63a7\u9700\u652f\u6301 REFsb \u8c03\u5ea6\u624d\u80fd\u53d7\u76ca<\/td>\n<\/tr>\n<tr>\n<td>Fine Granularity Refresh<\/td>\n<td>\u53ef\u914d\u7f6e\u6bd4\u4f8b<\/td>\n<td>\u6309 MR \u8bbe\u7f6e<\/td>\n<td>\u628a\u5237\u65b0\u5f00\u9500\u644a\u8584<\/td>\n<td>\u9ad8\u6e29\u573a\u666f\u4f18\u5148\u542f\u7528<\/td>\n<\/tr>\n<tr>\n<td>RFM \/ ARFM&#xff08;\u884c\u9524\u7f13\u89e3\u5237\u65b0&#xff09;<\/td>\n<td>Bank \u6216 Bank Group<\/td>\n<td>\u6309\u6fc0\u6d3b\u8ba1\u6570\u89e6\u53d1<\/td>\n<td>\u5c11\u91cf\u989d\u5916\u5237\u65b0\u5f00\u9500<\/td>\n<td>\u5fc5\u987b\u542f\u7528&#xff1b;\u7531\u4e3b\u63a7\u6216 DRAM \u5185\u90e8\u8ba1\u6570\u89e6\u53d1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u5237\u65b0\u5f00\u9500\u4f30\u7b97&#xff08;\u5355 rank&#xff0c;2 \u4e2a 16 Gb x8 \u9897\u7c92\u7ec4 32 bit \u5b50\u901a\u9053&#xff09;&#xff1a;<\/p>\n<p>  \u6807\u51c6\u5237\u65b0&#xff1a;tREFI &#061; 3.9 us  -&gt;  1 s \u5185 256,000 \u6b21 REFab<br \/>\n            \u6bcf\u6b21 tRFC1 \u2248 295 ns  -&gt;  \u5360\u7528\u7387 &#061; 256000 x 295ns \/ 1s \u2248 7.5%<\/p>\n<p>  \u540c\u5e27\u62c6\u5206\u4e3a REFsb&#xff08;\u5047\u8bbe\u628a 32 bank \u5206\u4e3a 32 \u6b21&#xff0c;\u6bcf\u6b21 tRFCsb \u2248 130 ns&#xff09;&#xff1a;<br \/>\n            \u603b\u5237\u65b0\u6b21\u6570\u4e0d\u53d8&#xff0c;\u4f46\u5355\u6b21\u963b\u585e\u4ece 295 ns \u964d\u5230 130 ns<br \/>\n            \u6700\u574f\u60c5\u51b5\u5355\u6b21\u963b\u585e\u964d\u4f4e\u7ea6 56%&#xff0c;\u5ef6\u8fdf\u5c16\u5cf0\u660e\u663e\u6539\u5584<\/p>\n<p>  \u9ad8\u6e29&#xff08;&gt; 85 C&#xff09;&#xff1a;tREFI \u6298\u534a\u4e3a 1.95 us  -&gt;  \u5360\u7528\u7387\u7ea6 15%&#xff0c;\u5e26\u5bbd\u53ef\u89c2\u6d4b\u4e0b\u964d<br \/>\n  &#061;&gt; \u70ed\u8bbe\u8ba1\u76ee\u6807&#xff1a;Tcase \u63a7\u5236\u5728 85 C \u4ee5\u4e0b&#xff0c;\u907f\u514d\u8fdb\u5165 2x \u5237\u65b0\u533a <\/p>\n<h4 id=\"s2-5\">2.5 \u6a21\u5f0f\u5bc4\u5b58\u5668\u4e0e\u8bad\u7ec3\u76f8\u5173 MR<\/h4>\n<p>DDR5 \u7684\u6a21\u5f0f\u5bc4\u5b58\u5668\u6570\u91cf\u663e\u8457\u591a\u4e8e DDR4&#xff0c;\u8bad\u7ec3\u76f8\u5173\u7684\u8bbe\u7f6e\u9879\u5206\u6563\u5728\u591a\u4e2a MR \u4e2d\u3002\u4e0b\u8868\u5217\u51fa\u4e0e\u786c\u4ef6\u8bbe\u8ba1\/\u8c03\u8bd5\u6700\u76f8\u5173\u7684\u9879&#xff08;\u5730\u5740\u4e0e\u4f4d\u5b9a\u4e49\u4ee5 JESD79-5 \u4e0e\u76ee\u6807 datasheet \u4e3a\u51c6&#xff09;&#xff1a;<\/p>\n<table>\n<tr>MR \u7c7b\u522b\u53ef\u914d\u7f6e\u5185\u5bb9\u786c\u4ef6\/\u8c03\u8bd5\u5173\u8054<\/tr>\n<tbody>\n<tr>\n<td>MR0~MR5&#xff08;\u57fa\u7840&#xff09;<\/td>\n<td>BL\u3001CL\u3001WR\/RTP\u3001\u9a71\u52a8\u5f3a\u5ea6\u3001ODT \u76f8\u5173\u57fa\u7840\u9879<\/td>\n<td>\u521d\u59cb\u5316\u7b2c\u4e00\u6279\u53d1\u5199&#xff1b;\u5199\u9519\u4f1a\u76f4\u63a5\u5bfc\u81f4\u8bad\u7ec3\u5931\u8d25<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;\u5199\u5747\u8861&#xff09;<\/td>\n<td>Write Leveling \u4f7f\u80fd \/ \u8f93\u51fa\u4f7f\u80fd<\/td>\n<td>\u9700\u8981 DQS \u4e0e CK \u8d70\u7ebf\u53ef\u6d4b&#xff1b;\u8bad\u7ec3\u5931\u8d25\u65f6\u4f18\u5148\u6392\u67e5 DQS\/CK \u62d3\u6251<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;Read Leveling&#xff09;<\/td>\n<td>Read Leveling \/ DQS \u5ef6\u8fdf\u94fe\u8bbe\u7f6e<\/td>\n<td>\u4e0e DQ-DQS \u7ec4\u5185\u7b49\u957f\u5f3a\u76f8\u5173<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;VREF&#xff09;<\/td>\n<td>\u5185\u90e8 VREF \u6863\u4f4d\u3001VREF \u8bad\u7ec3\u8303\u56f4\u4e0e\u6b65\u8fdb<\/td>\n<td>VREF \u4e0d\u5408\u7406\u4f1a\u8868\u73b0\u4e3a\u9ad8\u6e29\/\u4f4e\u538b\u4e0b\u968f\u673a\u9519<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;DFE&#xff09;<\/td>\n<td>DFE \u4f7f\u80fd\u3001\u62bd\u5934\u6570\u91cf\u3001\u7cfb\u6570\u52a0\u8f7d<\/td>\n<td>DFE \u4e0d\u6536\u655b\u65f6\u4f18\u5148\u67e5\u901a\u9053\u63d2\u635f\u4e0e\u6b8b\u6869<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;DCA&#xff09;<\/td>\n<td>Duty Cycle Adjuster \u5360\u7a7a\u6bd4\u8c03\u6574<\/td>\n<td>CK \u5360\u7a7a\u6bd4\u5931\u771f &gt; 2% \u65f6\u8865\u507f<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;CA \u8bad\u7ec3&#xff09;<\/td>\n<td>CA \u8bad\u7ec3\u6a21\u5f0f\u8fdb\u5165\/\u9000\u51fa\u3001CA VREF\u3001CA ODT<\/td>\n<td>CA \u8d70\u7ebf Fly-by \u672b\u7aef\u7aef\u63a5\u4e0d\u826f\u65f6\u8bad\u7ec3\u4e0d\u901a\u8fc7<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;CS \u8bad\u7ec3&#xff09;<\/td>\n<td>CS_n \u8bad\u7ec3\u6a21\u5f0f<\/td>\n<td>\u591a rank \u65f6\u9010 rank \u5355\u72ec\u8bad\u7ec3<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;Loopback&#xff09;<\/td>\n<td>Loopback \u53cd\u9988\u8f93\u51fa\u4f7f\u80fd\u4e0e\u9009\u62e9<\/td>\n<td>\u9700\u8981 PCB \u4e0a Loopback \u7f51\u7edc\u8fde\u901a\u4e14\u4e0d\u88ab\u8bef\u63a5\u4e0a\u62c9\/\u4e0b\u62c9<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;RTT&#xff09;<\/td>\n<td>RTT_NOM_RD \/ RTT_NOM_WR \/ RTT_WR \/ RTT_PARK<\/td>\n<td>\u7aef\u63a5\u503c\u9009\u62e9\u89c1\u7b2c 7 \u7ae0<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;\u5237\u65b0&#xff09;<\/td>\n<td>REFsb \u4f7f\u80fd\u3001FGR \u6bd4\u4f8b\u3001RFM\/ARFM \u914d\u7f6e<\/td>\n<td>\u884c\u9524\u4e0e\u9ad8\u6e29\u53ef\u9760\u6027\u76f8\u5173<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;\u6e29\u5ea6&#xff09;<\/td>\n<td>\u6e29\u5ea6\u8bfb\u51fa\u3001\u70ed\u8282\u6d41\u9608\u503c\u3001ALERT_n \u6e29\u5ea6\u4e8b\u4ef6\u4f7f\u80fd<\/td>\n<td>\u4e0e SPD Hub \u5185 TS \u8bfb\u6570\u4ea4\u53c9\u6838\u5bf9<\/td>\n<\/tr>\n<tr>\n<td>MR&#xff08;ECC \/ CRC&#xff09;<\/td>\n<td>ECC \u4f7f\u80fd\u3001\u5199 CRC\u3001\u9519\u8bef\u72b6\u6001\u4e0e\u8ba1\u6570\u8bfb\u51fa<\/td>\n<td>ECC \u62a5\u9519\u6392\u67e5\u7684\u6838\u5fc3\u5165\u53e3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u5178\u578b\u521d\u59cb\u5316\u5199 MR \u5e8f\u5217&#xff08;\u793a\u610f&#xff0c;\u987a\u5e8f\u4e0e\u5ef6\u65f6\u4ee5\u4e3b\u63a7 MRC \u4e0e datasheet \u4e3a\u51c6&#xff09;<\/p>\n<p> 1. \u4f9b\u7535\u7a33\u5b9a&#xff08;VDD\/VDDQ 1.1 V\u3001VPP 1.8 V&#xff09;&#xff0c;\u62c9\u4f4e RESET_n<br \/>\n 2. RESET_n \u4fdd\u6301\u4f4e &gt;&#061; tPW_RESET&#xff08;\u5178\u578b 1 us \u91cf\u7ea7&#xff0c;\u4ee5 datasheet \u4e3a\u51c6&#xff09;<br \/>\n 3. \u91ca\u653e RESET_n&#xff0c;\u7b49\u5f85 tXPR&#xff08;\u5178\u578b\u51e0\u767e ns ~ us&#xff09;<br \/>\n 4. \u62c9\u9ad8 CKE \u7c7b\u4f7f\u80fd&#xff08;DDR5 \u7531\u547d\u4ee4\/CS \u7ba1\u7406&#xff0c;\u6309\u4e3b\u63a7\u8981\u6c42\u6267\u884c&#xff09;<br \/>\n 5. ZQCL&#xff08;\u957f\u6821\u51c6&#xff09;&#xff0c;\u7b49\u5f85 tZQINIT&#xff08;\u5178\u578b 1 us \u91cf\u7ea7&#xff09;<br \/>\n 6. MRW&#xff1a;\u8bbe\u7f6e BL&#061;16\u3001CL\u3001tWR\u3001\u9a71\u52a8\u5f3a\u5ea6\u3001RTT_PARK<br \/>\n 7. MRW&#xff1a;\u8fdb\u5165 Write Leveling \u6a21\u5f0f -&gt; \u8bad\u7ec3 -&gt; \u9000\u51fa<br \/>\n 8. MRW&#xff1a;CA \u8bad\u7ec3\u6a21\u5f0f -&gt; CA VREF \/ CA \u5ef6\u8fdf\u8bad\u7ec3 -&gt; \u9000\u51fa<br \/>\n 9. MRW&#xff1a;Read Leveling \/ DQS \u5ef6\u8fdf\u8bad\u7ec3<br \/>\n10. MRW&#xff1a;\u5185\u90e8 VREF \u8bad\u7ec3&#xff08;\u9010\u5b57\u8282\u3001\u9010\u5b50\u901a\u9053&#xff09;<br \/>\n11. MRW&#xff1a;DFE \u4f7f\u80fd &#043; \u7cfb\u6570\u8bad\u7ec3<br \/>\n12. MRW&#xff1a;DCA&#xff08;\u5360\u7a7a\u6bd4&#xff09;\u8bad\u7ec3<br \/>\n13. MRW&#xff1a;Loopback \u8bad\u7ec3&#xff08;\u82e5\u4e3b\u63a7\u4e0e\u9897\u7c92\u652f\u6301&#xff09;<br \/>\n14. MRW&#xff1a;\u6b63\u5e38\u6a21\u5f0f&#xff0c;\u8fdb\u5165 IDLE&#xff0c;\u5f00\u59cb\u6b63\u5e38\u8bfb\u5199<br \/>\n15. \u5468\u671f\u6027&#xff1a;ZQCS&#xff08;\u77ed\u6821\u51c6&#xff09;\u3001VREF \u91cd\u8bad\u7ec3\u3001\u6e29\u5ea6\u89e6\u53d1\u91cd\u8bad\u7ec3 <\/p>\n<h4 id=\"s2-6\">2.6 \u5e26\u5bbd\u4e0e\u5bb9\u91cf\u8ba1\u7b97<\/h4>\n<table>\n<tr>\u901f\u7387\u7b49\u7ea7tCK (ns)\u5355\u5b50\u901a\u9053\u5e26\u5bbd (GB\/s)DIMM&#xff08;\u53cc\u901a\u9053&#xff0c;64 bit&#xff09;\u5e26\u5bbd (GB\/s)\u5178\u578b CL-tRCD-tRP&#xff08;JEDEC \u5e38\u89c1\u503c&#xff09;tAA (ns)<\/tr>\n<tbody>\n<tr>\n<td>DDR5-3200<\/td>\n<td>0.625<\/td>\n<td>12.8<\/td>\n<td>25.6<\/td>\n<td>22-22-22<\/td>\n<td>13.75<\/td>\n<\/tr>\n<tr>\n<td>DDR5-3600<\/td>\n<td>0.556<\/td>\n<td>14.4<\/td>\n<td>28.8<\/td>\n<td>26-26-26<\/td>\n<td>14.44<\/td>\n<\/tr>\n<tr>\n<td>DDR5-4000<\/td>\n<td>0.500<\/td>\n<td>16.0<\/td>\n<td>32.0<\/td>\n<td>30-30-30<\/td>\n<td>15.00<\/td>\n<\/tr>\n<tr>\n<td>DDR5-4400<\/td>\n<td>0.455<\/td>\n<td>17.6<\/td>\n<td>35.2<\/td>\n<td>34-34-34<\/td>\n<td>15.45<\/td>\n<\/tr>\n<tr>\n<td>DDR5-4800<\/td>\n<td>0.417<\/td>\n<td>19.2<\/td>\n<td>38.4<\/td>\n<td>40-40-40<\/td>\n<td>16.67<\/td>\n<\/tr>\n<tr>\n<td>DDR5-5200<\/td>\n<td>0.385<\/td>\n<td>20.8<\/td>\n<td>41.6<\/td>\n<td>42-42-42<\/td>\n<td>16.15<\/td>\n<\/tr>\n<tr>\n<td>DDR5-5600<\/td>\n<td>0.357<\/td>\n<td>22.4<\/td>\n<td>44.8<\/td>\n<td>46-45-45<\/td>\n<td>16.43<\/td>\n<\/tr>\n<tr>\n<td>DDR5-6000<\/td>\n<td>0.333<\/td>\n<td>24.0<\/td>\n<td>48.0<\/td>\n<td>48-48-48<\/td>\n<td>16.00<\/td>\n<\/tr>\n<tr>\n<td>DDR5-6400<\/td>\n<td>0.313<\/td>\n<td>25.6<\/td>\n<td>51.2<\/td>\n<td>52-52-52<\/td>\n<td>16.25<\/td>\n<\/tr>\n<tr>\n<td>DDR5-7200<\/td>\n<td>0.278<\/td>\n<td>28.8<\/td>\n<td>57.6<\/td>\n<td>58-58-58<\/td>\n<td>16.11<\/td>\n<\/tr>\n<tr>\n<td>DDR5-8000<\/td>\n<td>0.250<\/td>\n<td>32.0<\/td>\n<td>64.0<\/td>\n<td>64-64-64<\/td>\n<td>16.00<\/td>\n<\/tr>\n<tr>\n<td>DDR5-8800<\/td>\n<td>0.227<\/td>\n<td>35.2<\/td>\n<td>70.4<\/td>\n<td>70-70-70<\/td>\n<td>15.91<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u5e26\u5bbd\u8ba1\u7b97\u516c\u5f0f&#xff08;\u7406\u8bba\u5cf0\u503c&#xff09;<\/p>\n<p>  \u5355\u5b50\u901a\u9053\u5cf0\u503c (B\/s) &#061; \u901f\u7387(MT\/s) x \u5b50\u901a\u9053\u4f4d\u5bbd(bit) \/ 8<br \/>\n      \u4f8b&#xff1a;DDR5-6400 \u5355\u5b50\u901a\u9053 &#061; 6400 x 32 \/ 8 &#061; 25,600 MB\/s &#061; 25.6 GB\/s<\/p>\n<p>  \u5355\u4e2a DIMM \u5cf0\u503c &#061; \u901f\u7387 x 64 \/ 8        &#xff08;\u53cc 32 bit \u5b50\u901a\u9053\u5408\u8ba1&#xff09;<br \/>\n      \u4f8b&#xff1a;DDR5-6400 DIMM &#061; 6400 x 64 \/ 8 &#061; 51.2 GB\/s<\/p>\n<p>  \u6ce8\u610f&#xff1a;\u82e5\u542f\u7528 ECC&#xff08;CB[7:0]&#xff09;&#xff0c;\u94fe\u8def\u603b\u4f4d\u5bbd\u4e3a (32&#043;8) x 2 &#061; 80 bit&#xff0c;<br \/>\n        \u4f46\u300c\u6570\u636e\u5e26\u5bbd\u300d\u4ecd\u6309 64 bit \u8ba1\u7b97&#xff0c;\u6821\u9a8c\u4f4d\u4e0d\u627f\u8f7d\u7528\u6237\u6570\u636e\u3002<\/p>\n<p>  \u6709\u6548\u5e26\u5bbd &#061; \u5cf0\u503c x \u6548\u7387\u7cfb\u6570<br \/>\n      \u6548\u7387\u7cfb\u6570\u5178\u578b&#xff1a;Stream \u7c7b\u8fde\u7eed\u6d41 0.85~0.92<br \/>\n                    \u968f\u673a\u5c0f\u7c92\u5ea6\u8bbf\u95ee 0.25~0.45<br \/>\n                    \u53d7 tRC \/ tREFI \/ \u5237\u65b0\u5360\u7528\u7387 \/ \u8bfb\u5199\u7ffb\u8f6c\u60e9\u7f5a\u5f71\u54cd<\/p>\n<p>  \u677f\u8f7d&#xff08;down&#xff09;\u65b9\u6848\u5bb9\u91cf\u8ba1\u7b97&#xff1a;<br \/>\n      \u5355\u5b50\u901a\u9053\u5bb9\u91cf &#061; \u9897\u7c92\u5bb9\u91cf(bit) x \u9897\u7c92\u6570 \/ 8<br \/>\n      \u4f8b&#xff1a;4 \u9897 x8 16 Gb -&gt; 16 Gb x 4 \/ 8 &#061; 8 GB&#xff08;\u5355\u5b50\u901a\u9053&#xff09;<br \/>\n          \u4e24\u5b50\u901a\u9053\u5171 8 \u9897 -&gt; 16 GB <\/p>\n<h4 id=\"s2-7\">2.7 \u591a Rank\u30013DS \u4e0e\u5bb9\u91cf\u7ec4\u7ec7<\/h4>\n<table>\n<tr>\u6982\u5ff5\u5b9a\u4e49\u7535\u6c14\u5f71\u54cd\u8bbe\u8ba1\u6ce8\u610f<\/tr>\n<tbody>\n<tr>\n<td>Rank<\/td>\n<td>\u5171\u4eab\u540c\u4e00\u7ec4 CA\/CS \u7684\u4e00\u7ec4\u9897\u7c92&#xff0c;\u4e00\u6b21\u8bbf\u95ee\u53ea\u9009\u901a\u4e00\u4e2a rank<\/td>\n<td>DQ \u603b\u7ebf\u8d1f\u8f7d\u589e\u52a0&#xff08;\u591a rank \u65f6 DQ \u4e3a\u591a\u70b9\u5206\u652f&#xff09;<\/td>\n<td>\u6bcf rank \u9700\u72ec\u7acb CS_n&#xff1b;Fly-by \u987a\u5e8f\u5fc5\u987b\u4e0e\u4e3b\u63a7\u671f\u671b\u4e00\u81f4<\/td>\n<\/tr>\n<tr>\n<td>3DS&#xff08;3D Stacked&#xff09;<\/td>\n<td>\u5355\u5c01\u88c5\u5185\u5806\u53e0 2~8 \u4e2a die&#xff0c;\u901a\u8fc7 CS_n_A \/ CS_n_B \u4e0e\u5185\u90e8 CID \u9009\u62e9<\/td>\n<td>\u8d1f\u8f7d\u4e0e\u5355\u70b9\u5206\u652f\u7c7b\u4f3c\u591a rank&#xff0c;\u4f46\u8d70\u7ebf\u66f4\u77ed<\/td>\n<td>\u9700\u786e\u8ba4\u4e3b\u63a7\u652f\u6301 3DS&#xff1b;\u4e0a\u7535\u8bad\u7ec3\u9879\u589e\u52a0<\/td>\n<\/tr>\n<tr>\n<td>\u9897\u7c92\u4f4d\u5bbd\u7ec4\u5408<\/td>\n<td>x4 \/ x8 \/ x16<\/td>\n<td>x4 \u9700\u8981 8 \u9897\u7ec4 32 bit&#xff0c;\u8d1f\u8f7d\u6700\u91cd\u4f46\u5bc6\u5ea6\u6700\u9ad8<\/td>\n<td>\u677f\u8f7d\u65b9\u6848\u4f18\u5148 x16&#xff08;2 \u9897\/\u5b50\u901a\u9053&#xff0c;\u8d70\u7ebf\u6700\u77ed&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u6700\u5927\u5bb9\u91cf<\/td>\n<td>\u5355 DIMM \u53ef\u8fbe 128 GB&#043;&#xff08;RDIMM \/ 3DS \/ TSV \u7ec4\u5408&#xff09;<\/td>\n<td>\u5bb9\u91cf\u8d8a\u5927&#xff0c;\u5237\u65b0\u4e0e\u5730\u5740\u4f4d\u8d8a\u591a<\/td>\n<td>\u5730\u5740\u4f4d\u589e\u52a0\u4f1a\u63d0\u9ad8 CA 2T \u547d\u4ee4\u5360\u6bd4<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4 id=\"s2-8\">2.8 \u6a21\u7ec4\u4e0a\u7684\u5173\u952e\u5668\u4ef6&#xff1a;RCD \/ DB \/ PMIC \/ SPD Hub<\/h4>\n<table>\n<tr>\u5668\u4ef6\u5168\u79f0\u5e94\u7528\u5f62\u6001\u4f5c\u7528\u8bbe\u8ba1\u8981\u70b9<\/tr>\n<tbody>\n<tr>\n<td>RCD<\/td>\n<td>Registering Clock Driver<\/td>\n<td>RDIMM&#xff08;\u5fc5\u9009&#xff09;<\/td>\n<td>\u5bf9 CK\u3001CA\u3001CS \u8fdb\u884c\u5bc4\u5b58\u4e0e\u518d\u9a71\u52a8&#xff0c;\u9694\u79bb\u9897\u7c92\u8d1f\u8f7d&#xff1b;\u652f\u6301 CA \u7aef\u63a5\u4e0e\u5185\u90e8\u5747\u8861<\/td>\n<td>\u7531 PMIC \u4f9b\u7535&#xff1b;\u4e3b\u63a7\u4fa7\u5fc5\u987b\u6309 RCD \u7684\u5bc4\u5b58\u5668\u505a\u8bad\u7ec3&#xff08;RCD \u5f15\u5165\u56fa\u5b9a\u5ef6\u8fdf&#xff0c;\u9700\u8865\u507f&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>DB<\/td>\n<td>Data Buffer<\/td>\n<td>LRDIMM&#xff08;\u5fc5\u9009&#xff09;<\/td>\n<td>\u5bf9 DQ \/ DQS \/ DM \u7f13\u51b2&#xff0c;\u628a\u9897\u7c92\u4fa7\u6570\u636e\u8d1f\u8f7d\u9694\u79bb<\/td>\n<td>DDR5 LRDIMM \u5e38\u7528 MRCD\/MDB&#xff08;\u591a\u8def\u590d\u7528\u578b&#xff09;&#xff1b;\u4f1a\u589e\u52a0\u7ea6\u6570 ns \u5f80\u8fd4\u5ef6\u8fdf<\/td>\n<\/tr>\n<tr>\n<td>PMIC<\/td>\n<td>Power Management IC<\/td>\n<td>\u6240\u6709 DDR5 \u6a21\u7ec4<\/td>\n<td>\u8f93\u5165 5 V \u6216 12 V&#xff0c;\u8f93\u51fa VDD \/ VDDQ \/ VPP \u4e09\u8def&#xff1b;SMBus\/I3C \u53ef\u914d\u7f6e\u4e0e\u9065\u6d4b&#xff08;\u7535\u538b\u3001\u7535\u6d41\u3001\u6e29\u5ea6\u3001\u6545\u969c&#xff09;<\/td>\n<td>UDIMM\/SODIMM \u901a\u5e38 1 \u9897&#xff1b;RDIMM \u5e38\u89c1 2 \u9897&#xff08;\u5206\u522b\u4f9b\u4e24\u4e2a\u5b50\u901a\u9053\u533a\u57df&#xff09;\u3002\u8f93\u51fa\u7535\u538b\u4e0e\u65f6\u5e8f\u7531\u6a21\u7ec4\u5382\u5546\u9884\u8bbe&#xff0c;\u4e5f\u53ef\u7531\u4e3b\u63a7\u6539\u5199<\/td>\n<\/tr>\n<tr>\n<td>SPD Hub<\/td>\n<td>Serial Presence Detect Hub<\/td>\n<td>\u6240\u6709 DDR5 \u6a21\u7ec4<\/td>\n<td>\u5b58\u50a8 SPD \u6570\u636e&#xff0c;\u5e76\u4f5c\u4e3a I3C\/I2C hub \u7ba1\u7406 TS&#xff08;\u6e29\u5ea6\u4f20\u611f\u5668&#xff09;\u4e0e\u5176\u4ed6\u4ece\u8bbe\u5907<\/td>\n<td>\u5185\u542b TS&#xff08;\u5178\u578b 1~2 \u4e2a\u6e29\u5ea6\u4f20\u611f\u70b9&#xff09;&#xff1b;\u4e3b\u63a7\u901a\u8fc7\u5b83\u8bfb\u53d6\u6e29\u5ea6\u5e76\u89e6\u53d1\u70ed\u8282\u6d41<\/td>\n<\/tr>\n<tr>\n<td>TS<\/td>\n<td>Temperature Sensor<\/td>\n<td>\u96c6\u6210\u4e8e SPD Hub \u6216\u5206\u7acb<\/td>\n<td>\u63d0\u4f9b DIMM \u6e29\u5ea6&#xff0c;\u7528\u4e8e\u5237\u65b0\u7387\u5207\u6362\u4e0e\u8282\u6d41<\/td>\n<td>\u8bfb\u6570\u4e0e DRAM \u5185\u90e8 MR \u6e29\u5ea6\u5bc4\u5b58\u5668\u5e94\u4ea4\u53c9\u6838\u5bf9<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h5>\u7ba1\u7406\u603b\u7ebf&#xff08;HSCL \/ HSDA&#xff09;\u7684\u786c\u4ef6\u8981\u6c42<\/h5>\n<table>\n<tr>\u9879\u76ee\u8981\u6c42\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u534f\u8bae<\/td>\n<td>I2C \u517c\u5bb9 &#043; I3C&#xff08;MIPI I3C Basic&#xff09;<\/td>\n<td>\u4e0a\u7535\u9636\u6bb5\u4ee5 I2C \u6a21\u5f0f\u901a\u4fe1&#xff0c;\u4e3b\u63a7\u53ef\u5207\u6362\u5230 I3C \u63d0\u5347\u9065\u6d4b\u901f\u7387<\/td>\n<\/tr>\n<tr>\n<td>\u901f\u7387<\/td>\n<td>100 kHz \/ 400 kHz \/ 1 MHz&#xff08;I2C&#xff09;&#xff1b;\u6700\u9ad8 12.5 Mbps&#xff08;I3C SDR&#xff09;<\/td>\n<td>\u9ad8\u901f\u6a21\u5f0f\u9700\u91cd\u65b0\u6838\u7b97\u4e0a\u62c9\u4e0e\u603b\u7ebf\u7535\u5bb9<\/td>\n<\/tr>\n<tr>\n<td>\u4e0a\u62c9\u7535\u963b<\/td>\n<td>\u5178\u578b 1.5 ~ 4.7 k\u03a9&#xff08;\u4f9d\u7535\u538b\u4e0e\u603b\u7ebf\u7535\u5bb9&#xff09;<\/td>\n<td>\u4e0a\u62c9\u5230\u7ba1\u7406\u7535\u6e90&#xff08;\u6a21\u7ec4\u4fa7\u5e38\u4e3a 3.3 V \u6216 1.8 V&#xff0c;\u4ee5\u89c4\u8303\u4e3a\u51c6&#xff09;&#xff1b;\u4e3b\u63a7\u4fa7\u9700\u5339\u914d\u7535\u5e73<\/td>\n<\/tr>\n<tr>\n<td>\u603b\u7ebf\u7535\u5bb9<\/td>\n<td>\u2264 100 pF&#xff08;I2C 400 kHz \u5e38\u89c4\u4e0a\u9650&#xff09;<\/td>\n<td>\u591a\u63d2\u69fd\u5e76\u8054\u4f1a\u7d2f\u52a0&#xff0c;\u9700\u6838\u7b97\u6216\u52a0\u603b\u7ebf\u7f13\u51b2<\/td>\n<\/tr>\n<tr>\n<td>\u5730\u5740<\/td>\n<td>SPD Hub \u4e0e PMIC \u5404\u6709\u72ec\u7acb\u5730\u5740&#xff0c;\u7531 SA0~SA2 \u7c7b\u5f15\u811a\u8bbe\u5b9a<\/td>\n<td>\u591a\u63d2\u69fd\u65f6\u5fc5\u987b\u4fdd\u8bc1\u5730\u5740\u4e0d\u51b2\u7a81&#xff1b;\u539f\u7406\u8bbe\u8ba1\u9884\u7559\u5730\u5740\u914d\u7f6e\u7535\u963b<\/td>\n<\/tr>\n<tr>\n<td>PCB<\/td>\n<td>\u8d70\u6210\u5bf9\u3001\u8fdc\u79bb\u9ad8\u901f\u4fe1\u53f7\u3001\u5305\u5730<\/td>\n<td>\u867d\u662f\u4f4e\u901f\u603b\u7ebf&#xff0c;\u4f46\u88ab\u5e72\u6270\u4f1a\u5bfc\u81f4 SPD \u8bfb\u53d6\u5931\u8d25\u3001\u6574\u673a\u70b9\u4e0d\u4eae<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u7ba1\u7406\u603b\u7ebf\u662f\u6700\u5bb9\u6613\u88ab\u5ffd\u7565\u7684\u300c\u70b9\u4e0d\u4eae\u300d\u6839\u56e0<\/p>\n<p>\u82e5 HSCL\/HSDA \u4e0a\u62c9\u7f3a\u5931\u3001\u4e0a\u62c9\u7535\u6e90\u57df\u9519\u8bef\u3001\u6216\u591a\u63d2\u69fd\u5730\u5740\u51b2\u7a81&#xff0c;\u8868\u73b0\u4e3a\u4e3b\u63a7\u8bfb\u4e0d\u5230 SPD \u2192 \u65e0\u6cd5\u786e\u5b9a\u5185\u5b58\u53c2\u6570 \u2192 \u76f4\u63a5\u62d2\u7edd\u521d\u59cb\u5316&#xff0c;\u4e14\u4e0d\u4f1a\u7ed9\u51fa\u6709\u610f\u4e49\u7684\u9ad8\u901f\u62a5\u9519\u3002\u539f\u7406\u8bbe\u8ba1\u9636\u6bb5\u5fc5\u987b&#xff1a;\u2460 \u786e\u8ba4\u4e0a\u62c9\u7535\u6e90\u57df&#xff1b;\u2461 \u4e3a SA0~SA2 \u7559 0 \u03a9 \u53ef\u9009\u914d\u7f6e&#xff1b;\u2462 \u5728\u7ba1\u7406\u603b\u7ebf\u4e0a\u9884\u7559\u6d4b\u8bd5\u70b9&#xff08;\u4f46\u4e0d\u8981\u52a0\u62c9\u4f4e\u603b\u7ebf\u7535\u5bb9\u7684\u6d4b\u8bd5\u710a\u76d8&#xff09;\u3002<\/p>\n<h3>3 \u00b7 \u7535\u6e90\u8bbe\u8ba1<\/h3>\n<p>DDR5 \u7535\u6e90\u8bbe\u8ba1\u7684\u7b2c\u4e00\u539f\u5219\u662f&#xff1a;\u7535\u538b\u8c03\u8282\u4ece\u4e3b\u677f\u4e0b\u6c89\u5230\u5185\u5b58\u6761\u3002\u6a21\u7ec4\u65b9\u6848\u4e3b\u677f\u53ea\u8d1f\u8d23\u9001 5 V \u6216 12 V&#xff1b;\u677f\u8f7d&#xff08;down&#xff09;\u65b9\u6848\u5219\u5fc5\u987b\u7531\u8bbe\u8ba1\u8005\u81ea\u5df1\u5b8c\u6210\u6574\u6761 PMIC \/ DC-DC \u94fe\u8def\u30021.1 V \u4e0b \u00b13% \u7684 AC \u566a\u58f0\u9884\u7b97&#xff08;\u7ea6 33 mV&#xff09;\u51b3\u5b9a\u4e86\u8fd9\u4e00\u7ae0\u7684\u6bcf\u4e00\u9879\u90fd\u4e0d\u80fd\u6253\u6298\u3002<\/p>\n<h4 id=\"s3-1\">3.1 \u7535\u6e90\u57df\u4e0e\u5bb9\u5dee<\/h4>\n<table>\n<tr>\u7535\u6e90\u57df\u6807\u79f0\u503c\u6765\u6e90&#xff08;\u6a21\u7ec4\u65b9\u6848&#xff09;\u6765\u6e90&#xff08;\u677f\u8f7d\u65b9\u6848&#xff09;\u5bb9\u5dee\u8981\u70b9<\/tr>\n<tbody>\n<tr>\n<td>VDD&#xff08;\u6838\u5fc3&#xff09;<\/td>\n<td>1.1 V<\/td>\n<td>On-DIMM PMIC<\/td>\n<td>\u81ea\u5efa PMIC \/ \u5355\u76f8\u6216\u591a\u76f8 buck<\/td>\n<td>DC \u7cbe\u5ea6 &#043; \u7eb9\u6ce2 &#043; \u77ac\u6001\u603b\u548c\u9700\u6ee1\u8db3 datasheet&#xff08;\u5178\u578b \u00b13% AC&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>VDDQ&#xff08;I\/O&#xff09;<\/td>\n<td>1.1 V<\/td>\n<td>On-DIMM PMIC&#xff08;\u5e38\u4e0e VDD \u540c\u8def\u6216\u72ec\u7acb\u8def&#xff09;<\/td>\n<td>\u53ef\u4e0e VDD \u5171\u7528&#xff0c;\u4e5f\u53ef\u901a\u8fc7\u78c1\u73e0\/\u7535\u611f\u9694\u79bb<\/td>\n<td>\u9ad8\u9891\u566a\u58f0\u76f4\u63a5\u53e0\u52a0\u5728 DQ \u4e0a&#xff0c;\u53bb\u8026\u5fc5\u987b\u5230\u9897\u7c92<\/td>\n<\/tr>\n<tr>\n<td>VPP&#xff08;\u5b57\u7ebf\u5347\u538b&#xff09;<\/td>\n<td>1.8 V<\/td>\n<td>On-DIMM PMIC \u7b2c\u4e09\u8def<\/td>\n<td>\u5c0f\u7535\u6d41 LDO \u6216 buck&#xff08;\u51e0\u5341 mA \u91cf\u7ea7&#xff09;<\/td>\n<td>\u7535\u6d41\u5c0f\u4f46\u9700\u72ec\u7acb\u53bb\u8026&#xff0c;\u907f\u514d\u4e0e VDD \u5171\u7528\u540c\u4e00\u6ee4\u6ce2\u8282\u70b9<\/td>\n<\/tr>\n<tr>\n<td>\u7ba1\u7406\u7535\u6e90&#xff08;\u6a21\u7ec4\u4fa7&#xff09;<\/td>\n<td>1.8 V \/ 3.3 V&#xff08;\u4f9d\u89c4\u8303&#xff09;<\/td>\n<td>\u4e3b\u677f\u5e38\u4f9b VIN_SPD \u7c7b\u7535\u6e90<\/td>\n<td>\u6309\u9897\u5668\u4ef6\u786e\u5b9a<\/td>\n<td>\u7ed9 SPD Hub \/ PMIC \u63a7\u5236\u903b\u8f91\u4f9b\u7535&#xff0c;\u6389\u7535\u65f6\u901a\u5e38\u9700\u4fdd\u6301\u6216\u53d7\u63a7<\/td>\n<\/tr>\n<tr>\n<td>ZQ \/ VREF<\/td>\n<td>\u2014<\/td>\n<td>\u5185\u90e8\u751f\u6210<\/td>\n<td>\u5185\u90e8\u751f\u6210<\/td>\n<td>ZQ \u5916\u63a5 240 \u03a9 \u00b11%&#xff0c;\u6e29\u5ea6\u7cfb\u6570 \u2264 100 ppm\/\u00b0C \u66f4\u597d<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u566a\u58f0\u9884\u7b97\u62c6\u89e3&#xff08;\u4ee5 VDD &#061; 1.1 V \u4e3a\u4f8b&#xff0c;\u6570\u503c\u6309\u76ee\u6807 datasheet \u590d\u6838&#xff09;<\/p>\n<p>  \u603b\u5bb9\u5dee&#xff08;\u5178\u578b&#xff09;   : \u00b13%  -&gt;  \u00b133 mV<br \/>\n  \u5176\u4e2d\u5efa\u8bae\u5206\u914d&#xff1a;<br \/>\n     DC \u8bbe\u5b9a\u8bef\u5dee    : \u2264 8 mV   &#xff08;PMIC \u53cd\u9988\u7535\u963b 0.5% &#043; \u57fa\u51c6\u6e90\u8bef\u5dee&#xff09;<br \/>\n     \u4f4e\u9891\u7eb9\u6ce2 (&lt;1MHz): \u2264 10 mV  &#xff08;\u7531 buck \u8f93\u51fa\u7535\u611f\/\u8f93\u51fa\u7535\u5bb9\u51b3\u5b9a&#xff09;<br \/>\n     \u9ad8\u9891\u566a\u58f0 (&gt;1MHz): \u2264 8 mV   &#xff08;\u7531\u9676\u74f7\u53bb\u8026\u9635\u5217\u4e0e\u5e73\u9762\u7535\u5bb9\u51b3\u5b9a&#xff09;<br \/>\n     \u77ac\u6001\u8dcc\u843d        : \u2264 7 mV   &#xff08;\u7531\u8d1f\u8f7d\u9636\u8dc3\u54cd\u5e94\u4e0e bulk \u7535\u5bb9\u51b3\u5b9a&#xff09;<\/p>\n<p>  &#061;&gt; \u53ea\u8981\u6709\u4e00\u9879\u8d85\u9884\u7b97&#xff0c;\u5c31\u4f1a\u5728\u773c\u56fe\u4e0a\u76f4\u63a5\u8868\u73b0\u4e3a&#xff1a;\u5199\u773c\u6536\u7a84\u3001VREF \u8bad\u7ec3\u7a97\u53e3\u53d8\u7a84\u3001<br \/>\n     \u9ad8\u6e29\u4e0b\u968f\u673a\u9519\u3002\u4e0d\u8981\u6307\u671b\u300c\u9760\u8bad\u7ec3\u6551\u56de\u6765\u300d\u2014\u2014\u8bad\u7ec3\u80fd\u8865\u507f\u65f6\u5e8f&#xff0c;\u8865\u507f\u4e0d\u4e86\u7535\u6e90\u566a\u58f0\u3002 <\/p>\n<h4 id=\"s3-2\">3.2 On-DIMM PMIC<\/h4>\n<table>\n<tr>\u9879\u76ee\u5178\u578b\u89c4\u683c\u8bbe\u8ba1\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u8f93\u5165\u7535\u538b<\/td>\n<td>5 V&#xff08;SODIMM \/ \u591a\u6570 UDIMM&#xff09;\u6216 12 V&#xff08;\u670d\u52a1\u5668 RDIMM&#xff09;<\/td>\n<td>\u7531\u6a21\u7ec4\u5f62\u6001\u51b3\u5b9a&#xff1b;\u4e3b\u677f\u53ea\u9001\u4e00\u79cd&#xff0c;\u539f\u7406\u8bbe\u8ba1\u524d\u5148\u786e\u8ba4\u63d2\u69fd\u5b9a\u4e49<\/td>\n<\/tr>\n<tr>\n<td>\u8f93\u51fa\u901a\u9053<\/td>\n<td>3 \u8def&#xff1a;VDD \/ VDDQ \/ VPP<\/td>\n<td>\u90e8\u5206 PMIC \u96c6\u6210\u7b2c\u56db\u8def&#xff08;\u7ba1\u7406\u7535\u6e90&#xff09;\u6216 LDO<\/td>\n<\/tr>\n<tr>\n<td>\u8f93\u51fa\u7535\u6d41\u80fd\u529b<\/td>\n<td>VDD&#043;VDDQ \u5408\u8ba1\u53ef\u8fbe\u6570\u5341 A \u91cf\u7ea7&#xff08;\u4f9d PMIC \u4e0e\u6a21\u7ec4&#xff09;<\/td>\n<td>\u4e3b\u677f 5 V\/12 V \u7535\u6e90\u5fc5\u987b\u6309\u6ee1\u914d\u6a21\u7ec4\u6570\u91cf\u7559\u4f59\u91cf&#xff08;\u89c1 3.3&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u63a7\u5236\u63a5\u53e3<\/td>\n<td>I2C \/ I3C&#xff08;SMBus \u517c\u5bb9&#xff09;<\/td>\n<td>\u4e0e SPD Hub \u6302\u5728\u540c\u4e00\u6761 HSCL\/HSDA \u4e0a&#xff0c;\u5730\u5740\u4e0d\u540c<\/td>\n<\/tr>\n<tr>\n<td>\u9065\u6d4b<\/td>\n<td>\u8f93\u51fa\u7535\u538b\u3001\u7535\u6d41\u3001\u6e29\u5ea6\u3001\u6545\u969c\u72b6\u6001<\/td>\n<td>BMC \/ BIOS \u8bfb\u53d6\u7528\u4e8e\u70ed\u8282\u6d41\u4e0e\u6545\u969c\u4e0a\u62a5<\/td>\n<\/tr>\n<tr>\n<td>\u53ef\u914d\u7f6e\u6027<\/td>\n<td>\u8f93\u51fa\u7535\u538b\u3001\u8f6f\u542f\u52a8\u3001\u4fdd\u62a4\u9608\u503c\u3001\u5f00\u5173\u9891\u7387<\/td>\n<td>\u9ed8\u8ba4\u503c\u7531\u6a21\u7ec4\u5382\u5546\u5199\u5165&#xff1b;\u4e3b\u63a7\u53ef\u6539\u5199&#xff08;\u90e8\u5206\u5e73\u53f0\u9501\u5b9a&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u6545\u969c\u884c\u4e3a<\/td>\n<td>OVP \/ UVP \/ OCP \/ OTP \u2192 \u5173\u65ad\u6216\u544a\u8b66<\/td>\n<td>ALERT_n \u4e0e PMIC \u72b6\u6001\u5bc4\u5b58\u5668\u662f\u6392\u67e5\u7535\u6e90\u95ee\u9898\u7684\u7b2c\u4e00\u5165\u53e3<\/td>\n<\/tr>\n<tr>\n<td>\u6570\u91cf<\/td>\n<td>UDIMM \/ SODIMM \u901a\u5e38 1 \u9897&#xff1b;RDIMM \/ LRDIMM \u5e38\u89c1 2 \u9897<\/td>\n<td>\u4e24\u9897\u65f6\u5730\u5740\u9700\u533a\u5206&#xff0c;\u9065\u6d4b\u8981\u5206\u522b\u8bfb\u53d6<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4 id=\"s3-3\">3.3 \u677f\u8f7d&#xff08;down&#xff09;\u65b9\u6848\u4e0e\u4e3b\u677f\u4f9b\u7535\u89c4\u5212<\/h4>\n<h5>\u677f\u8f7d vs \u63d2\u69fd\u7684\u53d6\u820d<\/h5>\n<table>\n<tr>\u7ef4\u5ea6\u677f\u8f7d\u9897\u7c92&#xff08;down&#xff09;\u63d2\u69fd\u6a21\u7ec4&#xff08;UDIMM\/RDIMM&#xff09;<\/tr>\n<tbody>\n<tr>\n<td>\u4fe1\u53f7\u8d28\u91cf<\/td>\n<td>\u8d70\u7ebf\u6700\u77ed&#xff08;\u53ef \u2264 3 inch&#xff09;&#xff0c;\u65e0\u8fde\u63a5\u5668\u635f\u8017&#xff0c;\u6700\u5bb9\u6613\u8dd1\u5230 6400&#043;\u00a0\u4f18<\/td>\n<td>\u63d2\u69fd\u5f15\u5165 1~2 dB \u63d2\u635f\u4e0e\u963b\u6297\u4e0d\u8fde\u7eed&#xff0c;\u901f\u7387\u4e0a\u9650\u53d7\u9650<\/td>\n<\/tr>\n<tr>\n<td>\u5bb9\u91cf\u7075\u6d3b\u6027<\/td>\n<td>\u51fa\u5382\u5373\u56fa\u5b9a\u00a0\u52a3<\/td>\n<td>\u73b0\u573a\u53ef\u66f4\u6362\u3001\u53ef\u6269\u5bb9\u00a0\u4f18<\/td>\n<\/tr>\n<tr>\n<td>\u7535\u6e90\u8d23\u4efb<\/td>\n<td>\u8bbe\u8ba1\u8005\u5168\u8d23&#xff1a;PMIC \u9009\u578b\u3001\u65f6\u5e8f\u3001\u53bb\u8026\u3001PDN<\/td>\n<td>\u7531\u6a21\u7ec4 PMIC \u627f\u62c5&#xff0c;\u4e3b\u677f\u53ea\u9700\u9001 5 V\/12 V<\/td>\n<\/tr>\n<tr>\n<td>\u6210\u672c\u4e0e\u5e93\u5b58<\/td>\n<td>BOM \u4f4e&#xff0c;\u4f46\u9897\u7c92\u9700\u6309\u9879\u76ee\u5907\u8d27<\/td>\n<td>BOM \u9ad8&#xff08;\u542b PMIC\/SPD\/RCD&#xff09;&#xff0c;\u4f46\u6a21\u7ec4\u901a\u7528<\/td>\n<\/tr>\n<tr>\n<td>\u7ef4\u4fee\u6027<\/td>\n<td>BGA \u8fd4\u4fee\u56f0\u96be<\/td>\n<td>\u6362\u6761\u5373\u53ef<\/td>\n<\/tr>\n<tr>\n<td>\u9002\u7528\u573a\u666f<\/td>\n<td>\u5d4c\u5165\u5f0f\u3001\u8fb9\u7f18\u8ba1\u7b97\u3001\u7a7a\u95f4\u53d7\u9650\u3001\u56fa\u5b9a\u914d\u7f6e<\/td>\n<td>\u670d\u52a1\u5668\u3001PC\u3001\u5de5\u63a7\u3001\u9700\u73b0\u573a\u6269\u5bb9\u7684\u573a\u666f<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u677f\u8f7d\u65b9\u6848\u7535\u6e90\u9884\u7b97\u4f30\u7b97&#xff08;\u793a\u4f8b&#xff0c;\u6570\u503c\u9700\u6309\u5b9e\u9645\u5668\u4ef6\u590d\u6838&#xff09;<\/p>\n<p>  \u5355\u9897 DDR5 x8 \u9897\u7c92\u5de5\u4f5c\u7535\u6d41&#xff08;\u4f30\u7b97\u91cf\u7ea7&#xff09;&#xff1a;<br \/>\n      IDD0&#xff08;\u6fc0\u6d3b\u5f85\u673a&#xff09;        ~ 40~70 mA<br \/>\n      IDD4R&#xff08;\u8bfb&#xff0c;6400 MT\/s&#xff09; ~ 150~250 mA<br \/>\n      IDD4W&#xff08;\u5199&#xff0c;6400 MT\/s&#xff09; ~ 180~300 mA<br \/>\n      IDD5B&#xff08;\u5237\u65b0&#xff09;          ~ 200~350 mA<br \/>\n      IDD2P&#xff08;\u4f4e\u529f\u8017&#xff09;        ~ 15~40 mA<\/p>\n<p>  8 \u9897\u7c92&#xff08;16 GB&#xff0c;\u53cc 32 bit \u5b50\u901a\u9053&#xff09;\u6ee1\u8d1f\u8377\u4f30\u7b97&#xff1a;<br \/>\n      I_VDD  \u2248 8 x 0.25 A &#061; 2.0 A&#xff08;\u8bfb\u5199\u5cf0\u503c\u53ef\u5230 3 A&#xff09;<br \/>\n      I_VDDQ \u2248 0.5~1.5 A&#xff08;\u4e0e DQ \u7ffb\u8f6c\u7387\u548c\u7aef\u63a5\u7535\u6d41\u76f8\u5173&#xff0c;\u7aef\u63a5\u7535\u6d41\u4e0d\u53ef\u5ffd\u7565&#xff09;<br \/>\n      I_VPP  \u2248 10~30 mA&#xff08;\u5f88\u5c0f&#xff0c;\u4f46\u9700\u72ec\u7acb\u8def&#xff09;<\/p>\n<p>  \u8f93\u5165\u4fa7&#xff08;12 V&#xff09;\u7535\u6d41&#xff1a;<br \/>\n      \u603b\u529f\u7387 \u2248 1.1 V x 3.5 A &#043; 1.1 V x 1.5 A &#043; 1.8 V x 0.03 A \u2248 5.6 W<br \/>\n      I(12V) \u2248 5.6 W \/ 12 V \/ 0.9&#xff08;\u6548\u7387&#xff09; \u2248 0.52 A<\/p>\n<p>  \u591a\u63d2\u69fd\u573a\u666f&#xff08;\u670d\u52a1\u5668&#xff0c;8 \u6761 RDIMM &#064; 12 V&#xff09;&#xff1a;<br \/>\n      \u5355\u6761\u5cf0\u503c\u6309 25~40 W \u8ba1 -&gt; 8 \u6761 \u2248 200~320 W<br \/>\n      &#061;&gt; 12 V \u8f93\u5165\u9700 \u2265 30 A&#xff0c;\u5fc5\u987b\u72ec\u7acb\u7535\u6e90\u5c42 &#043; \u591a\u76ce\u53f8\u94dc\u539a <\/p>\n<p>\u591a\u63d2\u69fd\u4e3b\u677f\u7684 5 V \/ 12 V \u5206\u914d<\/p>\n<p>\u6a21\u7ec4\u65b9\u6848\u4e0b&#xff0c;\u4e3b\u677f\u7684 5 V\/12 V \u662f\u552f\u4e00\u7684\u4f9b\u7535\u901a\u9053&#xff0c;\u5176\u7eb9\u6ce2\u4f1a\u88ab PMIC \u7684 PSRR \u90e8\u5206\u6291\u5236&#xff0c;\u4f46\u4f4e\u9891\u8dcc\u843d\u65e0\u6cd5\u6291\u5236\u3002\u8bbe\u8ba1\u65f6\u5fc5\u987b&#xff1a;\u2460 \u6309\u6ee1\u914d\u6700\u9ad8\u901f\u7387\u6a21\u7ec4\u8ba1\u7b97\u8f93\u5165\u7535\u6d41\u5e76\u7559 \u2265 20% \u4f59\u91cf&#xff1b;\u2461 \u7535\u6e90\u5c42\u94dc\u539a \u2265 2 oz&#xff08;\u670d\u52a1\u5668\u5efa\u8bae\u5185\u5c42\u7535\u6e90\u7528 2 oz \u6216\u52a0\u94fa&#xff09;&#xff1b;\u2462 \u6bcf\u6761\u63d2\u69fd\u9644\u8fd1\u5e03\u7f6e bulk \u7535\u5bb9&#xff08;\u89c1 3.4&#xff09;&#xff1b;\u2463 \u907f\u514d\u4e0e GPU \/ \u7535\u673a \/ \u5927\u7535\u6d41 DC-DC \u5171\u7528\u540c\u4e00\u8def\u3002<\/p>\n<h4 id=\"s3-4\">3.4 \u53bb\u8026\u7535\u5bb9\u914d\u7f6e<\/h4>\n<table>\n<tr>\u4f4d\u7f6e\u5bb9\u503c\u4e0e\u6570\u91cf&#xff08;\u6bcf\u9897\u7c92 \/ \u6bcf\u6761 \/ \u6bcf\u8def&#xff09;\u5c01\u88c5\u4f5c\u7528\u9891\u6bb5\u5907\u6ce8<\/tr>\n<tbody>\n<tr>\n<td>\u9897\u7c92 VDD \u7403\u9644\u8fd1&#xff08;\u80cc\u9762&#xff09;<\/td>\n<td>0.1 \u00b5F \u00d7 1~2 &#043; 0.01 \u00b5F \u00d7 1&#xff08;\u6bcf\u9897&#xff09;<\/td>\n<td>0201 \/ 0402<\/td>\n<td>10~100 MHz<\/td>\n<td>\u5fc5\u987b\u80cc\u9762\u8d34\u88c5\u3001\u8fc7\u5b54\u6700\u77ed&#xff1b;0.01 \u00b5F \u4f18\u5148\u9009\u4f4e ESL \u578b<\/td>\n<\/tr>\n<tr>\n<td>\u9897\u7c92 VDDQ \u7403\u9644\u8fd1<\/td>\n<td>0.1 \u00b5F \u00d7 1 &#043; 0.047 \u00b5F \u00d7 1&#xff08;\u6bcf\u9897&#xff09;<\/td>\n<td>0201 \/ 0402<\/td>\n<td>10~150 MHz<\/td>\n<td>I\/O \u7535\u6e90\u566a\u58f0\u76f4\u63a5\u8fdb DQ \u773c\u56fe&#xff0c;\u4f18\u5148\u7ea7\u6700\u9ad8<\/td>\n<\/tr>\n<tr>\n<td>\u9897\u7c92 VPP<\/td>\n<td>0.1 \u00b5F \u00d7 1&#xff08;\u6bcf\u9897&#xff09;<\/td>\n<td>0402<\/td>\n<td>\u2014<\/td>\n<td>\u9760\u8fd1 VPP \u7403&#xff0c;\u56de\u6d41\u8def\u5f84\u77ed<\/td>\n<\/tr>\n<tr>\n<td>\u5b50\u901a\u9053\u533a\u57df\u4e2d\u9891<\/td>\n<td>1 \u00b5F \/ 2.2 \u00b5F \u00d7 \u6bcf 2 \u9897 1 \u53ea<\/td>\n<td>0603 \/ 0805<\/td>\n<td>1~10 MHz<\/td>\n<td>\u5747\u5300\u94fa\u5f00&#xff0c;\u4e0d\u8981\u96c6\u4e2d\u5728\u4e00\u5904<\/td>\n<\/tr>\n<tr>\n<td>Bulk&#xff08;\u6bcf\u4e2a\u5b50\u901a\u9053\u533a&#xff09;<\/td>\n<td>10 \u00b5F \/ 22 \u00b5F \u00d7 2~4<\/td>\n<td>0805 \/ 1206<\/td>\n<td>100 kHz~1 MHz<\/td>\n<td>\u9676\u74f7\u4f18\u5148&#xff1b;\u4f4e ESL \u9635\u5217\u7535\u5bb9\u66f4\u4f73<\/td>\n<\/tr>\n<tr>\n<td>VRM \u8f93\u51fa&#xff08;\u677f\u8f7d\u65b9\u6848&#xff09;<\/td>\n<td>100~330 \u00b5F&#xff08;\u9676\u74f7 &#043; \u805a\u5408\u7269\u5e76\u8054&#xff09;<\/td>\n<td>1210 \/ \u94bd \/ \u805a\u5408\u7269<\/td>\n<td>&lt; 100 kHz<\/td>\n<td>\u805a\u5408\u7269\u7535\u5bb9\u63d0\u4f9b ESR \u963b\u5c3c&#xff0c;\u6291\u5236\u53cd\u8c10\u632f\u5cf0<\/td>\n<\/tr>\n<tr>\n<td>\u63d2\u69fd\u9644\u8fd1&#xff08;\u6bcf\u6761 DIMM&#xff09;<\/td>\n<td>10 \u00b5F \u00d7 2~4 &#043; 1 \u00b5F \u00d7 4~6&#xff08;\u8f93\u5165 5 V\/12 V&#xff09;<\/td>\n<td>0805 \/ 1206<\/td>\n<td>\u8f93\u5165\u4fa7\u4fdd\u6301<\/td>\n<td>\u8f93\u5165\u7535\u5bb9\u4e0d\u8db3\u4f1a\u5728\u8d1f\u8f7d\u8df3\u53d8\u65f6\u62c9\u57ae\u8f93\u5165\u8f68<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u53bb\u8026\u5e03\u5c40\u786c\u89c4\u5219<\/p>\n<p>  1. \u9ad8\u9891\u7535\u5bb9&#xff08;0.1 \/ 0.01 uF&#xff09;\u5fc5\u987b\u8d34\u5728\u9897\u7c92\u80cc\u9762\u3001\u6b63\u5bf9\u7535\u6e90\u7403&#xff0c;<br \/>\n     \u8fc7\u5b54\u5230\u710a\u76d8\u8ddd\u79bb &lt;&#061; 1.0 mm&#xff0c;\u8fc7\u5b54\u5230\u5e73\u9762 &lt;&#061; 0.5 mm\u3002<br \/>\n  2. \u6bcf\u4e2a\u7535\u5bb9\u81f3\u5c11 2 \u4e2a\u8fc7\u5b54\u5230\u7535\u6e90\u5e73\u9762\u30012 \u4e2a\u8fc7\u5b54\u5230\u5730\u5e73\u9762&#xff0c;\u7981\u6b62\u5171\u7528\u8fc7\u5b54\u3002<br \/>\n  3. \u7535\u5bb9\u672c\u4f53\u5230 BGA \u7684\u8ddd\u79bb\u4f18\u5148\u4e8e\u300c\u5e03\u7ebf\u7f8e\u89c2\u300d&#xff1a;\u5b81\u53ef\u7ed5\u7ebf&#xff0c;\u4e0d\u8981\u632a\u8d70\u7535\u5bb9\u3002<br \/>\n  4. \u4e0d\u540c\u5bb9\u503c\u7535\u5bb9\u4e0d\u8981\u6392\u6210\u4e00\u6761\u76f4\u7ebf&#xff08;\u4f1a\u9020\u6210\u540c\u4e00\u65b9\u5411\u7684\u53cd\u8c10\u632f&#xff09;&#xff0c;<br \/>\n     \u91c7\u7528\u4ea4\u9519 \/ \u68cb\u76d8\u5f0f\u5e03\u7f6e\u3002<br \/>\n  5. 0201 \u4e0e 0402 \u6df7\u7528\u65f6\u6ce8\u610f\u56de\u6d41\u710a\u7684\u7acb\u7891\u98ce\u9669&#xff0c;0402 \u66f4\u7a33\u59a5\u3002<br \/>\n  6. \u677f\u8f7d\u65b9\u6848\u5728 VRM \u8f93\u51fa\u4fa7\u9884\u7559 1~2 \u4e2a bulk \u710a\u4f4d&#xff0c;\u4fbf\u4e8e\u8c03\u8bd5\u65f6\u8c03\u6574 ESR\/\u5bb9\u503c\u3002 <\/p>\n<h4 id=\"s3-5\">3.5 \u4e0a\u7535 \/ \u6389\u7535\u65f6\u5e8f<\/h4>\n<p>DDR5 \u4e0a\u7535 \/ \u590d\u4f4d \/ \u521d\u59cb\u5316\u65f6\u5e8f&#xff08;\u793a\u610f&#xff0c;\u65f6\u95f4\u8f74\u975e\u7b49\u6bd4&#xff09;t0 \u4f7f\u80fdt1 \u7ba1\u7406\u7535\u6e90 OKt2 VDD \u8fbe 90%t3 RESET_n \u91ca\u653et4 ZQCL \u5b8c\u6210t5 \u8bad\u7ec3\u9636\u6bb5t6 \u6b63\u5e38\u8bfb\u5199\u7ba1\u7406\/\u5907\u7528\u7535\u6e901.8 V \/ 3.3 V&#xff08;\u7ba1\u7406\u57df&#xff0c;\u5148\u884c\u5efa\u7acb&#xff09;VDD \/ VDDQ1.1 V\u5355\u8c03\u4e0a\u5347&#xff0c;\u7981\u6b62\u56de\u52fe\u2265 200 us \u7a33\u5b9a\u671f&#xff08;\u5178\u578b&#xff0c;\u4ee5 datasheet \u4e3a\u51c6&#xff09;VPP1.8 VVPP \u4e0e VDD \u540c\u65f6\u6216\u5148\u4e8e VDD \u5efa\u7acb&#xff0c;\u4efb\u610f\u65f6\u523b VPP \u2265 VDDRESET_n&#xff08;\u4f4e\u6709\u6548&#xff09;\u6574\u6bb5\u4f9b\u7535\u722c\u5347\u671f\u95f4\u4fdd\u6301\u4f4e\u7535\u5e73\u91ca\u653e\u540e\u9700\u7b49\u5f85 \u2265 \u89c4\u5b9a\u65f6\u95f4&#xff08;tXPR \u91cf\u7ea7&#xff09;\u624d\u5141\u8bb8\u53d1\u7b2c\u4e00\u6761\u547d\u4ee4&#xff08;\u89c1\u4e0b&#xff09;ZQCLCA \/ WL \/ RL \u8bad\u7ec3VREF \/ DFE \/ DCA\u6b64\u533a\u95f4&#xff1a;\u63a7\u5236\u5668\u3001PLL\u3001PHY \u4e0a\u7535&#xff0c;\u547d\u4ee4\u603b\u7ebf\u4fdd\u6301\u65e0\u6548\u6001<\/p>\n<p>\u56fe 3-1\u3000DDR5 \u4e0a\u7535\u4e0e\u590d\u4f4d\u65f6\u5e8f&#xff1a;\u7ba1\u7406\u7535\u6e90\u5148\u884c\u3001VDD\/VDDQ \u5355\u8c03\u4e0a\u5347\u3001VPP \u540c\u6b65\u6216\u63d0\u524d\u3001RESET_n \u5168\u7a0b\u62c9\u4f4e\u5e76\u5728\u7535\u6e90\u7a33\u5b9a\u540e\u91ca\u653e<\/p>\n<p>\u4e0a\u7535\u65f6\u5e8f\u89c4\u5219&#xff08;\u6574\u7406\u7248&#xff0c;\u6240\u6709\u5ef6\u65f6\u4ee5\u76ee\u6807 datasheet \u4e3a\u51c6&#xff09;<\/p>\n<p>  seq:<br \/>\n    1) \u7ba1\u7406\/\u5907\u7528\u7535\u6e90\u5efa\u7acb&#xff08;1.8 V \u6216 3.3 V&#xff0c;\u6309\u6a21\u7ec4\u89c4\u8303&#xff09;<br \/>\n    2) \u6a21\u7ec4\u8f93\u5165\u7535\u6e90 5 V \/ 12 V \u5efa\u7acb\u5e76\u7a33\u5b9a<br \/>\n    3) On-DIMM PMIC \u5b8c\u6210\u8f6f\u542f\u52a8&#xff0c;\u8f93\u51fa VPP(1.8 V) \u4e0e VDD\/VDDQ(1.1 V)<br \/>\n       &#8211; VPP \u4e0e VDD \u7684\u5148\u540e\u5173\u7cfb&#xff1a;VPP \u540c\u65f6\u6216\u5148\u4e8e VDD \u5efa\u7acb<br \/>\n       &#8211; \u4efb\u610f\u65f6\u523b\u6ee1\u8db3 VPP &gt;&#061; VDD<br \/>\n       &#8211; VDD \u4e0e VDDQ \u4e4b\u95f4\u901a\u5e38\u8981\u6c42\u540c\u65f6\u6216 VDDQ \u4e0d\u665a\u4e8e VDD<br \/>\n    4) \u7535\u6e90\u7a33\u5b9a\u5e76\u7ef4\u6301\u8db3\u591f\u65f6\u95f4&#xff08;\u5178\u578b &gt;&#061; 200 us \u91cf\u7ea7&#xff09;\u540e\u91ca\u653e RESET_n<br \/>\n    5) RESET_n \u91ca\u653e\u540e\u7b49\u5f85 tXPR&#xff08;\u91cf\u7ea7\u6570\u767e ns ~ us&#xff09;\u624d\u5141\u8bb8\u53d1\u7b2c\u4e00\u6761\u547d\u4ee4<br \/>\n    6) ZQCL&#xff08;\u957f\u6821\u51c6&#xff09;-&gt; tZQINIT \u7b49\u5f85<br \/>\n    7) \u8bad\u7ec3\u5e8f\u5217&#xff08;\u8be6\u89c1\u7b2c 5 \u7ae0&#xff09;<br \/>\n    8) \u6b63\u5e38\u8bfb\u5199<\/p>\n<p>  \u6389\u7535\u65f6\u5e8f&#xff1a;<br \/>\n    a) \u505c\u6b62\u6240\u6709\u8bbf\u95ee&#xff0c;\u53d1\u51fa PRECHARGE ALL \u5173\u95ed\u6240\u6709\u884c<br \/>\n    b) \u8fdb\u5165\u81ea\u5237\u65b0&#xff08;\u82e5\u9700\u4fdd\u6301\u6570\u636e&#xff09;\u6216\u76f4\u63a5\u4e0b\u7535<br \/>\n    c) \u62c9\u4f4e RESET_n&#xff08;\u63a8\u8350&#xff09;&#xff0c;\u786e\u4fdd DRAM \u5904\u4e8e\u786e\u5b9a\u6001<br \/>\n    d) \u64a4\u9664 VDD \/ VDDQ \/ VPP&#xff1a;VPP \u540c\u65f6\u6216\u665a\u4e8e VDD \u64a4\u9664<br \/>\n    e) \u4e25\u7981\u5728 VDD \u672a\u64a4\u9664\u65f6\u5355\u72ec\u64a4\u9664 VPP&#xff08;\u5b57\u7ebf\u504f\u7f6e\u5f02\u5e38\u98ce\u9669&#xff09;<\/p>\n<p>  \u8fdd\u53cd\u540e\u679c&#xff1a;<br \/>\n    &#8211; VDD \u4e0a\u5347\u975e\u5355\u8c03 \/ \u56de\u52fe -&gt; \u5185\u90e8\u72b6\u6001\u673a\u5361\u6b7b&#xff0c;\u8868\u73b0\u4e3a\u4e0a\u7535\u540e\u4e0d\u54cd\u5e94<br \/>\n    &#8211; VPP \u665a\u4e8e VDD -&gt; \u5b57\u7ebf\u9a71\u52a8\u4e0d\u8db3&#xff0c;\u8bfb\u5199\u5931\u8d25\u6216\u5355\u5143\u635f\u4f24<br \/>\n    &#8211; RESET_n \u91ca\u653e\u8fc7\u65e9 -&gt; \u521d\u59cb\u5316\u4e0d\u5b8c\u6574&#xff0c;\u8bad\u7ec3\u9636\u6bb5\u968f\u673a\u5931\u8d25 <\/p>\n<h5>\u81ea\u5237\u65b0\u4e0e\u6389\u7535\u4fdd\u6301<\/h5>\n<table>\n<tr>\u6a21\u5f0f\u8fdb\u5165\u65b9\u5f0f\u7535\u6d41\u91cf\u7ea7\u4fdd\u6301\u8981\u6c42\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u81ea\u5237\u65b0&#xff08;Self-Refresh&#xff09;<\/td>\n<td>SRE \u547d\u4ee4<\/td>\n<td>\u6570 mA ~ \u6570\u5341 mA&#xff08;\u968f\u6e29\u5ea6\u4e0a\u5347&#xff09;<\/td>\n<td>VDD\/VDDQ\/VPP \u5747\u9700\u4fdd\u6301<\/td>\n<td>\u6570\u636e\u4fdd\u6301\u9760\u5185\u90e8\u5237\u65b0&#xff1b;\u6e29\u5ea6\u8d8a\u9ad8\u5237\u65b0\u8d8a\u9891\u7e41\u3001\u7535\u6d41\u8d8a\u5927<\/td>\n<\/tr>\n<tr>\n<td>\u81ea\u5237\u65b0\u6389\u7535&#xff08;SRPD&#xff09;<\/td>\n<td>\u81ea\u5237\u65b0 &#043; \u5173\u65f6\u949f<\/td>\n<td>\u66f4\u4f4e<\/td>\n<td>\u540c\u4e0a<\/td>\n<td>CK \u53ef\u505c&#xff0c;\u8fdb\u4e00\u6b65\u7701\u7535<\/td>\n<\/tr>\n<tr>\n<td>\u6700\u5927\u7701\u7535 \/ \u6df1\u5ea6\u6389\u7535<\/td>\n<td>\u4f9d\u5668\u4ef6\u652f\u6301\u60c5\u51b5<\/td>\n<td>\u6700\u4f4e<\/td>\n<td>\u90e8\u5206\u5668\u4ef6\u53ef\u65ad VDDQ<\/td>\n<td>\u9700\u786e\u8ba4\u9000\u51fa\u6d41\u7a0b\u4e0e\u65f6\u95f4&#xff0c;\u5207\u52ff\u51ed\u7ecf\u9a8c\u64cd\u4f5c<\/td>\n<\/tr>\n<tr>\n<td>\u5b8c\u5168\u6389\u7535<\/td>\n<td>\u76f4\u63a5\u65ad\u7535<\/td>\n<td>0<\/td>\n<td>\u2014<\/td>\n<td>\u6570\u636e\u4e22\u5931&#xff1b;\u5fc5\u987b\u6309\u6389\u7535\u65f6\u5e8f\u6267\u884c<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4 id=\"s3-6\">3.6 \u529f\u8017\u4e0e\u70ed\u7ba1\u7406<\/h4>\n<table>\n<tr>\u9879\u76ee\u5178\u578b\u503c \/ \u89c4\u5219\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u6e29\u5ea6\u4f20\u611f&#xff08;TS&#xff09;<\/td>\n<td>SPD Hub \u5185\u7f6e&#xff08;\u5178\u578b 1~2 \u70b9&#xff09;&#043; \u9897\u7c92\u5185\u90e8 MR \u6e29\u5ea6<\/td>\n<td>\u4e24\u8def\u8bfb\u6570\u5e94\u5b9a\u671f\u4ea4\u53c9\u6838\u5bf9&#xff0c;\u504f\u5dee\u8fc7\u5927\u8bf4\u660e\u6563\u70ed\u6216\u4f20\u611f\u5668\u5f02\u5e38<\/td>\n<\/tr>\n<tr>\n<td>\u5237\u65b0\u7387\u5207\u6362\u70b9<\/td>\n<td>Tcase \u2248 85 \u00b0C<\/td>\n<td>\u8d85\u8fc7\u540e tREFI \u7531 3.9 \u00b5s \u6298\u534a\u5230 1.95 \u00b5s&#xff0c;\u5e26\u5bbd\u53ef\u89c2\u6d4b\u4e0b\u964d 5%~15%<\/td>\n<\/tr>\n<tr>\n<td>\u70ed\u8282\u6d41\u89e6\u53d1<\/td>\n<td>\u7531\u4e3b\u63a7\u6309 TS \u8bfb\u6570\u51b3\u5b9a&#xff0c;\u9608\u503c\u4f9d\u5e73\u53f0<\/td>\n<td>\u5178\u578b\u884c\u4e3a&#xff1a;\u964d\u901f\u7387 \/ \u964d\u5e76\u53d1 \/ \u9650\u5e26\u5bbd&#xff0c;\u4e25\u91cd\u65f6\u62a5\u9519<\/td>\n<\/tr>\n<tr>\n<td>\u6a21\u529f\u8017&#xff08;DDR5 DIMM&#xff09;<\/td>\n<td>\u7a7a\u95f2 2~5 W&#xff1b;\u6ee1\u8f7d 10~30 W&#xff08;\u4f9d\u5bb9\u91cf\u4e0e\u901f\u7387&#xff09;<\/td>\n<td>\u670d\u52a1\u5668\u6ee1\u914d\u673a\u7bb1\u5185\u662f\u4e3b\u8981\u70ed\u6e90\u4e4b\u4e00<\/td>\n<\/tr>\n<tr>\n<td>\u6563\u70ed\u63aa\u65bd<\/td>\n<td>\u6563\u70ed\u7247\u3001\u5bfc\u70ed\u5e26\u3001\u5f3a\u5236\u98ce\u9053&#xff08;\u2265 1.5 m\/s \u901a\u8fc7\u6a21\u7ec4\u8868\u9762&#xff09;<\/td>\n<td>\u6563\u70ed\u7247\u9700\u4e0e\u9897\u7c92\u9876\u9762\u8d34\u5408&#xff0c;\u5bfc\u70ed\u57ab\u539a\u5ea6 0.5~1.5 mm<\/td>\n<\/tr>\n<tr>\n<td>\u5e03\u5c40\u907f\u8ba9<\/td>\n<td>\u6a21\u7ec4\u4e0e CPU \/ GPU \u70ed\u6e90\u95f4\u8ddd \u2265 20 mm \u6216\u52a0\u5bfc\u6d41<\/td>\n<td>\u907f\u514d\u4e0b\u6e38\u6a21\u7ec4\u5904\u4e8e\u4e0a\u6e38\u70ed\u98ce\u51fa\u53e3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u70ed\u8282\u6d41\u4e0d\u662f\u300c\u4fdd\u62a4\u529f\u80fd\u300d&#xff0c;\u662f\u6027\u80fd\u4e8b\u6545<\/p>\n<p>DDR5 \u901f\u7387\u8d8a\u9ad8\u3001\u529f\u8017\u8d8a\u5927&#xff0c;\u4e14 tREFI \u672c\u8eab\u53ea\u6709 DDR4 \u7684\u4e00\u534a&#xff0c;\u9ad8\u6e29\u65f6\u8fdb\u4e00\u6b65\u6298\u534a\u3002\u5de5\u7a0b\u4e0a\u5e94\u628aTcase \u2264 85 \u00b0C \u4f5c\u4e3a\u786c\u6027\u8bbe\u8ba1\u76ee\u6807&#xff08;\u5de5\u6e29\u573a\u666f\u6309\u5668\u4ef6\u89c4\u683c&#xff09;\u3002\u82e5\u5728\u6574\u673a\u6d4b\u8bd5\u4e2d\u53d1\u73b0\u5185\u5b58\u5e26\u5bbd\u968f\u8fd0\u884c\u65f6\u95f4\u4e0b\u964d&#xff0c;\u7b2c\u4e00\u6b65\u5e94\u8bfb\u53d6 SPD Hub \u7684 TS \u4e0e PMIC \u9065\u6d4b\u6e29\u5ea6&#xff0c;\u786e\u8ba4\u662f\u5426\u8fdb\u5165 2\u00d7 \u5237\u65b0\u6216\u8282\u6d41\u533a&#xff0c;\u800c\u4e0d\u662f\u5148\u6000\u7591\u4fe1\u53f7\u5b8c\u6574\u6027\u3002<\/p>\n<h4 id=\"s3-7\">3.7 PDN \u76ee\u6807\u963b\u6297\u4e0e\u7535\u6e90\u5b8c\u6574\u6027<\/h4>\n<p>\u76ee\u6807\u963b\u6297\u6cd5&#xff08;\u677f\u8f7d\u65b9\u6848\u5fc5\u505a&#xff0c;\u6a21\u7ec4\u65b9\u6848\u505a\u8f93\u5165\u4fa7&#xff09;<\/p>\n<p>  Z_target &#061; \u5141\u8bb8\u7eb9\u6ce2\u7535\u538b \/ \u6700\u5927\u77ac\u6001\u7535\u6d41<\/p>\n<p>  \u4f8b&#xff1a;VDD &#061; 1.1 V&#xff0c;\u5141\u8bb8\u9ad8\u9891\u7eb9\u6ce2 15 mV&#xff0c;\u6700\u574f\u9636\u8dc3\u7535\u6d41 6 A<br \/>\n      Z_target &#061; 15 mV \/ 6 A &#061; 2.5 m\u03a9<\/p>\n<p>  \u63a7\u5236\u9891\u6bb5&#xff1a;<br \/>\n      F_max &#061; 1 \/ (2 x pi x t_r)     \u6216\u7ecf\u9a8c\u53d6 0.35 \/ t_r<br \/>\n      \u82e5\u7535\u6d41\u9636\u8dc3\u4e0a\u5347\u65f6\u95f4 t_r &#061; 50 ns -&gt;  F_max \u2248 7 MHz&#xff08;\u7531 bulk \u4e0e\u4e2d\u9891\u7535\u5bb9\u8986\u76d6&#xff09;<br \/>\n      \u82e5 t_r &#061; 5 ns -&gt; F_max \u2248 70 MHz&#xff08;\u5fc5\u987b\u7531\u9676\u74f7\u9635\u5217 &#043; \u5e73\u9762\u7535\u5bb9\u8986\u76d6&#xff09;<\/p>\n<p>  \u5206\u5c42\u63a7\u5236\u5efa\u8bae&#xff1a;<br \/>\n      &lt; 100 kHz      : VRM \u73af\u8def &#043; bulk&#xff08;\u805a\u5408\u7269 \/ \u7535\u89e3&#xff09;<br \/>\n      100 kHz~2 MHz  : \u4e2d\u9891\u9676\u74f7&#xff08;10 \/ 22 uF&#xff09;<br \/>\n      2 MHz~80 MHz   : \u9ad8\u9891\u9676\u74f7&#xff08;0.1 \/ 0.047 \/ 0.01 uF&#xff09;&#043; \u7535\u6e90\/\u5730\u5e73\u9762\u5bf9\u7535\u5bb9<br \/>\n      &gt; 80 MHz       : \u5c01\u88c5\u5185\u7535\u5bb9 &#043; \u82af\u7247\u5185\u7535\u5bb9&#xff08;\u8bbe\u8ba1\u8005\u53ea\u80fd\u901a\u8fc7\u5e73\u9762\u4e0e\u8fc7\u5b54\u4f18\u5316&#xff09;<\/p>\n<p>  \u5e73\u9762\u7535\u5bb9&#xff08;\u8584\u4ecb\u8d28\u7535\u6e90\u5730\u5e73\u9762\u5bf9&#xff09;\u662f\u6700\u4fbf\u5b9c\u7684 &gt;100 MHz \u53bb\u8026&#xff1a;<br \/>\n      \u91c7\u7528 2~4 mil \u4ecb\u8d28&#xff08;PP 106 \/ 1080&#xff09;\u7d27\u8026\u5408\u7535\u6e90\u5730\u5e73\u9762&#xff0c;<br \/>\n      \u5355\u4f4d\u9762\u79ef\u7535\u5bb9\u7ea6 100~250 pF\/cm^2&#xff0c;ESL \u6781\u4f4e\u3002 <\/p>\n<table>\n<tr>\u68c0\u67e5\u9879\u76ee\u6807\u4eff\u771f \/ \u6d4b\u91cf\u624b\u6bb5<\/tr>\n<tbody>\n<tr>\n<td>DC \u538b\u964d&#xff08;IR Drop&#xff09;<\/td>\n<td>VRM \u5230\u6700\u8fdc\u7aef\u9897\u7c92 \u2264 \u5141\u8bb8 DC \u8bef\u5dee\u7684\u4e00\u534a<\/td>\n<td>\u7535\u6e90\u5b8c\u6574\u6027 DC \u4eff\u771f&#xff08;\u5982 Cadence Sigrity \/ Ansys SIwave&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>AC \u963b\u6297\u66f2\u7ebf<\/td>\n<td>\u76ee\u6807\u9891\u6bb5\u5185 Z \u2264 Z_target&#xff0c;\u4e14\u65e0\u660e\u663e\u53cd\u8c10\u632f\u5cf0<\/td>\n<td>PDN AC \u4eff\u771f &#043; \u53bb\u8026\u65b9\u6848\u4f18\u5316<\/td>\n<\/tr>\n<tr>\n<td>\u53cd\u8c10\u632f\u5cf0<\/td>\n<td>\u5cf0\u503c\u963b\u6297 \u2264 1.5 \u00d7 Z_target<\/td>\n<td>\u8c03\u6574\u7535\u5bb9\u5bb9\u503c\u68af\u5ea6\u6216\u589e\u52a0 ESR&#xff08;\u805a\u5408\u7269\u7535\u5bb9&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u77ac\u6001\u54cd\u5e94<\/td>\n<td>\u5cf0\u5cf0\u503c \u2264 \u566a\u58f0\u9884\u7b97<\/td>\n<td>\u65f6\u57df\u4eff\u771f &#043; \u5b9e\u6d4b&#xff08;\u793a\u6ce2\u5668 &#043; \u7535\u6e90\u7eb9\u6ce2\u63a2\u5934&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>\u5b9e\u6d4b\u7eb9\u6ce2<\/td>\n<td>20 MHz \u5e26\u5bbd\u9650\u5236&#xff0c;\u4f7f\u7528\u540c\u8f74\/\u70b9\u6d4b\u63a2\u5934<\/td>\n<td>\u7981\u6b62\u4f7f\u7528\u957f\u63a5\u5730\u7ebf&#xff08;\u4f1a\u5f15\u5165\u6570\u5341 mV \u5047\u566a\u58f0&#xff09;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>4 \u00b7 \u5178\u578b\u5e94\u7528\u7535\u8def<\/h3>\n<p>\u672c\u8282\u7ed9\u51fa\u4e09\u79cd\u843d\u5730\u5f62\u6001\u7684\u539f\u7406\u56fe&#xff08;\u5185\u8054\u7ed8\u5236&#xff09;&#xff1a;\u677f\u8f7d\u9897\u7c92\u70b9\u5bf9\u70b9\u3001UDIMM\/SODIMM \u63d2\u69fd\u3001RDIMM&#xff08;\u542b RCD&#xff09;\u3002\u6240\u6709\u7f51\u7edc\u5747\u6309\u7b2c 6 \u7ae0\u7684\u963b\u6297\u4e0e\u7b49\u957f\u89c4\u5219\u5e03\u7ebf\u3002<\/p>\n<h4 id=\"s4-1\">4.1 \u677f\u8f7d&#xff08;down&#xff09;\u9897\u7c92\u70b9\u5bf9\u70b9\u65b9\u6848<\/h4>\n<p>DDR5 \u677f\u8f7d&#xff08;down&#xff09;\u70b9\u5bf9\u70b9\u65b9\u6848 \u2014\u2014 \u5355\u5b50\u901a\u9053 32 bit&#xff08;4 \u00d7 x8 \u9897\u7c92&#xff09;CPU \/ SoC\u96c6\u6210 DDR5 \u63a7\u5236\u5668 &#043; PHYCK_A_t \/ CK_A_cCA_A[13:0]CS_A_nDQ_A[31:0]DQS_A_t\/c \u00d74DM_A_n \u00d74CB_A[7:0]ALERT_nRESET_nTENLoopback_A \/ _BHSCL \/ HSDA&#xff08;\u5b50\u901a\u9053 B \u5f15\u811a\u5bf9\u79f0\u5b58\u5728&#xff0c;\u672c\u56fe\u7701\u7565\u7ed8\u5236&#xff09;U1 DDR5 x8 16 GbDQ[7:0] \/ DQS \/ DM_n \/ FBGA-82U2 DDR5 x8 16 GbDQ[15:8] \/ DQS \/ DM_nU3 DDR5 x8 16 GbDQ[23:16] \/ DQS \/ DM_nU4 DDR5 x8 16 GbUECC DDR5 x8&#xff08;CB[7:0]&#xff09;\u6821\u9a8c\u4f4d\u9897\u7c92&#xff08;\u82e5\u4e3b\u63a7\u542f\u7528\u540c\u5e27 ECC&#xff09;CK_A_t\/c \u5dee\u5206 80 \u03a9&#xff0c;Fly-by&#xff0c;\u7b49\u957f \u00b110 milCA_A[13:0] &#043; CS_A_n&#xff1a;Fly-by \u4f9d\u6b21\u4e32\u8054 4 \u9897&#xff0c;\u672b\u7aef\u7aef\u63a5RttCA \u7aef\u63a5DQ_A[31:0] &#043; DQS_A \u00d74 &#043; DM_A_n \u00d74&#xff08;\u70b9\u5bf9\u70b9&#xff0c;\u6bcf\u5b57\u8282\u7ec4\u72ec\u7acb\u7b49\u957f&#xff09;DQ \u4e0d\u7ecf CA \u7684 Fly-by&#xff0c;\u76f4\u63a5\u70b9\u5bf9\u70b9\u5230\u5bf9\u5e94\u9897\u7c92CB_A[7:0] \u6821\u9a8c\u4f4d&#xff0c;\u4e0e DQ \u540c\u5e27\u3001\u540c\u5b50\u901a\u9053\u7b49\u957f10kALERT_n \u5f00\u6f0f&#xff0c;\u9700\u4e0a\u62c9&#xff1b;\u591a rank \u7ebf\u4e0e10kRESET_n&#xff1a;\u4e0b\u62c9\u4fdd\u8bc1\u4e0a\u7535\u4e3a\u4f4e&#xff1b;\u5efa\u8bae\u4e3b\u63a7 GPIO \u53ef\u62c9\u9ad8TEN&#xff1a;\u6b63\u5e38\u5de5\u4f5c\u4fdd\u6301\u65e0\u6548&#xff0c;\u9884\u7559\u4e0b\u62c9&#xff08;\u7535\u5e73\u4f9d datasheet&#xff09;Loopback&#xff1a;\u8bad\u7ec3\u53cd\u9988\u56de\u4e3b\u63a7&#xff0c;\u7981\u6b62\u8bef\u63a5\u4e0a\u62c9\/\u4e0b\u62c9PMIC \/ \u591a\u8def DC-DC&#xff08;\u677f\u8f7d\u65b9\u6848\u81ea\u5efa&#xff09;5 V \u6216 12 V \u8f93\u5165 \u2192 VDD 1.1 V \/ VDDQ 1.1 V \/ VPP 1.8 V\u9700\u8f6f\u542f\u52a8\u3001Power Good\u3001\u4f7f\u80fd\u65f6\u5e8f\u63a7\u5236\u4e0e\u9065\u6d4bVIN 5 V \/ 12 VVDD \/ VDDQVPP 1.8 V\u53bb\u8026\u9635\u5217 0.1 \u00b5F \/ 0.01 \u00b5F&#xff08;\u9897\u7c92\u80cc\u9762&#xff09;240 \u03a9ZQ\u00b11%\u6bcf\u9897 DRAM \u5404\u914d 1 \u53ea 240 \u03a9&#xff0c;\u8ddd ZQ \u7403 \u2264 5 mm&#xff0c;\u7981\u6b62\u8fc7\u5b54<\/p>\n<p>\u56fe 4-1\u3000\u677f\u8f7d\u70b9\u5bf9\u70b9\u65b9\u6848&#xff1a;CK\/CA\/CS \u8d70 Fly-by \u5e76\u672b\u7aef\u7aef\u63a5&#xff0c;DQ\/DQS\/DM\/CB \u70b9\u5bf9\u70b9&#xff0c;PMIC \u81ea\u5efa\u4e09\u8def\u7535\u6e90&#xff0c;ZQ \u4e0e\u53bb\u8026\u8d34\u8fd1\u9897\u7c92<\/p>\n<h5>\u677f\u8f7d\u65b9\u6848\u9010\u7f51\u7edc\u8bf4\u660e<\/h5>\n<table>\n<tr>\u7f51\u7edc\u8fde\u63a5\u62d3\u6251\u7aef\u63a5 \/ \u4e0a\u62c9\u5173\u952e\u70b9<\/tr>\n<tbody>\n<tr>\n<td>CK_A_t \/ CK_A_c<\/td>\n<td>SoC \u2192 4 \u9897\u7c92<\/td>\n<td>Fly-by&#xff08;\u4e32\u63a5&#xff0c;\u672b\u7aef\u7aef\u63a5&#xff09;<\/td>\n<td>\u672b\u7aef\u5dee\u5206\u7aef\u63a5&#xff08;\u5178\u578b 80 \u03a9 \u5dee\u5206&#xff0c;\u6216\u4f9d PDG&#xff09;<\/td>\n<td>\u5dee\u5206\u5bf9\u5185 \u00b11~2 mil&#xff1b;\u5168\u7a0b\u540c\u5c42&#xff1b;\u7981\u6b62\u5206\u652f<\/td>\n<\/tr>\n<tr>\n<td>CA_A[13:0]<\/td>\n<td>SoC \u2192 4 \u9897\u7c92<\/td>\n<td>Fly-by<\/td>\n<td>\u672b\u7aef\u5355\u7aef\u7aef\u63a5&#xff08;\u5178\u578b 40~60 \u03a9&#xff0c;\u7aef\u63a5\u7535\u6e90\u4f9d PDG&#xff09;<\/td>\n<td>\u7ec4\u5185\u7b49\u957f \u00b110 mil&#xff1b;\u4e0e CK \u957f\u5ea6\u5dee\u6309 PDG&#xff08;\u5178\u578b \u00b120~50 mil&#xff09;<\/td>\n<\/tr>\n<tr>\n<td>CS_A_n<\/td>\n<td>SoC \u2192 \u6bcf rank \u4e00\u6839<\/td>\n<td>Fly-by&#xff08;\u4e0e CA \u540c\u5e8f&#xff09;<\/td>\n<td>\u4e0e CA \u540c\u7aef\u63a5\u7b56\u7565<\/td>\n<td>\u5355 rank \u65f6\u53ef\u89c6\u4e3a CA \u7ec4\u6210\u5458\u4e00\u8d77\u7b49\u957f<\/td>\n<\/tr>\n<tr>\n<td>DQ_A[31:0]<\/td>\n<td>SoC \u2194 \u9897\u7c92&#xff08;\u6bcf\u9897 8 bit&#xff09;<\/td>\n<td>\u70b9\u5bf9\u70b9<\/td>\n<td>\u7247\u5185 ODT&#xff08;DRAM \u4fa7 &#043; \u4e3b\u63a7\u4fa7&#xff09;<\/td>\n<td>\u6bcf\u5b57\u8282\u7ec4\u4e0e\u5bf9\u5e94 DQS \u7b49\u957f \u00b13~5 mil<\/td>\n<\/tr>\n<tr>\n<td>DQS_A_t\/c \u00d74<\/td>\n<td>SoC \u2194 \u9897\u7c92<\/td>\n<td>\u70b9\u5bf9\u70b9\u5dee\u5206<\/td>\n<td>\u5dee\u5206 ODT<\/td>\n<td>\u5dee\u5206\u5bf9\u5185 \u00b11~2 mil&#xff1b;\u4e0e CK \u7684\u957f\u5ea6\u5173\u7cfb\u7531 write leveling \u8865\u507f<\/td>\n<\/tr>\n<tr>\n<td>DM_A_n \u00d74<\/td>\n<td>SoC \u2192 \u9897\u7c92<\/td>\n<td>\u70b9\u5bf9\u70b9<\/td>\n<td>\u540c DQ<\/td>\n<td>\u4e0e\u540c\u5b57\u8282\u7ec4 DQ \u7b49\u957f<\/td>\n<\/tr>\n<tr>\n<td>CB_A[7:0]<\/td>\n<td>SoC \u2194 \u6821\u9a8c\u9897\u7c92<\/td>\n<td>\u70b9\u5bf9\u70b9<\/td>\n<td>\u540c DQ<\/td>\n<td>\u4e0e DQ \u7ec4\u7b49\u957f&#xff0c;\u957f\u5ea6\u5dee\u7eb3\u5165\u540c\u7ec4\u5339\u914d<\/td>\n<\/tr>\n<tr>\n<td>ALERT_n<\/td>\n<td>SoC \u2190 \u6240\u6709\u9897\u7c92&#xff08;\u7ebf\u4e0e&#xff09;<\/td>\n<td>\u591a\u70b9<\/td>\n<td>\u4e0a\u62c9 4.7~10 k\u03a9&#xff08;\u7535\u6e90\u57df\u4f9d datasheet&#xff09;<\/td>\n<td>\u8d70\u7ebf\u77ed\u3001\u8fdc\u79bb\u9ad8\u901f&#xff1b;\u9884\u7559\u6d4b\u8bd5\u70b9<\/td>\n<\/tr>\n<tr>\n<td>RESET_n<\/td>\n<td>SoC \u2192 \u6240\u6709\u9897\u7c92<\/td>\n<td>\u591a\u70b9<\/td>\n<td>\u4e0b\u62c9 1~10 k\u03a9 &#043; \u53ef\u62c9\u9ad8<\/td>\n<td>\u4e0a\u7535\u671f\u95f4\u5fc5\u987b\u4e3a\u4f4e&#xff1b;\u6ce8\u610f\u590d\u4f4d\u671f\u95f4\u4e0d\u5f97\u6d6e\u7a7a<\/td>\n<\/tr>\n<tr>\n<td>TEN<\/td>\n<td>SoC \u2192 \u6240\u6709\u9897\u7c92<\/td>\n<td>\u591a\u70b9<\/td>\n<td>\u4e0b\u62c9&#xff08;\u4f9d datasheet&#xff09;<\/td>\n<td>\u4ec5\u6d4b\u8bd5\/\u8bad\u7ec3\u4f7f\u7528&#xff0c;\u6b63\u5e38\u4fdd\u6301\u65e0\u6548<\/td>\n<\/tr>\n<tr>\n<td>Loopback<\/td>\n<td>SoC \u2190 \u9897\u7c92<\/td>\n<td>\u70b9\u5bf9\u70b9<\/td>\n<td>\u4e0d\u52a0\u4e0a\u4e0b\u62c9<\/td>\n<td>\u53cd\u9988\u8bad\u7ec3\u7528&#xff0c;\u8d70\u7ebf\u7b49\u957f\u5230\u4e3b\u63a7&#xff0c;\u7981\u6b62\u5e76\u8054<\/td>\n<\/tr>\n<tr>\n<td>ZQ<\/td>\n<td>\u9897\u7c92 \u2192 240 \u03a9 \u2192 \u5730&#xff08;\u6216\u6307\u5b9a\u7535\u4f4d&#xff09;<\/td>\n<td>\u2014<\/td>\n<td>\u2014<\/td>\n<td>\u6bcf\u9897 1 \u53ea&#xff1b;\u2264 5 mm&#xff1b;1% \u7cbe\u5ea6<\/td>\n<\/tr>\n<tr>\n<td>VDD \/ VDDQ \/ VPP<\/td>\n<td>PMIC \u2192 \u9897\u7c92<\/td>\n<td>\u5e73\u9762 \/ \u94dc\u76ae<\/td>\n<td>\u53bb\u8026\u9635\u5217\u89c1 3.4<\/td>\n<td>VPP \u72ec\u7acb\u8d70\u7ebf\u4e0e\u53bb\u8026<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4 id=\"s4-2\">4.2 UDIMM \/ SODIMM \u63d2\u69fd\u65b9\u6848<\/h4>\n<p>DDR5 \u6a21\u7ec4\u65b9\u6848&#xff1a;\u4e3b\u63a7 \u2194 288 pin \u63d2\u69fd \u2194 UDIMM \/ RDIMM&#xff08;\u542b On-DIMM PMIC \u4e0e SPD Hub&#xff09;CPU \/ SoC \/ BMCCK_A\/B\u3001CA_A\/B\u3001CS_A\/BDQ_A\/B[31:0]\u3001DQS_A\/BDM_A\/B\u3001CB_A\/B[7:0]ALERT_n \/ RESET_n \/ TENLoopback_A \/ Loopback_BHSCL \/ HSDA&#xff08;\u7ba1\u7406&#xff09;GPIO \/ \u5728\u4f4d\u68c0\u6d4b\u4e3b\u63a7\u4fa7\u5b8c\u6210\u5168\u90e8\u8bad\u7ec3&#xff1a;CA \/ WL \/ RL \/ VREF \/DFE \/ DCA \/ Loopback\u4e3b\u677f\u7535\u6e905 V&#xff08;UDIMM\/SODIMM&#xff09;\u6216 12 V&#xff08;RDIMM&#xff09;288 pin DDR5 \u63d2\u69fd&#xff08;UDIMM \/ RDIMM&#xff09;\u3000\u91d1\u624b\u6307 30 \u00b5&#034; Au&#xff0c;\u5361\u53e3\u9632\u5446DDR5 DIMM&#xff08;\u6a21\u7ec4\u4fa7&#xff09;DDR5 \u9897\u7c92\u9635\u5217\u5b50\u901a\u9053 A&#xff1a;4~8 \u9897&#xff08;32 bit &#043; 8 CB&#xff09;\u5b50\u901a\u9053 B&#xff1a;4~8 \u9897&#xff08;32 bit &#043; 8 CB&#xff09;RCD\u5bc4\u5b58\u65f6\u949f\u9a71\u52a8\u5668&#xff08;RDIMM \u5fc5\u9009&#xff09;DB \/ MDB&#xff08;LRDIMM \u624d\u6709&#xff0c;\u7f13\u51b2 DQ&#xff09;On-DIMM PMIC5 V \/ 12 V \u2192 VDD 1.1 V \/ VDDQ 1.1 V \/ VPP 1.8 V&#xff08;SMBus\/I3C \u53ef\u914d&#xff09;SPD Hub&#043; TS \u6e29\u5ea6\u4f20\u611fSPD \u6570\u636e &#043; I3C Hub\u5730\u5740\u7531 SA0~SA2 \u8bbe\u5b9a\u70ed\u8282\u6d41\u6e29\u5ea6\u4e0a\u62a5VDD\/VDDQ\/VPPHSCL\/HSDA\u6a21\u7ec4\u5185\u90e8\u7ba1\u7406\u603b\u7ebf\u9ad8\u901f\u603b\u7ebf&#xff1a;CK \/ CA \/ CS \/ DQ \/ DQS \/ DM \/ CB \/ Loopback&#xff08;\u5dee\u5206 80 \u03a9\u3001\u5355\u7aef 40 \u03a9&#xff09;5 V \/ 12 V \u2192 \u6a21\u7ec4 PMIC\u4e0a\u62c9\u7ba1\u7406\u4fa7&#xff1a;ALERT_n \u4e0a\u62c9\u3001RESET_n \u53ef\u63a7\u3001TEN \u4e0b\u62c9\u8f93\u5165\u4fa7\u53bb\u8026&#xff1a;\u6bcf\u6761\u63d2\u69fd 10 \u00b5F \u00d72~4 &#043; 1 \u00b5F \u00d74~6&#xff08;\u89c1 3.4&#xff09;\u4e3b\u63a7\u5230\u63d2\u69fd\u8d70\u7ebf&#xff1a;6400 MT\/s \u65f6\u5efa\u8bae \u2264 4~6 inch&#xff0c;\u542b\u8fde\u63a5\u5668\u635f\u8017\u6309\u7b2c 6 \u7ae0\u6838\u7b97<\/p>\n<p>\u56fe 4-2\u3000\u6a21\u7ec4\u65b9\u6848&#xff1a;\u4e3b\u677f\u53ea\u9001 5 V\/12 V \u4e0e\u7ba1\u7406\u603b\u7ebf&#xff0c;\u7535\u538b\u8c03\u8282\u7531 On-DIMM PMIC \u5b8c\u6210&#xff1b;RDIMM \u7684 CK\/CA\/CS \u7ecf RCD \u5bc4\u5b58&#xff0c;LRDIMM \u7684 DQ \u518d\u7ecf DB \u7f13\u51b2<\/p>\n<h5>\u63d2\u69fd\u65b9\u6848\u8bbe\u8ba1\u8981\u70b9<\/h5>\n<table>\n<tr>\u9879\u76ee\u8981\u6c42\u8bf4\u660e<\/tr>\n<tbody>\n<tr>\n<td>\u63d2\u69fd\u9009\u578b<\/td>\n<td>\u5fc5\u987b\u4f7f\u7528 DDR5 \u4e13\u7528 288 pin \u63d2\u69fd&#xff08;\u4e0e DDR4 \u7269\u7406\u4e0d\u517c\u5bb9&#xff09;<\/td>\n<td>\u5361\u53e3\u4f4d\u7f6e\u4e0e DDR4 \u4e0d\u540c&#xff1b;\u4e0d\u53ef\u6df7\u63d2&#xff0c;\u4e5f\u4e0d\u53ef\u7528 DDR4 \u63d2\u69fd\u66ff\u4ee3<\/td>\n<\/tr>\n<tr>\n<td>\u91d1\u624b\u6307\u9540\u5c42<\/td>\n<td>\u63a8\u8350 30 \u00b5&#034;&#xff08;0.76 \u00b5m&#xff09;\u786c\u91d1&#xff0c;\u63d2\u62d4\u5bff\u547d \u2265 25 \u6b21<\/td>\n<td>15 \u00b5&#034; \u5728\u591a\u6b21\u63d2\u62d4\u540e\u63a5\u89e6\u7535\u963b\u4e0a\u5347&#xff0c;\u4f1a\u5f71\u54cd\u9ad8\u901f\u4fe1\u53f7<\/td>\n<\/tr>\n<tr>\n<td>\u63d2\u69fd\u56fa\u5b9a<\/td>\n<td>\u4e24\u4fa7\u5361\u6263 &#043; \u5b9a\u4f4d\u67f1&#xff1b;\u632f\u52a8\u573a\u666f\u52a0\u9501\u56fa\u4ef6<\/td>\n<td>\u63a5\u89e6\u4e0d\u826f\u4f1a\u8868\u73b0\u4e3a\u8bad\u7ec3\u5931\u8d25\u6216\u95f4\u6b47\u6027\u62a5\u9519<\/td>\n<\/tr>\n<tr>\n<td>\u63d2\u69fd\u4e0b\u65b9\u5e03\u7ebf<\/td>\n<td>\u7981\u6b62\u5728\u63d2\u69fd\u6b63\u4e0b\u65b9\u8d70\u9ad8\u901f\u7ebf\u6216\u653e\u7f6e\u8fc7\u5b54\u9635\u5217<\/td>\n<td>\u4f1a\u9020\u6210\u53c2\u8003\u5e73\u9762\u4e0d\u8fde\u7eed\u4e0e\u63d2\u635f\u6076\u5316<\/td>\n<\/tr>\n<tr>\n<td>\u8f93\u5165\u7535\u6e90<\/td>\n<td>5 V \u6216 12 V&#xff08;\u6309\u63d2\u69fd\u5b9a\u4e49&#xff09;&#xff0c;\u6bcf\u6761\u72ec\u7acb\u9650\u6d41\/\u4fdd\u62a4<\/td>\n<td>\u70ed\u63d2\u62d4&#xff08;\u82e5\u652f\u6301&#xff09;\u9700\u7f13\u542f\u52a8\u4e0e\u6d6a\u6d8c\u6291\u5236<\/td>\n<\/tr>\n<tr>\n<td>\u5728\u4f4d\u68c0\u6d4b<\/td>\n<td>\u9884\u7559\u673a\u68b0\/\u7535\u6c14\u68c0\u6d4b&#xff0c;\u907f\u514d\u7a7a\u8f7d\u63d2\u69fd\u8bef\u62a5<\/td>\n<td>\u591a\u63d2\u69fd\u7cfb\u7edf\u6309\u9700\u5173\u95ed\u7a7a\u69fd\u7684\u65f6\u949f\u4e0e\u7535\u6e90<\/td>\n<\/tr>\n<tr>\n<td>SODIMM<\/td>\n<td>262 pin&#xff0c;0.5 mm pitch&#xff0c;\u540c\u6837\u53cc 40 bit \u5b50\u901a\u9053<\/td>\n<td>\u7a7a\u95f4\u53d7\u9650&#xff0c;\u9700\u6ce8\u610f\u63d2\u69fd\u4e0b\u65b9\u7981\u5e03\u533a\u4e0e\u6a21\u7ec4\u9ad8\u5ea6<\/td>\n<\/tr>\n<tr>\n<td>CAMM2 \/ LPCAMM2<\/td>\n<td>\u538b\u7f29\u8fde\u63a5\u5668&#xff0c;\u538b\u63a5\u65b9\u5f0f&#xff0c;\u8d70\u7ebf\u66f4\u77ed<\/td>\n<td>\u53ef\u652f\u6301\u66f4\u9ad8\u901f\u7387&#xff08;8000&#043;&#xff09;&#xff1b;\u9700\u4e13\u7528\u8fde\u63a5\u5668\u4e0e\u538b\u63a5\u5de5\u827a<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4 id=\"s4-3\">4.3 RDIMM&#xff08;\u542b RCD&#xff09;\u65b9\u6848\u7684\u989d\u5916\u6ce8\u610f<\/h4>\n<table>\n<tr>\u9879\u76ee\u8bf4\u660e\u8bbe\u8ba1\u52a8\u4f5c<\/tr>\n<tbody>\n<tr>\n<td>RCD \u5f15\u5165\u7684\u56fa\u5b9a\u5ef6\u8fdf<\/td>\n<td>CK\/CA \u7ecf RCD \u518d\u9a71\u52a8&#xff0c;\u4e3b\u63a7\u8bad\u7ec3\u7ed3\u679c\u9700\u5305\u542b RCD \u5ef6\u8fdf<\/td>\n<td>\u8bad\u7ec3\u7b97\u6cd5\u7531\u4e3b\u63a7 MRC \u5904\u7406&#xff0c;\u786c\u4ef6\u4e0a\u53ea\u9700\u4fdd\u8bc1 RCD \u4f9b\u7535\u4e0e\u65c1\u8def\u7535\u5bb9\u7b26\u5408\u8981\u6c42<\/td>\n<\/tr>\n<tr>\n<td>RCD \u7535\u6e90<\/td>\n<td>\u7531 On-DIMM PMIC \u4f9b\u7535&#xff08;\u5e38\u89c1 1.1 V \u57df&#xff09;<\/td>\n<td>\u6a21\u7ec4\u4fa7\u5df2\u5904\u7406&#xff1b;\u4e3b\u677f\u65e0\u9700\u989d\u5916\u4f9b RCD \u7535\u6e90<\/td>\n<\/tr>\n<tr>\n<td>CA \u62d3\u6251\u6539\u53d8<\/td>\n<td>\u4e3b\u63a7 \u2192 RCD \u2192 \u9897\u7c92&#xff08;\u4e24\u6bb5&#xff09;<\/td>\n<td>\u4e3b\u677f\u53ea\u8d1f\u8d23\u4e3b\u63a7\u5230\u63d2\u69fd\u8fd9\u4e00\u6bb5&#xff1b;\u6bb5\u5185 Fly-by \u7531\u6a21\u7ec4\u5b8c\u6210<\/td>\n<\/tr>\n<tr>\n<td>DB&#xff08;LRDIMM&#xff09;<\/td>\n<td>DQ \u4e5f\u7f13\u51b2&#xff0c;\u5f80\u8fd4\u5ef6\u8fdf\u589e\u52a0<\/td>\n<td>\u5ef6\u8fdf\u654f\u611f\u573a\u666f\u614e\u7528 LRDIMM&#xff1b;\u5bb9\u91cf\u4f18\u5148\u65f6\u9009\u7528<\/td>\n<\/tr>\n<tr>\n<td>RCD \u914d\u7f6e<\/td>\n<td>\u90e8\u5206\u5e73\u53f0\u5728\u8bad\u7ec3\u524d\u9700\u901a\u8fc7\u7ba1\u7406\u603b\u7ebf\u914d\u7f6e RCD \u5bc4\u5b58\u5668<\/td>\n<td>\u786e\u8ba4\u4e3b\u63a7 MRC \u652f\u6301\u8be5 RCD \u578b\u53f7&#xff08;\u517c\u5bb9\u6027\u6e05\u5355&#xff09;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\u5f62\u6001\u9009\u62e9\u5c0f\u7ed3<\/p>\n<p>\u901f\u7387\u4f18\u5148 &#043; \u56fa\u5b9a\u914d\u7f6e \u2192\u00a0\u677f\u8f7d x16 \u9897\u7c92&#xff08;\u8d70\u7ebf\u6700\u77ed\u3001\u65e0\u8fde\u63a5\u5668&#xff09;\u3002\u5bb9\u91cf\u4e0e\u53ef\u7ef4\u62a4\u4f18\u5148 \u2192\u00a0UDIMM\/RDIMM \u63d2\u69fd&#xff08;\u22646400 MT\/s \u7a33\u59a5&#xff0c;\u66f4\u9ad8\u9700\u4e25\u683c\u8bc4\u4f30\u901a\u9053\u4f59\u91cf&#xff09;\u3002\u7a7a\u95f4\u53d7\u9650 &#043; \u9ad8\u901f \u2192\u00a0CAMM2\/LPCAMM2\u3002\u7535\u6c60\u4f9b\u7535 \u2192\u00a0LPDDR5(X)&#xff0c;\u4e0d\u8981\u7528 DDR5\u3002<\/p>\n<p>\u4e2d\u6587\u786c\u4ef6\u6280\u672f\u6587\u6863\u7cfb\u5217 \u00b7 DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 \u00b7 \u4ee5\u76ee\u6807\u578b\u53f7 datasheet \u4e0e\u4e3b\u63a7 DDR \u63a7\u5236\u5668\u8bbe\u8ba1\u6307\u5357\u4e3a\u51c6<\/p>\n<h3>\u540e\u7eed\u7ae0\u8282\u8bf7\u4e0b\u8f7d\u300c\u82af\u53c2\u8c0b\u300d\u67e5\u770b<\/h3>\n<p>\u2026\u2026&#xff08;\u7bc7\u5e45\u539f\u56e0, \u8fd8\u670910\u7ae0\u00b7 \u8be6\u89c1\u82af\u53c2\u8c0b\u2192\u65b9\u6848\u8bbe\u8ba1&#xff09;<\/p>\n<p>\u5f53\u524d\u5206\u4eab\u4ec5\u5f00\u653e\u524d\u00a05\u00a0\u7ae0\u6b63\u6587\u3002\u8be6\u7ec6\u8d44\u6599\u8bf7\u5728\u82af\u53c2\u8c0b\u5ba2\u6237\u7aef\u4e2d\u6253\u5f00\u5b8c\u6574\u6587\u6863\u3002<\/p>\n<p>\u6253\u5f00\u8def\u5f84&#xff1a;&#x1f527;\u89e3\u51b3\u65b9\u6848&amp;\u5e94\u7528\u5e02\u573a\u5206\u6790 -&gt; \u539f\u7406\u65b9\u6848\u8bbe\u8ba1 -&gt; DRAM\u7cfb\u5217\u4ea7\u54c1\u65b9\u6848 -&gt; DDR5_\u7535\u8def\u8bbe\u8ba1\u6307\u5357<\/p>\n<p>&#x1f4e5; \u4e0b\u8f7d\u82af\u53c2\u8c0b\u5ba2\u6237\u7aef(\u514d\u8d39\u67e5\u770b)<\/p>\n<p>\u76f8\u5173\u62a5\u544a \u00b7 1<\/p>\n<ul>\n<li>\u5149\u4f0f\u8ddf\u8e2a\u63a7\u5236\u5668(Solar Tracker Controller)_\u5e02\u573a\u5206\u6790\u5e02\u573a\u5e94\u7528\u5206\u6790<\/li>\n<li>Load_Switch_\u7cfb\u7edf\u8bbe\u8ba1\u6307\u5357\u539f\u7406\u65b9\u6848\u8bbe\u8ba1<\/li>\n<li>MOSFET_\u91cf\u4ea7\u5931\u6548\u4e0e\u6765\u6599\u5dee\u5f02_\u91cf\u4ea7\u6392\u67e5\u8c03\u8bd5&amp;\u89e3\u51b3\u65b9\u6848<\/li>\n<li>\u5206\u533a\u9519\u4f4d_\u574f\u5757\u8df3\u8fc7\u4e0d\u4e00\u81f4_\u91cf\u4ea7\u6392\u67e5\u8c03\u8bd5&amp;\u89e3\u51b3\u65b9\u6848<\/li>\n<li>\u4fe1\u521b\u786c\u4ef6(XC Hardware)_\u5e02\u573a\u5206\u6790\u5e02\u573a\u5e94\u7528\u5206\u6790<\/li>\n<\/ul>\n<p>\u76f8\u5173\u62a5\u544a \u00b7 2<\/p>\n<ul>\n<li>LEDDriver_\u8c03\u5149\u4e0e\u6052\u6d41\u5f02\u5e38_\u6837\u673a\u6392\u67e5\u8c03\u8bd5&amp;\u89e3\u51b3\u65b9\u6848<\/li>\n<li>eMCP_\u7535\u8def\u8bbe\u8ba1\u6307\u5357\u539f\u7406\u65b9\u6848\u8bbe\u8ba1<\/li>\n<li>\u6db2\u51b7\u63a7\u5236\u677f(CDU)_\u5e02\u573a\u5206\u6790\u5e02\u573a\u5e94\u7528\u5206\u6790<\/li>\n<li>\u626b\u62d6\u4e00\u4f53\u673a\u5668\u4eba(Vacuum-Mop Robot)_\u5e02\u573a\u5206\u6790\u5e02\u573a\u5e94\u7528\u5206\u6790<\/li>\n<li>SPI_\u56db\u79cd\u5de5\u4f5c\u6a21\u5f0f_\u6280\u672f\u62a5\u544a\u8c03\u8bd5&amp;\u89e3\u51b3\u65b9\u6848<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>\u9002\u7528\u8303\u56f4<br \/>\n\u672c\u6587\u9488\u5bf9\u00a0DDR5 SDRAM&#xff08;JESD79-5 \u7cfb\u5217&#xff09;\u7684\u786c\u4ef6\u7535\u8def\u8bbe\u8ba1&#xff0c;\u8986\u76d6\u9897\u7c92&#xff08;down \/ \u677f\u8f7d&#xff09;\u4e0e\u6a21\u7ec4&#xff08;UDIMM\u3001SODIMM\u3001RDIMM\u3001LRDIMM&#xff09;\u4e24\u7c7b\u843d\u5730\u5f62\u6001&#xff0c;\u901f\u7387\u8986\u76d6\u00a03200 ~ 8800 MT\/s\u3002\u9002\u7528\u5bf9\u8c61&#xff1a;\u670d\u52a1\u5668 \/ PC \/ \u8fb9\u7f18\u8ba1\u7b97 \/ \u9ad8\u7aef\u5d4c\u5165\u5f0f\u4e3b\u63a7&#xff08;Intel\u3001AMD\u3001\u98de\u817e\u3001\u6d77\u5149\u3001NXP\u3001\u745e\u8428\u3001<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[751,270,269,2122],"topic":[],"class_list":["post-112670","post","type-post","status-publish","format-standard","hentry","category-server","tag-arm","tag-270","tag-269","tag-2122"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.3 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.wsisp.com\/helps\/112670.html\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\" \/>\n<meta property=\"og:description\" content=\"\u9002\u7528\u8303\u56f4 \u672c\u6587\u9488\u5bf9\u00a0DDR5 SDRAM&#xff08;JESD79-5 \u7cfb\u5217&#xff09;\u7684\u786c\u4ef6\u7535\u8def\u8bbe\u8ba1&#xff0c;\u8986\u76d6\u9897\u7c92&#xff08;down \/ \u677f\u8f7d&#xff09;\u4e0e\u6a21\u7ec4&#xff08;UDIMM\u3001SODIMM\u3001RDIMM\u3001LRDIMM&#xff09;\u4e24\u7c7b\u843d\u5730\u5f62\u6001&#xff0c;\u901f\u7387\u8986\u76d6\u00a03200 ~ 8800 MT\/s\u3002\u9002\u7528\u5bf9\u8c61&#xff1a;\u670d\u52a1\u5668 \/ PC \/ \u8fb9\u7f18\u8ba1\u7b97 \/ \u9ad8\u7aef\u5d4c\u5165\u5f0f\u4e3b\u63a7&#xff08;Intel\u3001AMD\u3001\u98de\u817e\u3001\u6d77\u5149\u3001NXP\u3001\u745e\u8428\u3001\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.wsisp.com\/helps\/112670.html\" \/>\n<meta property=\"og:site_name\" content=\"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\" \/>\n<meta property=\"article:published_time\" content=\"2026-10-04T06:09:01+00:00\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"20 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/112670.html\",\"url\":\"https:\/\/www.wsisp.com\/helps\/112670.html\",\"name\":\"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\",\"isPartOf\":{\"@id\":\"https:\/\/www.wsisp.com\/helps\/#website\"},\"datePublished\":\"2026-10-04T06:09:01+00:00\",\"dateModified\":\"2026-10-04T06:09:01+00:00\",\"author\":{\"@id\":\"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41\"},\"breadcrumb\":{\"@id\":\"https:\/\/www.wsisp.com\/helps\/112670.html#breadcrumb\"},\"inLanguage\":\"zh-Hans\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.wsisp.com\/helps\/112670.html\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/112670.html#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"\u9996\u9875\",\"item\":\"https:\/\/www.wsisp.com\/helps\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/#website\",\"url\":\"https:\/\/www.wsisp.com\/helps\/\",\"name\":\"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\",\"description\":\"\u9999\u6e2f\u670d\u52a1\u5668_\u9999\u6e2f\u4e91\u670d\u52a1\u5668\u8d44\u8baf_\u670d\u52a1\u5668\u5e2e\u52a9\u6587\u6863_\u670d\u52a1\u5668\u6559\u7a0b\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.wsisp.com\/helps\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"zh-Hans\"},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41\",\"name\":\"admin\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"zh-Hans\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery\",\"contentUrl\":\"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery\",\"caption\":\"admin\"},\"sameAs\":[\"http:\/\/wp.wsisp.com\"],\"url\":\"https:\/\/www.wsisp.com\/helps\/author\/admin\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.wsisp.com\/helps\/112670.html","og_locale":"zh_CN","og_type":"article","og_title":"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","og_description":"\u9002\u7528\u8303\u56f4 \u672c\u6587\u9488\u5bf9\u00a0DDR5 SDRAM&#xff08;JESD79-5 \u7cfb\u5217&#xff09;\u7684\u786c\u4ef6\u7535\u8def\u8bbe\u8ba1&#xff0c;\u8986\u76d6\u9897\u7c92&#xff08;down \/ \u677f\u8f7d&#xff09;\u4e0e\u6a21\u7ec4&#xff08;UDIMM\u3001SODIMM\u3001RDIMM\u3001LRDIMM&#xff09;\u4e24\u7c7b\u843d\u5730\u5f62\u6001&#xff0c;\u901f\u7387\u8986\u76d6\u00a03200 ~ 8800 MT\/s\u3002\u9002\u7528\u5bf9\u8c61&#xff1a;\u670d\u52a1\u5668 \/ PC \/ \u8fb9\u7f18\u8ba1\u7b97 \/ \u9ad8\u7aef\u5d4c\u5165\u5f0f\u4e3b\u63a7&#xff08;Intel\u3001AMD\u3001\u98de\u817e\u3001\u6d77\u5149\u3001NXP\u3001\u745e\u8428\u3001","og_url":"https:\/\/www.wsisp.com\/helps\/112670.html","og_site_name":"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","article_published_time":"2026-10-04T06:09:01+00:00","author":"admin","twitter_card":"summary_large_image","twitter_misc":{"\u4f5c\u8005":"admin","\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4":"20 \u5206"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/www.wsisp.com\/helps\/112670.html","url":"https:\/\/www.wsisp.com\/helps\/112670.html","name":"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","isPartOf":{"@id":"https:\/\/www.wsisp.com\/helps\/#website"},"datePublished":"2026-10-04T06:09:01+00:00","dateModified":"2026-10-04T06:09:01+00:00","author":{"@id":"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41"},"breadcrumb":{"@id":"https:\/\/www.wsisp.com\/helps\/112670.html#breadcrumb"},"inLanguage":"zh-Hans","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.wsisp.com\/helps\/112670.html"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.wsisp.com\/helps\/112670.html#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"\u9996\u9875","item":"https:\/\/www.wsisp.com\/helps"},{"@type":"ListItem","position":2,"name":"\u82af\u53c2\u8c0b(39):DDR5 SDRAM \u7535\u8def\u8bbe\u8ba1\u6307\u5357"}]},{"@type":"WebSite","@id":"https:\/\/www.wsisp.com\/helps\/#website","url":"https:\/\/www.wsisp.com\/helps\/","name":"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","description":"\u9999\u6e2f\u670d\u52a1\u5668_\u9999\u6e2f\u4e91\u670d\u52a1\u5668\u8d44\u8baf_\u670d\u52a1\u5668\u5e2e\u52a9\u6587\u6863_\u670d\u52a1\u5668\u6559\u7a0b","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.wsisp.com\/helps\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"zh-Hans"},{"@type":"Person","@id":"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41","name":"admin","image":{"@type":"ImageObject","inLanguage":"zh-Hans","@id":"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/image\/","url":"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery","contentUrl":"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery","caption":"admin"},"sameAs":["http:\/\/wp.wsisp.com"],"url":"https:\/\/www.wsisp.com\/helps\/author\/admin"}]}},"_links":{"self":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/posts\/112670","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/comments?post=112670"}],"version-history":[{"count":0,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/posts\/112670\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/media?parent=112670"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/categories?post=112670"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/tags?post=112670"},{"taxonomy":"topic","embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/topic?post=112670"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}