{"id":106002,"date":"2026-09-16T13:51:19","date_gmt":"2026-09-16T05:51:19","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/106002.html"},"modified":"2026-09-16T13:51:19","modified_gmt":"2026-09-16T05:51:19","slug":"fpga-%e5%bc%80%e5%8f%91%e8%af%ad%e8%a8%80%e5%8f%8a%e7%a8%8b%e5%ba%8f%e5%ae%9e%e4%be%8b%e8%a7%a3%e6%9e%90%ef%bc%8c%e5%bc%80%e5%8f%91%e5%b7%a5%e5%85%b7%e7%ae%80%e8%bf%b0%ef%bc%8c%e5%bc%80%e5%8f%91","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/106002.html","title":{"rendered":"FPGA \u5f00\u53d1\u8bed\u8a00\u53ca\u7a0b\u5e8f\u5b9e\u4f8b\u89e3\u6790\uff0c\u5f00\u53d1\u5de5\u5177\u7b80\u8ff0\uff0c\u5f00\u53d1\u6280\u5de7\u4e0e\u4f18\u5316\u7b56\u7565\uff0c\u5b66\u4e60\u8d44\u6e90\u4e0e\u793e\u533a\u8bba\u575b"},"content":{"rendered":"<h4>\u4e00\u3001FPGA \u5f00\u53d1\u8bed\u8a00\u4f53\u7cfb<\/h4>\n<h5>1. \u786c\u4ef6\u63cf\u8ff0\u8bed\u8a00&#xff08;HDL&#xff09;<\/h5>\n<p>Verilog<\/p>\n<\/p>\n<ul>\n<li>\u6838\u5fc3\u7279\u6027&#xff1a;\n<ul>\n<li>\u652f\u6301\u884c\u4e3a\u7ea7\u3001RTL \u7ea7\u3001\u95e8\u7ea7\u5efa\u6a21&#xff0c;\u901a\u8fc7always &#064;(posedge clk)\u5b9e\u73b0\u540c\u6b65\u65f6\u5e8f\u903b\u8f91\u3002<\/li>\n<li>2025 \u5e74\u65b0\u589e\u7279\u6027&#xff1a;$urandom\u7cfb\u7edf\u51fd\u6570\u652f\u6301\u66f4\u5927\u8303\u56f4\u968f\u673a\u6570\u751f\u6210&#xff0c;$bitstoreal\u53ef\u76f4\u63a5\u5c06\u4f4d\u6d41\u8f6c\u6362\u4e3a\u6d6e\u70b9\u6570\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u5178\u578b\u4ee3\u7801\u793a\u4f8b&#xff1a;\n<p>verilog<\/p>\n<p> module counter #(parameter WIDTH&#061;8) (<br \/>\n  input clk,<br \/>\n  input rst_n,<br \/>\n  output reg [WIDTH-1:0] count<br \/>\n);<br \/>\n  always &#064;(posedge clk or negedge rst_n) begin<br \/>\n    if (!rst_n) count &lt;&#061; &#039;d0;<br \/>\n    else count &lt;&#061; count &#043; 1&#039;b1;<br \/>\n  end<br \/>\nend\n <\/li>\n<\/ul>\n<p>VHDL<\/p>\n<\/p>\n<ul>\n<li>\u4f18\u52bf\u9886\u57df&#xff1a;\n<ul>\n<li>\u5f3a\u7c7b\u578b\u7cfb\u7edf&#xff08;\u5982std_logic&#xff09;\u51cf\u5c11\u7c7b\u578b\u9519\u8bef&#xff0c;entity\/architecture\u7ed3\u6784\u9002\u5408\u5927\u578b\u9879\u76ee\u3002<\/li>\n<li>2025 \u5e74\u589e\u5f3a\u529f\u80fd&#xff1a;\u652f\u6301generate\u8bed\u53e5\u52a8\u6001\u751f\u6210\u591a\u5b9e\u4f8b\u6a21\u5757&#xff0c;package\u53ef\u5b9a\u4e49\u5168\u5c40\u5e38\u91cf\u4e0e\u51fd\u6570\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u5178\u578b\u4ee3\u7801\u793a\u4f8b&#xff1a;\n<p>vhdl<\/p>\n<p> library IEEE;<br \/>\nuse IEEE.STD_LOGIC_1164.ALL;<\/p>\n<p>entity counter is<br \/>\n  generic (WIDTH : natural :&#061; 8);<br \/>\n  port (<br \/>\n    clk  : in  std_logic;<br \/>\n    rst_n: in  std_logic;<br \/>\n    count: out std_logic_vector(WIDTH-1 downto 0)<br \/>\n  );<br \/>\nend counter;<\/p>\n<p>architecture Behavioral of counter is<br \/>\n  signal cnt_reg: std_logic_vector(WIDTH-1 downto 0) :&#061; (others &#061;&gt; &#039;0&#039;);<br \/>\nbegin<br \/>\n  process(clk, rst_n)<br \/>\n  begin<br \/>\n    if rst_n &#061; &#039;0&#039; then<br \/>\n      cnt_reg &lt;&#061; (others &#061;&gt; &#039;0&#039;);<br \/>\n    elsif rising_edge(clk) then<br \/>\n      cnt_reg &lt;&#061; std_logic_vector(unsigned(cnt_reg) &#043; 1);<br \/>\n    end if;<br \/>\n  end process;<br \/>\n  count &lt;&#061; cnt_reg;<br \/>\nend architecture;\n <\/li>\n<\/ul>\n<p>SystemVerilog<\/p>\n<\/p>\n<ul>\n<li>\u9a8c\u8bc1\u6269\u5c55&#xff1a;\n<ul>\n<li>\u65ad\u8a00&#xff08;assert property&#xff09;\u53ef\u5b9e\u65f6\u76d1\u6d4b\u4fe1\u53f7\u884c\u4e3a&#xff0c;UVM&#xff08;Universal Verification Methodology&#xff09;\u652f\u6301\u590d\u6742\u9a8c\u8bc1\u73af\u5883\u3002<\/li>\n<li>2025 \u5e74\u65b0\u589e&#xff1a;virtual interface\u652f\u6301\u591a\u534f\u8bae\u63a5\u53e3\u590d\u7528&#xff0c;covergroup\u53ef\u81ea\u52a8\u751f\u6210\u8986\u76d6\u7387\u62a5\u544a\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u5178\u578b\u4ee3\u7801\u793a\u4f8b&#xff1a;\n<p>systemverilog<\/p>\n<p> module uart_tx (<br \/>\n  input clk,<br \/>\n  input rst_n,<br \/>\n  input [7:0] data,<br \/>\n  input valid,<br \/>\n  output reg tx<br \/>\n);<\/p>\n<p>\/\/ \u72b6\u6001\u673a\u5b9a\u4e49<br \/>\ntypedef enum logic [1:0] {IDLE, START, DATA, STOP} state_t;<br \/>\nstate_t state, next_state;<\/p>\n<p>\/\/ \u65ad\u8a00&#xff1a;\u7981\u6b62\u5728IDLE\u72b6\u6001\u53d1\u9001\u6570\u636e<br \/>\nassert property (&#064;(posedge clk) disable iff (!rst_n)<br \/>\n  (state &#061;&#061; IDLE) |-&gt; !valid);<\/p>\n<p>\/\/ \u72b6\u6001\u8f6c\u79fb\u903b\u8f91<br \/>\nalways &#064;(posedge clk or negedge rst_n) begin<br \/>\n  if (!rst_n) state &lt;&#061; IDLE;<br \/>\n  else state &lt;&#061; next_state;<br \/>\nend<\/p>\n<p>\/\/ \u6570\u636e\u53d1\u9001\u903b\u8f91<br \/>\nalways &#064;* begin<br \/>\n  case(state)<br \/>\n    IDLE: next_state &#061; valid ? START : IDLE;<br \/>\n    START: next_state &#061; DATA;<br \/>\n    DATA: next_state &#061; (tx_cnt &#061;&#061; 7) ? STOP : DATA;<br \/>\n    STOP: next_state &#061; IDLE;<br \/>\n  endcase<br \/>\nend<br \/>\nendmodule\n <\/li>\n<\/ul>\n<h5>2. \u9ad8\u7ea7\u7efc\u5408&#xff08;HLS&#xff09;\u8bed\u8a00<\/h5>\n<p>Vivado HLS&#xff08;Xilinx&#xff09;<\/p>\n<\/p>\n<ul>\n<li>C\/C&#043;&#043; \u4f18\u5316&#xff1a;\n<ul>\n<li>#pragma HLS pipeline\u6307\u4ee4\u81ea\u52a8\u63d2\u5165\u6d41\u6c34\u7ebf&#xff0c;#pragma HLS dataflow\u5b9e\u73b0\u6570\u636e\u6d41\u5e76\u884c\u3002<\/li>\n<li>2025 \u5e74\u65b0\u589e&#xff1a;\u652f\u6301auto_pipeline\u81ea\u52a8\u4f18\u5316\u5faa\u73af\u7ed3\u6784&#xff0c;resource_sharing\u51cf\u5c11\u4e58\u6cd5\u5668\u7b49\u8d44\u6e90\u5360\u7528\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u5178\u578b\u4ee3\u7801\u793a\u4f8b&#xff1a;\n<p>c<\/p>\n<p> void matrix_multiply(<br \/>\n  float A[M][N],<br \/>\n  float B[N][P],<br \/>\n  float C[M][P]<br \/>\n) {<br \/>\n  #pragma HLS INTERFACE m_axi port&#061;A offset&#061;slave bundle&#061;AXI_A<br \/>\n  #pragma HLS INTERFACE m_axi port&#061;B offset&#061;slave bundle&#061;AXI_B<br \/>\n  #pragma HLS INTERFACE m_axi port&#061;C offset&#061;slave bundle&#061;AXI_C<\/p>\n<p>  for (int i &#061; 0; i &lt; M; i&#043;&#043;) {<br \/>\n    for (int j &#061; 0; j &lt; P; j&#043;&#043;) {<br \/>\n      float sum &#061; 0;<br \/>\n      for (int k &#061; 0; k &lt; N; k&#043;&#043;) {<br \/>\n        #pragma HLS UNROLL factor&#061;4  \/\/ \u5c55\u5f00\u5faa\u73af4\u500d<br \/>\n        sum &#043;&#061; A[i][k] * B[k][j];<br \/>\n      }<br \/>\n      C[i][j] &#061; sum;<br \/>\n    }<br \/>\n  }<br \/>\n}\n <\/li>\n<\/ul>\n<p>Intel HLS&#xff08;Intel&#xff09;<\/p>\n<\/p>\n<ul>\n<li>OpenCL \u652f\u6301&#xff1a;\n<ul>\n<li>\u901a\u8fc7#pragma OPENCL kernel\u5b9a\u4e49\u5185\u6838\u51fd\u6570&#xff0c;#pragma OPENCL access_pattern\u4f18\u5316\u5185\u5b58\u8bbf\u95ee\u3002<\/li>\n<li>2025 \u5e74\u589e\u5f3a&#xff1a;\u652f\u6301pipeline\u6307\u4ee4\u5d4c\u5957&#xff0c;array_partition\u53ef\u52a8\u6001\u5206\u5272\u6570\u7ec4\u63d0\u5347\u5e26\u5bbd\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u5178\u578b\u4ee3\u7801\u793a\u4f8b&#xff1a;\n<p>c<\/p>\n<p> __kernel void vector_add(<br \/>\n  __global float *A,<br \/>\n  __global float *B,<br \/>\n  __global float *C,<br \/>\n  const int size<br \/>\n) {<br \/>\n  int i &#061; get_global_id(0);<br \/>\n  if (i &lt; size) {<br \/>\n    C[i] &#061; A[i] &#043; B[i];<br \/>\n  }<br \/>\n}\n <\/li>\n<\/ul>\n<h4>\u4e8c\u3001\u5f00\u53d1\u5de5\u5177\u94fe\u4e0e\u7a0b\u5e8f\u5b9e\u4f8b<\/h4>\n<h5>1. \u4e3b\u6d41\u5de5\u5177\u94fe<\/h5>\n<p>Xilinx Vivado<\/p>\n<\/p>\n<ul>\n<li>\u6838\u5fc3\u6d41\u7a0b&#xff1a;\n<li>RTL \u8bbe\u8ba1&#xff1a;\u7f16\u5199 Verilog\/VHDL \u4ee3\u7801&#xff0c;\u4f7f\u7528 IP Integrator \u642d\u5efa\u7cfb\u7edf\u3002<\/li>\n<li>\u7efc\u5408\u4f18\u5316&#xff1a;\u901a\u8fc7opt_design\u547d\u4ee4\u8c03\u6574\u65f6\u5e8f\u7ea6\u675f&#xff0c;report_timing_summary\u5206\u6790\u5173\u952e\u8def\u5f84\u3002<\/li>\n<li>\u4eff\u771f\u9a8c\u8bc1&#xff1a;\u4f7f\u7528 Vivado Simulator \u8fd0\u884c Testbench&#xff0c;\u901a\u8fc7add_wave\u547d\u4ee4\u6293\u53d6\u4fe1\u53f7\u6ce2\u5f62\u3002<\/li>\n<li>\u8c03\u8bd5\u5de5\u5177&#xff1a;ChipScope Pro \u901a\u8fc7 ILA \u6838\u5b9e\u65f6\u76d1\u63a7\u5185\u90e8\u4fe1\u53f7&#xff0c;debug_core\u53ef\u52a8\u6001\u4fee\u6539\u5bc4\u5b58\u5668\u503c\u3002<\/li>\n<\/li>\n<\/ul>\n<p>Intel Quartus Prime<\/p>\n<\/p>\n<ul>\n<li>\u65b0\u7279\u6027&#xff08;24.3 \u7248\u672c&#xff09;&#xff1a;\n<ul>\n<li>\u652f\u6301 Agilex 7 FPGA \u7684 CXL 2.0 \u786c\u6838 IP&#xff0c;\u53ef\u5b9e\u73b0\u5168\u5c40\u6301\u4e45\u51b2\u6d17\u548c RAS \u529f\u80fd\u3002<\/li>\n<li>Nios V \u5904\u7406\u5668\u589e\u5f3a\u5206\u652f\u9884\u6d4b\u4e0e\u9501\u6b65\u652f\u6301&#xff0c;Coremark \u57fa\u51c6\u6027\u80fd\u63d0\u5347 30%\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>\u5f00\u6e90\u5de5\u5177\u94fe&#xff08;Yosys&#043;NextPNR&#043;Icarus Verilog&#xff09;<\/p>\n<\/p>\n<ul>\n<li>\u5178\u578b\u6d41\u7a0b&#xff1a;\n<li>\u7efc\u5408&#xff1a;yosys -p &#034;synth_ice40 -json design.json&#034;\u751f\u6210\u7f51\u8868\u3002<\/li>\n<li>\u5e03\u5c40\u5e03\u7ebf&#xff1a;nextpnr-ice40 &#8211;json design.json &#8211;asc design.asc\u6620\u5c04\u5230\u786c\u4ef6\u8d44\u6e90\u3002<\/li>\n<li>\u4eff\u771f&#xff1a;iverilog -o sim design.v testbench.v &amp;&amp; vvp sim\u8fd0\u884c\u6d4b\u8bd5\u3002<\/li>\n<ul>\n<li>\u4f18\u52bf&#xff1a;\u5b8c\u5168\u514d\u8d39&#xff0c;\u652f\u6301 Lattice iCE40 \u7b49\u4f4e\u6210\u672c FPGA\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h5>2. \u7a0b\u5e8f\u5b9e\u4f8b\u6559\u7a0b<\/h5>\n<p>\u5b9e\u4f8b 1&#xff1a;UART \u901a\u4fe1\u6a21\u5757<\/p>\n<\/p>\n<ul>\n<li>\u529f\u80fd&#xff1a;\u5b9e\u73b0 115200 \u6ce2\u7279\u7387\u5f02\u6b65\u4e32\u53e3\u6536\u53d1\u3002<\/li>\n<li>Verilog \u4ee3\u7801&#xff1a;\n<p>verilog<\/p>\n<p> module uart (<br \/>\n  input clk,<br \/>\n  input rst_n,<br \/>\n  input rx,<br \/>\n  output reg tx,<br \/>\n  output reg [7:0] rx_data,<br \/>\n  output reg rx_valid<br \/>\n);<\/p>\n<p>parameter BAUD_RATE &#061; 115200;<br \/>\nlocalparam CLK_FREQ &#061; 100_000_000;<br \/>\nlocalparam DIVISOR &#061; CLK_FREQ \/ BAUD_RATE;<\/p>\n<p>\/\/ \u6ce2\u7279\u7387\u8ba1\u6570\u5668<br \/>\nreg [15:0] baud_cnt;<br \/>\nalways &#064;(posedge clk or negedge rst_n) begin<br \/>\n  if (!rst_n) baud_cnt &lt;&#061; 0;<br \/>\n  else if (baud_cnt &#061;&#061; DIVISOR\/2 &#8211; 1) baud_cnt &lt;&#061; 0;<br \/>\n  else baud_cnt &lt;&#061; baud_cnt &#043; 1;<br \/>\nend<\/p>\n<p>\/\/ \u63a5\u6536\u72b6\u6001\u673a<br \/>\nenum logic [2:0] {IDLE, START, DATA, STOP} rx_state;<br \/>\nalways &#064;(posedge clk or negedge rst_n) begin<br \/>\n  if (!rst_n) begin<br \/>\n    rx_state &lt;&#061; IDLE;<br \/>\n    rx_data &lt;&#061; 0;<br \/>\n    rx_valid &lt;&#061; 0;<br \/>\n  end else begin<br \/>\n    case(rx_state)<br \/>\n      IDLE: if (!rx) rx_state &lt;&#061; START;<br \/>\n      START: if (baud_cnt &#061;&#061; DIVISOR\/2 &#8211; 1) rx_state &lt;&#061; DATA;<br \/>\n      DATA: if (bit_cnt &#061;&#061; 7 &amp;&amp; baud_cnt &#061;&#061; DIVISOR\/2 &#8211; 1) rx_state &lt;&#061; STOP;<br \/>\n      STOP: if (baud_cnt &#061;&#061; DIVISOR\/2 &#8211; 1) begin<br \/>\n        rx_state &lt;&#061; IDLE;<br \/>\n        rx_valid &lt;&#061; 1;<br \/>\n      end<br \/>\n    endcase<br \/>\n  end<br \/>\nend<br \/>\nendmodule\n <\/li>\n<\/ul>\n<p>\u5b9e\u4f8b 2&#xff1a;AI \u52a0\u901f\u6a21\u5757&#xff08;Vitis AI&#xff09;<\/p>\n<\/p>\n<ul>\n<li>\u529f\u80fd&#xff1a;\u5728 Xilinx Alveo \u5361\u4e0a\u90e8\u7f72 ResNet-50 \u56fe\u50cf\u5206\u7c7b\u6a21\u578b\u3002<\/li>\n<li>\u6d41\u7a0b&#xff1a;\n<li>\u6a21\u578b\u91cf\u5316&#xff1a;vai_q_tensorflow &#8211;input_frozen_graph resnet50.pb &#8211;output_dir quantized\u3002<\/li>\n<li>\u7f16\u8bd1\u90e8\u7f72&#xff1a;v&#043;&#043; -t hw &#8211;platform xilinx_u250_xdma_201830_2 &#8211;target sw_emu resnet50.xo\u3002<\/li>\n<li>\u6027\u80fd\u4f18\u5316&#xff1a;\u901a\u8fc7&#8211;config&#061;resnet50_config.toml\u8c03\u6574\u5185\u5b58\u5e26\u5bbd\u5206\u914d\u3002<\/li>\n<\/li>\n<\/ul>\n<p>\u5b9e\u4f8b 3&#xff1a;CXL \u534f\u8bae\u63a5\u53e3&#xff08;Intel Agilex&#xff09;<\/p>\n<\/p>\n<ul>\n<li>\u529f\u80fd&#xff1a;\u4f7f\u7528 Intel CXL IP \u6838\u5b9e\u73b0 FPGA \u4e0e CPU \u7684\u7f13\u5b58\u4e00\u81f4\u6027\u4e92\u8054\u3002<\/li>\n<li>\u5173\u952e\u914d\u7f6e&#xff1a;\n<p>tcl<\/p>\n<p> # \u542f\u7528CXL.cache\u534f\u8bae<br \/>\nset_property -dict [list \\\\<br \/>\n  CONFIG.Protocol {CXL_CACHE} \\\\<br \/>\n  CONFIG.MaxReadDataSize {64} \\\\<br \/>\n  CONFIG.MaxWriteDataSize {64} \\\\<br \/>\n] [get_ips cxl_ip]\n <\/li>\n<\/ul>\n<h4>\u4e09\u3001\u5f00\u53d1\u6280\u5de7\u4e0e\u4f18\u5316\u7b56\u7565<\/h4>\n<h5>1. \u65f6\u5e8f\u4f18\u5316<\/h5>\n<ul>\n<li>\u5173\u952e\u8def\u5f84\u5206\u6790&#xff1a;\n<ul>\n<li>Vivado&#xff1a;report_timing_summary -max_paths 10\u67e5\u770b\u6700\u957f\u8def\u5f84\u3002<\/li>\n<li>Quartus&#xff1a;Timing Analyzer\u5de5\u5177\u6807\u8bb0 Hold Time \u8fdd\u4f8b\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u4f18\u5316\u65b9\u6cd5&#xff1a;\n<ul>\n<li>\u5bc4\u5b58\u5668\u91cd\u5b9a\u65f6&#xff08;Register Retiming&#xff09;&#xff1a;opt_design -retime\u81ea\u52a8\u8c03\u6574\u5bc4\u5b58\u5668\u4f4d\u7f6e\u3002<\/li>\n<li>\u6d41\u6c34\u7ebf\u5206\u5272&#xff1a;\u5728\u7ec4\u5408\u903b\u8f91\u4e2d\u63d2\u5165\u5bc4\u5b58\u5668&#xff0c;\u964d\u4f4e\u5355\u7ea7\u5ef6\u8fdf\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h5>2. \u4f4e\u529f\u8017\u8bbe\u8ba1<\/h5>\n<ul>\n<li>\u52a8\u6001\u529f\u8017&#xff1a;\n<ul>\n<li>\u95e8\u63a7\u65f6\u949f&#xff08;Clock Gating&#xff09;&#xff1a;clk_gating_cell\u81ea\u52a8\u63d2\u5165\u4f7f\u80fd\u4fe1\u53f7\u3002<\/li>\n<li>\u6570\u636e\u901a\u8def\u4f18\u5316&#xff1a;\u907f\u514d\u9ad8\u9891\u4fe1\u53f7\u7ffb\u8f6c&#xff0c;\u5982\u4f7f\u7528assign\u66ff\u4ee3always\u5757\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u9759\u6001\u529f\u8017&#xff1a;\n<ul>\n<li>\u7535\u6e90\u57df\u5212\u5206&#xff1a;create_power_domain\u5b9a\u4e49\u72ec\u7acb\u4f9b\u7535\u533a\u57df\u3002<\/li>\n<li>\u7761\u7720\u6a21\u5f0f&#xff1a;\u901a\u8fc7set_sleep_ports\u914d\u7f6e\u6a21\u5757\u4f11\u7720\u72b6\u6001\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h5>3. \u9ad8\u901f\u63a5\u53e3\u8bbe\u8ba1<\/h5>\n<ul>\n<li>DDR4 \u63a7\u5236\u5668&#xff1a;\n<ul>\n<li>Xilinx MIG IP&#xff1a;\u914d\u7f6ephy_init_clk\u9891\u7387\u4e3a 1666 MHz&#xff0c;ddr_phy\u9009\u62e9 HBM2E \u7c7b\u578b\u3002<\/li>\n<li>Intel Qsys&#xff1a;\u8bbe\u7f6eburst_length\u4e3a 8&#xff0c;read_latency\u4e3a 14 cycles\u3002<\/li>\n<\/ul>\n<\/li>\n<li>PCIe Gen4&#xff1a;\n<ul>\n<li>\u914d\u7f6emax_payload_size\u4e3a 4096 \u5b57\u8282&#xff0c;max_read_request\u4e3a 4096 \u5b57\u8282\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h4>\u56db\u3001\u5b66\u4e60\u8d44\u6e90\u4e0e\u793e\u533a<\/h4>\n<h5>1. \u5b98\u65b9\u6587\u6863<\/h5>\n<ul>\n<li>Xilinx&#xff1a;\n<ul>\n<li>Vitis AI User Guide&#xff1a;\u6db5\u76d6\u6a21\u578b\u91cf\u5316\u4e0e\u90e8\u7f72\u6d41\u7a0b\u3002<\/li>\n<li>Vivado Design Suite Tutorial&#xff1a;\u4ece\u57fa\u7840\u5230\u9ad8\u7ea7\u7684\u8bbe\u8ba1\u6307\u5357\u3002<\/li>\n<\/ul>\n<\/li>\n<li>Intel&#xff1a;\n<ul>\n<li>Quartus Prime Handbook&#xff1a;\u5305\u542b CXL \u534f\u8bae\u914d\u7f6e\u5b9e\u4f8b\u3002<\/li>\n<li>Agilex FPGA IP User Guide&#xff1a;\u8be6\u7ec6\u8bf4\u660e CXL \u63a5\u53e3\u5f00\u53d1\u6b65\u9aa4\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h5>2. \u5f00\u6e90\u9879\u76ee<\/h5>\n<ul>\n<li>RISC-V \u8f6f\u6838&#xff1a;\n<ul>\n<li>PicoRV32&#xff1a;\u6781\u7b80 32 \u4f4d\u5904\u7406\u5668&#xff0c;\u652f\u6301\u54c8\u4f5b\u67b6\u6784\u4e0e\u538b\u7f29\u6307\u4ee4\u96c6\u3002<\/li>\n<li>VexRiscv&#xff1a;5 \u7ea7\u6d41\u6c34\u7ebf\u8bbe\u8ba1&#xff0c;\u652f\u6301 Linux \u7cfb\u7edf\u3002<\/li>\n<\/ul>\n<\/li>\n<li>\u901a\u4fe1\u534f\u8bae&#xff1a;\n<ul>\n<li>Verilog-UART&#xff1a;\u5e26 FIFO \u7f13\u51b2\u7684\u901a\u7528\u5f02\u6b65\u6536\u53d1\u5668\u3002<\/li>\n<li>VHDL-I2C&#xff1a;\u652f\u6301\u591a\u4e3b\u8bbe\u5907\u7684\u603b\u7ebf\u63a7\u5236\u5668\u3002<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h5>3. \u793e\u533a\u4e0e\u8bba\u575b<\/h5>\n<ul>\n<li>Reddit&#xff1a;r\/FPGA&#xff1a;\u8ba8\u8bba\u6280\u672f\u95ee\u9898\u4e0e\u9879\u76ee\u7ecf\u9a8c\u3002<\/li>\n<li>GitHub&#xff1a;\u641c\u7d22 \u201cFPGA projects\u201d \u83b7\u53d6\u5f00\u6e90\u4ee3\u7801&#xff0c;\u5982 HDMI \u63a7\u5236\u5668\u3001FFT \u52a0\u901f\u5668\u3002<\/li>\n<li>CSDN&#xff1a;FPGA \u5f00\u53d1\u8005\u8bba\u575b&#xff1a;\u4e2d\u6587\u6280\u672f\u4ea4\u6d41\u5e73\u53f0\u3002<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>\u4e00\u3001FPGA \u5f00\u53d1\u8bed\u8a00\u4f53\u7cfb<br \/>\n1. \u786c\u4ef6\u63cf\u8ff0\u8bed\u8a00&#xff08;HDL&#xff09;<br \/>\nVerilog \u6838\u5fc3\u7279\u6027&#xff1a; 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