{"id":104546,"date":"2026-09-12T17:41:38","date_gmt":"2026-09-12T09:41:38","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/104546.html"},"modified":"2026-09-12T17:41:38","modified_gmt":"2026-09-12T09:41:38","slug":"verilog%e5%ae%9e%e7%8e%b0iic%ef%bc%88%e9%9b%86%e6%88%90%e7%94%b5%e8%b7%af%e6%80%bb%e7%ba%bf%ef%bc%89%e5%8d%8f%e8%ae%ae","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/104546.html","title":{"rendered":"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae"},"content":{"rendered":"<h2>IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf<\/h2>\n<\/p>\n<h4>\u6587\u7ae0\u76ee\u5f55<\/h4>\n<ul>\n<li>IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf<\/li>\n<li>\n<ul>\n<li>\u4e00\u3001IIC \u603b\u7ebf\u6982\u8ff0<\/li>\n<li>\u4e8c\u3001\u7269\u7406\u5c42<\/li>\n<li>\u4e09\u3001\u8bbe\u5907\u5bfb\u5740&#xff1a;7&#043;1 \u5b57\u8282\u683c\u5f0f<\/li>\n<li>\u56db\u3001\u8bbe\u5907\u89d2\u8272\u4e0e\u529f\u80fd<\/li>\n<li>\n<ul>\n<li>\u4e3b\u8bbe\u5907<\/li>\n<li>\u4ece\u8bbe\u5907<\/li>\n<\/ul>\n<\/li>\n<li>\u4e94\u3001\u901a\u4fe1\u901f\u7387<\/li>\n<li>\u516d\u3001\u534f\u8bae\u5c42<\/li>\n<li>\n<ul>\n<li>6.1 \u8d77\u59cb\u4fe1\u53f7 &amp; \u505c\u6b62\u4fe1\u53f7<\/li>\n<li>6.2 \u6570\u636e\u4f4d\u4f20\u8f93\u89c4\u5219<\/li>\n<li>6.3 ACK \u5e94\u7b54\u4fe1\u53f7<\/li>\n<li>6.4 \u4e09\u79cd\u5de5\u4f5c\u6a21\u5f0f<\/li>\n<li>6.5 \u591a\u4e3b\u673a\u4e0e\u603b\u7ebf\u4ef2\u88c1<\/li>\n<\/ul>\n<\/li>\n<li>\u4e03\u3001IIC \u6838\u5fc3\u5c0f\u7ed3<\/li>\n<li>\u516b\u3001Verilog \u5b9e\u73b0 IIC \u534f\u8bae<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>\u6458\u8981&#xff1a;IIC&#xff08;Inter\u2011Integrated Circuit&#xff09;\u662f\u4e00\u79cd\u4e24\u7ebf\u5f0f\u53cc\u5411\u4e32\u884c\u603b\u7ebf&#xff0c;\u4ec5\u9700 SDA&#xff08;\u6570\u636e\u7ebf&#xff09;\u4e0e SCL&#xff08;\u65f6\u949f\u7ebf&#xff09;\u4e24\u6839\u4fe1\u53f7\u7ebf&#xff0c;\u914d\u5408\u5916\u90e8\u4e0a\u62c9\u7535\u963b\u5373\u53ef\u5b9e\u73b0\u4e3b\u4ece\u8bbe\u5907\u95f4\u7684\u677f\u5185\u77ed\u8ddd\u79bb\u901a\u4fe1\u3002\u672c\u6587\u4ece\u7269\u7406\u5c42\u3001\u8bbe\u5907\u5bfb\u5740&#xff08;7 \u4f4d\u5730\u5740 &#043; 1 \u4f4d\u8bfb\u5199\u4f4d&#xff09;\u3001\u8bbe\u5907\u89d2\u8272\u3001\u901a\u4fe1\u901f\u7387\u4e0e\u534f\u8bae\u5c42&#xff08;\u8d77\u59cb\/\u505c\u6b62\u4fe1\u53f7\u3001\u6570\u636e\u4f4d\u4f20\u8f93\u3001ACK \u5e94\u7b54\u3001\u591a\u4e3b\u673a\u4ef2\u88c1&#xff09;\u9010\u5c42\u8bb2\u89e3 IIC \u6838\u5fc3\u673a\u5236&#xff0c;\u5e76\u7ed9\u51fa\u57fa\u4e8e\u4e09\u6bb5\u5f0f\u72b6\u6001\u673a\u7684 Verilog \u5b8c\u6574\u5b9e\u73b0\u4e0e\u4eff\u771f\u4ee3\u7801&#xff0c;\u5e2e\u52a9\u8bfb\u8005\u4ece\u539f\u7406\u5230\u4ee3\u7801\u5168\u9762\u638c\u63e1 IIC \u534f\u8bae\u3002<\/p>\n<h3>\u4e00\u3001IIC \u603b\u7ebf\u6982\u8ff0<\/h3>\n<p>IIC&#xff08;Inter\u2011Integrated Circuit&#xff0c;\u96c6\u6210\u7535\u8def\u603b\u7ebf&#xff09;&#xff0c;\u4e3b\u8981\u7528\u4e8e\u8fde\u63a5\u5fae\u63a7\u5236\u5668\u4e0e\u5404\u7c7b\u5916\u56f4\u5668\u4ef6&#xff0c;\u5b9e\u73b0\u82af\u7247\u4e0e\u82af\u7247\u4e4b\u95f4\u7684\u901a\u4fe1\u3002 \u53ef\u4ee5\u5728 CPU \u4e0e\u88ab\u63a7 IC\u3001IC \u4e0e IC \u4e4b\u95f4\u5b8c\u6210\u53cc\u5411\u6570\u636e\u4f20\u8f93&#xff0c;\u9ad8\u901f IIC \u603b\u7ebf\u901f\u7387\u53ef\u8fbe 400kbps \u4ee5\u4e0a\u3002<\/p>\n<p>\u9002\u7528\u573a\u666f&#xff1a;\u4e3b\u63a7\u5236\u5668\u4e0e\u4ece\u5668\u4ef6\u7684\u4e3b\u4ece\u901a\u4fe1&#xff0c;\u9002\u5408\u5c0f\u6570\u636e\u91cf\u3001\u77ed\u8ddd\u79bb\u677f\u5185\u901a\u4fe1&#xff1b; \u7ea6\u675f\u7279\u6027&#xff1a;\u4efb\u610f\u65f6\u523b\u603b\u7ebf\u53ea\u5141\u8bb8\u5b58\u5728\u4e00\u4e2a\u6709\u6548\u4e3b\u673a&#xff1b;\u4ece\u673a\u4e0e\u4ece\u673a\u4e4b\u95f4\u4e0d\u80fd\u76f4\u63a5\u4ea4\u6362\u6570\u636e&#xff0c;\u5fc5\u987b\u7ecf\u8fc7\u4e3b\u673a\u8f6c\u53d1\u3002<\/p>\n<h3>\u4e8c\u3001\u7269\u7406\u5c42<\/h3>\n<p>IIC \u662f\u4e24\u7ebf\u5f0f\u53cc\u5411\u4e32\u884c\u603b\u7ebf&#xff0c;\u53ea\u9700\u8981\u4e24\u6839\u4fe1\u53f7\u7ebf&#xff1a;<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094130-6aa51e4a2f8dc.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n<li>SDA&#xff08;Serial Data&#xff09;&#xff1a;\u4e32\u884c\u6570\u636e\u7ebf&#xff0c;\u8d1f\u8d23\u4f20\u8f93\u5b9e\u9645\u6536\u53d1\u7684\u6570\u636e\u3002<\/li>\n<li>SCL&#xff08;Serial Clock Line&#xff09;&#xff1a;\u4e32\u884c\u65f6\u949f\u7ebf&#xff0c;\u7531\u4e3b\u673a\u4ea7\u751f\u65f6\u949f&#xff0c;\u63a7\u5236\u6570\u636e\u6536\u53d1\u65f6\u5e8f\u3002<\/li>\n<p>\u603b\u7ebf\u786c\u4ef6\u8981\u6c42&#xff1a;SDA\u3001SCL \u4e24\u6839\u4fe1\u53f7\u7ebf\u5fc5\u987b\u5916\u63a5\u4e0a\u62c9\u7535\u963b&#xff0c;\u963b\u503c\u6839\u636e\u901a\u4fe1\u901f\u7387\u3001\u603b\u7ebf\u5bb9\u6027\u8d1f\u8f7d\u9009\u62e9&#xff0c;\u5e38\u7528\u53d6\u503c3.3k\u03a9 ~ 10k\u03a9\u3002\u603b\u7ebf\u7a7a\u95f2\u65f6\u4e24\u6839\u7ebf\u88ab\u4e0a\u62c9\u7535\u963b\u62c9\u4e3a\u9ad8\u7535\u5e73&#xff1b;\u5668\u4ef6\u5185\u90e8\u4e3a\u5f00\u6f0f\u8f93\u51fa\u7ed3\u6784&#xff0c;\u4f9d\u9760\u9ad8\u963b\u6001\u5b9e\u73b0\u7ebf\u4e0e\u903b\u8f91\u3002<\/p>\n<p>\u603b\u7ebf\u4e0a\u6302\u8f7d\u7684\u6bcf\u4e00\u4e2a IIC \u4ece\u8bbe\u5907&#xff0c;\u90fd\u62e5\u6709\u552f\u4e00\u8bbe\u5907\u5730\u5740&#xff0c;\u4e3b\u673a\u4f9d\u9760\u5730\u5740\u533a\u5206\u4e0d\u540c\u4ece\u673a&#xff0c;\u4fdd\u8bc1\u8bbf\u95ee\u51c6\u786e\u3002<\/p>\n<h3>\u4e09\u3001\u8bbe\u5907\u5bfb\u5740&#xff1a;7&#043;1 \u5b57\u8282\u683c\u5f0f<\/h3>\n<p>IIC \u8bfb\u5199\u5bfb\u5740\u5b57\u8282\u4e00\u5171 8bit&#xff1a;7bit\u4ece\u673a\u8bbe\u5907\u5730\u5740 &#043; 1bit\u8bfb\u5199\u65b9\u5411\u4f4d<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094131-6aa51e4b720df.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n<ul>\n<li>bit7~bit1&#xff1a;7 \u4f4d\u4ece\u673a\u8bbe\u5907\u5730\u5740&#xff0c;\u7528\u6765\u5bfb\u627e\u603b\u7ebf\u4e0a\u76ee\u6807\u4ece\u673a<\/li>\n<li>bit0&#xff1a;\u8bfb\u5199\u65b9\u5411\u4f4d\n<ul>\n<li>0&#xff1a;\u4e3b\u673a\u5411\u4ece\u673a\u5199\u6570\u636e<\/li>\n<li>1&#xff1a;\u4e3b\u673a\u4ece\u4ece\u673a\u8bfb\u6570\u636e<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>\u6ce8\u610f&#xff1a;IIC \u5668\u4ef6\u5185\u90e8 IO \u4e3a\u5f00\u6f0f\u7ed3\u6784&#xff0c;\u603b\u7ebf\u7a7a\u95f2\u65f6 SDA\u3001SCL \u5904\u4e8e\u9ad8\u963b\u6001&#xff0c;\u4f9d\u9760\u5916\u90e8\u4e0a\u62c9\u7535\u963b\u62c9\u9ad8\u7535\u5e73\u3002<\/p>\n<h3>\u56db\u3001\u8bbe\u5907\u89d2\u8272\u4e0e\u529f\u80fd<\/h3>\n<h4>\u4e3b\u8bbe\u5907<\/h4>\n<li>\u4ea7\u751f SCL \u65f6\u949f\u4fe1\u53f7<\/li>\n<li>\u4ea7\u751f\u8d77\u59cb\u4fe1\u53f7\u3001\u505c\u6b62\u4fe1\u53f7<\/li>\n<li>\u53d1\u8d77\u603b\u7ebf\u8bbf\u95ee\u3001\u53d1\u9001\u5bfb\u5740\u5b57\u8282<\/li>\n<h4>\u4ece\u8bbe\u5907<\/h4>\n<li>\u68c0\u6d4b\u603b\u7ebf\u4e0a\u7684\u8bbe\u5907\u5730\u5740&#xff0c;\u5339\u914d\u81ea\u8eab\u5730\u5740\u540e\u54cd\u5e94<\/li>\n<li>\u68c0\u6d4b\u8d77\u59cb\u4f4d\u3001\u505c\u6b62\u4f4d&#xff0c;\u914d\u5408\u4e3b\u673a\u5b8c\u6210\u5e94\u7b54\u4e0e\u6570\u636e\u6536\u53d1<\/li>\n<p>IIC \u652f\u6301\u591a\u4e3b\u673a\u6a21\u5f0f&#xff08;multimastering&#xff09;&#xff0c;\u4e00\u6761\u603b\u7ebf\u53ef\u4ee5\u6302\u591a\u4e2a\u4e3b\u673a&#xff1b; \u91cd\u70b9&#xff1a;\u540c\u4e00\u65f6\u95f4\u53ea\u5141\u8bb8\u4e00\u4e2a\u4e3b\u673a\u638c\u63e1\u603b\u7ebf\u63a7\u5236\u6743\u3002 \u591a\u4e3b\u673a\u573a\u666f\u4f9d\u9760\u603b\u7ebf\u4ef2\u88c1\u673a\u5236&#xff0c;\u907f\u514d\u591a\u4e2a\u4e3b\u673a\u540c\u65f6\u53d1\u9001\u4fe1\u53f7\u9020\u6210\u51b2\u7a81\u3002<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094131-6aa51e4ba18a3.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n<h3>\u4e94\u3001\u901a\u4fe1\u901f\u7387<\/h3>\n<ul>\n<li>\u6807\u51c6\u6a21\u5f0f&#xff1a;\u6700\u9ad8 100kHz<\/li>\n<li>\u5feb\u901f\u6a21\u5f0f&#xff1a;\u6700\u9ad8 400kHz<\/li>\n<li>\u8d85\u9ad8\u901f\u6a21\u5f0f&#xff1a;\u6700\u9ad83.4MHz<\/li>\n<\/ul>\n<p>\u901a\u4fe1\u5c5e\u6027&#xff1a;\u540c\u6b65\u3001\u4e32\u884c\u3001\u534a\u53cc\u5de5<\/p>\n<ul>\n<li>\u540c\u6b65&#xff1a;\u901a\u4fe1\u65f6\u5e8f\u5b8c\u5168\u8ddf\u968f SCL \u65f6\u949f&#xff1b;<\/li>\n<li>\u4e32\u884c&#xff1a;\u6570\u636e\u6309 bit \u9010\u4f4d\u4f20\u8f93&#xff1b;<\/li>\n<li>\u534a\u53cc\u5de5&#xff1a;\u540c\u4e00\u65f6\u523b\u53ea\u80fd\u5355\u5411\u4f20\u8f93&#xff0c;\u4e0d\u80fd\u540c\u65f6\u6536\u53d1\u3002<\/li>\n<\/ul>\n<h3>\u516d\u3001\u534f\u8bae\u5c42<\/h3>\n<h4>6.1 \u8d77\u59cb\u4fe1\u53f7 &amp; \u505c\u6b62\u4fe1\u53f7<\/h4>\n<ul>\n<li>\u8d77\u59cb\u4fe1\u53f7 (S)&#xff1a;SCL \u4e3a\u9ad8\u7535\u5e73\u65f6&#xff0c;SDA \u7531\u9ad8\u7535\u5e73\u8df3\u53d8\u5230\u4f4e\u7535\u5e73&#xff0c;\u8868\u793a\u901a\u4fe1\u5f00\u59cb\u3002<\/li>\n<li>\u53e3\u8bc0&#xff1a;sda\u5148\u62c9\u4f4e&#xff0c;scl\u540e\u62c9\u4f4e\u3002<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094132-6aa51e4c02244.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<li>\u505c\u6b62\u4fe1\u53f7 \u00a7&#xff1a;SCL \u4e3a\u9ad8\u7535\u5e73\u65f6&#xff0c;SDA \u7531\u4f4e\u7535\u5e73\u8df3\u53d8\u5230\u9ad8\u7535\u5e73&#xff0c;\u8868\u793a\u901a\u4fe1\u7ed3\u675f&#xff0c;\u603b\u7ebf\u56de\u5230\u7a7a\u95f2\u72b6\u6001\u3002<\/li>\n<li>\u53e3\u8bc0&#xff1a;sda\u540e\u62c9\u9ad8&#xff0c;scl\u5148\u62c9\u9ad8\u3002<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094132-6aa51e4cec05d.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<p>\u53ea\u6709 SCL \u5904\u4e8e\u9ad8\u7535\u5e73\u671f\u95f4&#xff0c;SDA \u7684\u8df3\u53d8\u624d\u4ee3\u8868\u8d77\u59cb \/ \u505c\u6b62&#xff1b;SCL \u4f4e\u7535\u5e73\u65f6&#xff0c;\u5141\u8bb8 SDA \u6539\u53d8\u7535\u5e73&#xff0c;\u7528\u6765\u4f20\u8f93\u6570\u636e bit\u3002<\/p>\n<h4>6.2 \u6570\u636e\u4f4d\u4f20\u8f93\u89c4\u5219<\/h4>\n<p>SCL \u9ad8\u7535\u5e73\u9636\u6bb5&#xff1a;SDA \u7535\u5e73\u5fc5\u987b\u4fdd\u6301\u7a33\u5b9a&#xff0c;\u63a5\u6536\u7aef\u91c7\u6837 SDA \u5f97\u5230\u6570\u636e&#xff1b; SCL \u4f4e\u7535\u5e73\u9636\u6bb5&#xff1a;\u5141\u8bb8 SDA \u7535\u5e73\u7ffb\u8f6c&#xff0c;\u51c6\u5907\u4e0b\u4e00\u4f4d\u6570\u636e\u3002 \u6bcf\u4f20\u8f93 1bit \u6570\u636e&#xff0c;\u5bf9\u5e94\u4e00\u4e2a SCL \u65f6\u949f\u5468\u671f\u3002 \u53e3\u8bc0&#xff1a;\u4f4e\u7535\u5e73\u5207\u6362\u6570\u636e&#xff0c;\u9ad8\u7535\u5e73\u4fdd\u6301\u3002<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094133-6aa51e4d85be3.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n<h4>6.3 ACK \u5e94\u7b54\u4fe1\u53f7<\/h4>\n<p>\u6bcf\u53d1\u9001\u5b8c 8bit&#xff08;1 \u5b57\u8282&#xff09;\u6570\u636e\u4e4b\u540e&#xff0c;\u63a5\u6536\u65b9\u9700\u8981\u62c9\u4f4e SDA \u4ea7\u751f\u5e94\u7b54 ACK&#xff1b;<\/p>\n<ul>\n<li>ACK&#xff08;\u5e94\u7b54&#xff09;&#xff1a;\u63a5\u6536\u65b9\u5c06 SDA \u62c9\u4f4e&#xff0c;\u544a\u8bc9\u53d1\u9001\u65b9\u63a5\u6536\u6b63\u5e38&#xff1b;<\/li>\n<li>NACK&#xff08;\u975e\u5e94\u7b54&#xff09;&#xff1a;SDA \u4fdd\u6301\u9ad8\u7535\u5e73&#xff0c;\u4ee3\u8868\u65e0\u5e94\u7b54&#xff0c;\u901a\u5e38\u8868\u793a\u4ece\u673a\u672a\u6536\u5230\u3001\u7ed3\u675f\u8bfb\u64cd\u4f5c\u3002<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094133-6aa51e4df3c29.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<h4>6.4 \u4e09\u79cd\u5de5\u4f5c\u6a21\u5f0f<\/h4>\n<ul>\n<li>\u5199\u6a21\u5f0f&#xff1a;\u5f00\u59cb\u4fe1\u53f7 \u2192\u4e3b\u673a\u53d1\u4ece\u673a\u5730\u5740 &#043; \u5199\u4f4d \u2192 \u4ece\u673a ACK \u2192 \u4e3b\u673a\u53d1\u9001\u5bc4\u5b58\u5668\u5730\u5740\/\u6216\u8005\u76f4\u63a5\u4ece\u5934\u5f00\u59cb\u5199\u6570\u636e \u2192 \u4ece\u673a ACK \u2192 \u4e3b\u673a\u53d1\u9001\u6570\u636e \u2192 \u4ece\u673a ACK\u2026 \u2192 \u505c\u6b62\u4fe1\u53f7<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094134-6aa51e4e65187.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<li>\u8bfb\u6a21\u5f0f&#xff1a;\u5f00\u59cb\u4fe1\u53f7 \u2192 \u4e3b\u673a\u53d1\u4ece\u673a\u5730\u5740 &#043; \u8bfb\u4f4d \u2192 \u4ece\u673aACK \u2192 \u4e3b\u673a\u8bfb\u53d6\u6570\u636e&#xff08;\u53d8\u73b0\u4e3a\u4e0d\u5de5\u4f5c&#xff0c;\u9ad8\u963b\u6001&#xff0c;\u901a\u8fc7\u4e0a\u62c9\u7535\u963b\u8f93\u5165\u6570\u636e&#xff09;\u2192 \u4e3b\u673aACK \u2192 \u8bfb\u53d6\u4e0b\u4e00\u4e2a\u6570\u636e \u2192\u4e3b\u673aACK\u2026\u2192\u4e3b\u673aNACK\u2192\u505c\u6b62\u4fe1\u53f7<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094135-6aa51e4f02eea.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<li>\u5148\u5199\u540e\u8bfb\u6a21\u5f0f&#xff1a;\u5f00\u59cb\u4fe1\u53f7 \u2192 \u4e3b\u673a\u53d1\u4ece\u673a\u5730\u5740 &#043; \u5199\u4f4d \u2192 \u6307\u5b9a\u5bc4\u5b58\u5668\u6216\u5148\u4ece\u5934\u5199\u5165\u6570\u636e\u2192\u2026\u2192\u4ece\u673aACK \u2192 \u91cd\u65b0\u53d1\u8d77\u8d77\u59cb\u2192\u53d1\u9001\u4ece\u673a\u5730\u5740 &#043; \u8bfb\u4f4d \u2192 \u4ece\u673a ACK \u2192 \u4ece\u673a\u8f93\u51fa\u6570\u636e \u2192 \u4e3b\u673aACK\u2026\u2192 \u4e3b\u673a NACK \u2192 \u53d1\u51fa\u505c\u6b62\u4fe1\u53f7\u7ed3\u675f\u8bfb\u53d6\u3002<img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094135-6aa51e4f6ab7d.jpg\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/li>\n<\/ul>\n<h4>6.5 \u591a\u4e3b\u673a\u4e0e\u603b\u7ebf\u4ef2\u88c1<\/h4>\n<p>\u591a\u4e2a\u4e3b\u673a\u540c\u65f6\u62a2\u5360\u603b\u7ebf\u65f6&#xff0c;\u4ef2\u88c1\u903b\u8f91&#xff1a; \u4e3b\u673a\u4e00\u8fb9\u53d1\u9001\u6570\u636e&#xff0c;\u4e00\u8fb9\u5b9e\u65f6\u76d1\u542c SDA \u603b\u7ebf\u7535\u5e73&#xff1b; \u5982\u679c\u81ea\u5df1\u8f93\u51fa\u9ad8\u7535\u5e73&#xff0c;\u4f46\u603b\u7ebf\u88ab\u522b\u7684\u4e3b\u673a\u62c9\u4e3a\u4f4e\u7535\u5e73&#xff0c;\u4ee3\u8868\u4ef2\u88c1\u5931\u8d25&#xff0c;\u8be5\u4e3b\u673a\u7acb\u523b\u505c\u6b62\u53d1\u9001&#xff0c;\u8ba9\u51fa\u603b\u7ebf&#xff0c;\u7b49\u5f85\u603b\u7ebf\u7a7a\u95f2\u540e\u91cd\u65b0\u53d1\u8d77\u901a\u4fe1\u3002<\/p>\n<h3>\u4e03\u3001IIC \u6838\u5fc3\u5c0f\u7ed3<\/h3>\n<li>\u786c\u4ef6&#xff1a;SDA&#043;SCL&#xff0c;\u5f00\u6f0f\u8f93\u51fa&#xff0c;\u5fc5\u987b\u5916\u90e8\u4e0a\u62c9\u7535\u963b&#xff1b;\u7a7a\u95f2\u603b\u7ebf\u4e3a\u9ad8\u7535\u5e73&#xff1b;<\/li>\n<li>\u5bfb\u5740&#xff1a;7 \u4f4d\u8bbe\u5907\u5730\u5740 &#043; 1 \u4f4d\u8bfb\u5199\u4f4d&#xff1b;\u4ece\u673a\u4e4b\u95f4\u4e0d\u80fd\u76f4\u63a5\u901a\u4fe1&#xff1b;<\/li>\n<li>\u4fe1\u53f7&#xff1a;\u8d77\u59cb\u3001\u505c\u6b62\u3001\u5e94\u7b54 ACK\/NACK&#xff0c;SCL \u9ad8\u7535\u5e73\u91c7\u6837\u6570\u636e&#xff0c;SCL\u4f4e\u7535\u5e73SDA\u8f6c\u6362&#xff1b;<\/li>\n<li>\u652f\u6301\u591a\u4e3b\u673a&#xff0c;\u4f46\u540c\u4e00\u65f6\u523b\u4ec5\u6709\u4e00\u4e2a\u4e3b\u673a\u6709\u6548&#xff0c;\u4f9d\u9760\u603b\u7ebf\u4ef2\u88c1\u89e3\u51b3\u51b2\u7a81&#xff1b;<\/li>\n<li>\u534a\u53cc\u5de5\u540c\u6b65\u4e32\u884c&#xff0c;\u9002\u5408\u677f\u5185\u77ed\u8ddd\u79bb\u5c0f\u6570\u636e\u5916\u8bbe&#xff08;OLED\u3001DS18B20\u3001EEPROM \u7b49&#xff09;\u3002<\/li>\n<h3>\u516b\u3001Verilog \u5b9e\u73b0 IIC \u534f\u8bae<\/h3>\n<p>\u8bf4\u660e&#xff1a;\u4e3a\u672c\u7bc7\u521d\u7a3f\u5b9e\u73b0&#xff0c;\u652f\u6301 IIC \u5199\u3001\u8bfb\u3001\u7ec4\u5408\u8bfb\u5199&#xff08;\u91cd\u590d\u8d77\u59cb&#xff09;&#xff0c;\u5185\u90e8\u91c7\u7528\u4e09\u6bb5\u5f0f\u72b6\u6001\u673a&#xff0c;\u4f7f\u7528\u4e09\u6001\u95e8\u5904\u7406 SDA\/SCL \u53cc\u5411\u7aef\u53e3\u3002<\/p>\n<p>module top (<br \/>\n    input   wire            clk        ,<br \/>\n    input   wire            rst_n      ,<br \/>\n    input   wire            start_iic  ,\/\/\u534f\u8bae\u5f00\u59cb\u4fe1\u53f7<br \/>\n    input   wire            worr       ,\/\/\u65b9\u5411\u4fe1\u53f7<br \/>\n    input   wire    [7:0]   sendnum    ,\/\/\u5668\u4ef6\u89c4\u5b9a\u4e3b\u673a\u7684\u5199\u5165\u6570\u636e\u91cf<br \/>\n    input   wire    [7:0]   recvnum    ,\/\/\u89c4\u5b9a\u4e3b\u673a\u7684\u8bfb\u51fa\u6570\u636e\u91cf<br \/>\n    input   wire    [7:0]   data_i_iic ,\/\/\u5916\u90e8\u7ed9\u5230\u7684\u6570\u636e<br \/>\n    output  wire    [7:0]   data_o_iic ,\/\/\u4ece\u673a\u91cc\u9762\u8bfb\u5230\u3001\u8f93\u51fa\u7684\u6570\u636e<br \/>\n    output  wire            done_w     ,\/\/\u5b8c\u6210\u4e00\u6b21\u5199\u6570\u636e\u7684\u63e1\u624b\u4fe1\u53f7<br \/>\n    output  wire            done_r     ,\/\/\u5b8c\u6210\u4e00\u6b21\u8bfb\u6570\u636e\u7684\u63e1\u624b\u4fe1\u53f7<br \/>\n    output  wire            done_iic   ,\/\/\u5b8c\u6210\u4e00\u6b21iic\u901a\u4fe1\u7684\u63e1\u624b\u4fe1\u53f7<br \/>\n    output  wire            wrong      ,\/\/\u62a5\u8b66\u4fe1\u53f7<br \/>\n    inout   wire            scl        ,\/\/\u65f6\u949f\u603b\u7ebf<br \/>\n    inout   wire            sda         \/\/\u6570\u636e\u603b\u7ebf<br \/>\n);<br \/>\n    \/\/\u53c2\u6570<br \/>\n    parameter   sysclk &#061; 50_000_000     ,\/\/\u7cfb\u7edf\u65f6\u949f<br \/>\n                iiclk  &#061; 100_000        ,\/\/iic\u901f\u7387<br \/>\n                delay  &#061; sysclk\/iiclk   ,\/\/\u53d1\u4e00\u6bd4\u7279\u6240\u7528\u5468\u671f\u657010us<br \/>\n                MID    &#061; delay\/2        ,\/\/5us<br \/>\n                Q_MID  &#061; delay\/4        ,\/\/2.5us<br \/>\n                TQ_MID &#061; MID &#043; Q_MID    ,\/\/12.5us<br \/>\n                ID_W   &#061; 8&#039;b1010_0000   ,\/\/\u8bbe\u5907ID&#043;\u65b9\u5411<br \/>\n                ID_R   &#061; 8&#039;b1010_0001   ;\/\/\u8bbe\u5907ID&#043;\u65b9\u5411   <\/p>\n<p>    \/\/\u72b6\u6001\u5b9a\u4e49<br \/>\n    localparam  IDLE    &#061; &#039;d1  ,<br \/>\n                START1  &#061; &#039;d2  ,<br \/>\n                IDW     &#061; &#039;d3  ,<br \/>\n                ACK1    &#061; &#039;d4  ,<br \/>\n                WDATA   &#061; &#039;d5  ,<br \/>\n                ACK2    &#061; &#039;d6  ,<br \/>\n                STOP    &#061; &#039;d7  ,<br \/>\n                IDR     &#061; &#039;d8  ,<br \/>\n                ACK3    &#061; &#039;d9  ,<br \/>\n                RDATA   &#061; &#039;d10 ,<br \/>\n                ACK4    &#061; &#039;d11 ,<br \/>\n                START2  &#061; &#039;d12 ;<\/p>\n<p>    reg [3:0]   state_c,state_n;<\/p>\n<p>    \/\/\u72b6\u6001\u8f6c\u79fb<br \/>\n    wire        IDLE_START1 ,<br \/>\n                START1_IDW  ,<br \/>\n                IDW_ACK1    ,<br \/>\n                ACK1_WDATA  ,<br \/>\n                WDATA_ACK2  ,<br \/>\n                ACK2_WDATA  ,<br \/>\n                ACK2_STOP   ,\/\/\u7b2c\u4e00\u79cd\u5de5\u4f5c\u6a21\u5f0f&#xff1a;IDLE -&gt; START1 -&gt; IDW -&gt; ACK1 -&gt; WDATA &lt;&#8211;&gt; ACK2 -&gt;STOP -&gt;ILDE<br \/>\n                START1_IDR  ,<br \/>\n                IDR_ACK3    ,<br \/>\n                ACK3_RDATA  ,<br \/>\n                RDATA_ACK4  ,<br \/>\n                ACK4_RDATA  ,<br \/>\n                ACK4_STOP   ,\/\/\u7b2c\u4e8c\u79cd\u5de5\u4f5c\u6a21\u5f0f&#xff1a;IDLE -&gt; START1 -&gt; IDR -&gt; ACK3 -&gt; RDATA &lt;&#8211;&gt; ACK4 -&gt;STOP -&gt;ILDE<br \/>\n                ACK2_START2 ,<br \/>\n                START2_IDR  ,\/\/\u7b2c\u4e09\u79cd\u5de5\u4f5c\u65b9\u5f0f&#xff1a;IDLE -&gt; START1 -&gt; IDW -&gt; ACK1 -&gt; WDATA &lt;&#8211;&gt; ACK2 -&gt; IDR -&gt; ACK3 -&gt; RDATA &lt;&#8211;&gt; ACK4 -&gt;STOP -&gt;ILDE<br \/>\n                ACK1_STOP   ,\/\/\u4ece\u673a\u9519\u8bef\u5e94\u7b54\u60c5\u51b5<br \/>\n                ACK3_STOP   ,\/\/\u4ece\u673a\u9519\u8bef\u5e94\u7b54\u60c5\u51b5<br \/>\n                STOP_IDLE   ;<\/p>\n<p>    \/\/\u5185\u90e8\u4fe1\u53f7<br \/>\n    \/\/\u8ba1\u6570\u5668<br \/>\n    reg     [9:0]   cnt_time ;\/\/\u65f6\u95f4\u8ba1\u6570<br \/>\n    reg     [3:0]   cnt_bit  ;\/\/\u6bd4\u7279\u8ba1\u6570<br \/>\n    \/\/\u5bc4\u5b58\u4fe1\u53f7<br \/>\n    reg     [1:0]   start_reg   ;\/\/\u534f\u8bae\u5f00\u59cb&#xff0c;\u4e24\u4e2a\u4f4d\u5bbd\u662f\u4e3a\u4e86\u540e\u7eed\u6839\u636e\u9700\u6c42\u9009\u62e9\u957f\u77ed\u4fe1\u53f7<br \/>\n    reg             worr_reg    ;\/\/\u5de5\u4f5c\u6a21\u5f0f1\/2\u9009\u62e9<br \/>\n    reg     [7:0]   sendnum_reg ;<br \/>\n    reg     [7:0]   recvnum_reg ;<br \/>\n    reg     [7:0]   data_reg    ;<br \/>\n    \/\/\u6570\u636e\u91cf\u8ba1\u6570<br \/>\n    reg     [7:0]   sendcnt  ;\/\/\u53d1\u9001\u8ba1\u6570<br \/>\n    reg     [7:0]   recvcnt  ;\/\/\u63a5\u6536\u8ba1\u6570<br \/>\n    \/\/\u6570\u636e\u6682\u5b58\u548c\u5e94\u7b54\u4fe1\u53f7<br \/>\n    reg     [7:0]   data_temp ;<br \/>\n    reg             ack_flag  ;\/\/\u5e94\u7b54\u4fe1\u53f7<br \/>\n    \/\/\u4e09\u6001\u95e8\u4fe1\u53f7<br \/>\n    reg     scl_en  ;<br \/>\n    reg     scl_out ;<br \/>\n    wire    scl_in  ;    <\/p>\n<p>    reg     sda_en  ;<br \/>\n    reg     sda_out ;<br \/>\n    wire    sda_in  ;   <\/p>\n<p>    \/\/\u4e09\u6001\u95e8<br \/>\n    assign  scl &#061; scl_en ? scl_out : 1&#039;bz;<br \/>\n    assign  scl_in &#061; scl;<\/p>\n<p>    assign  sda &#061; sda_en ? sda_out : 1&#039;bz;<br \/>\n    assign  sda_in &#061; sda;<\/p>\n<p>    \/\/\u8f93\u5165\u6570\u636e\u5bc4\u5b58<br \/>\n    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (rst_n &#061;&#061; 0) begin<br \/>\n            start_reg &lt;&#061; 2&#039;b00;<br \/>\n        end<br \/>\n        else begin<br \/>\n            start_reg &lt;&#061; {start_reg[0],start_iic};<br \/>\n        end<br \/>\n    end<\/p>\n<p>    \/\/\u72b6\u6001\u673a\u7b2c\u4e00\u6bb5<br \/>\n    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (rst_n &#061;&#061; 0) begin<br \/>\n            state_c &lt;&#061; IDLE;<br \/>\n        end<br \/>\n        else begin<br \/>\n            state_c &lt;&#061; state_n;<br \/>\n        end<br \/>\n    end<\/p>\n<p>    \/\/\u72b6\u6001\u673a\u7b2c\u4e8c\u6bb5<br \/>\n    always &#064;(*) begin<br \/>\n        if (rst_n &#061;&#061; 0) begin<br \/>\n            state_n &#061; IDLE;<br \/>\n        end<br \/>\n        else begin<br \/>\n            case (state_c)<br \/>\n                IDLE   : state_n &#061; (IDLE_START1) ? START1: IDLE   ;<br \/>\n                START1 : state_n &#061; (START1_IDW ) ? IDW   : (START1_IDR) ? IDR : START1;<br \/>\n                IDW    : state_n &#061; (IDW_ACK1   ) ? ACK1  : IDW    ;<br \/>\n                ACK1   : state_n &#061; (ACK1_STOP  ) ? STOP  : (ACK1_WDATA) ? WDATA : ACK1;<br \/>\n                WDATA  : state_n &#061; (WDATA_ACK2 ) ? ACK2  : WDATA  ;<br \/>\n                ACK2   : state_n &#061; (ACK2_STOP  ) ? STOP  : (ACK2_START2)?START2 :(ACK2_WDATA ) ? WDATA : ACK2;<br \/>\n                STOP   : state_n &#061; (STOP_IDLE  ) ? IDLE  : STOP   ;<br \/>\n                IDR    : state_n &#061; (IDR_ACK3   ) ? ACK3  : IDR    ;<br \/>\n                ACK3   : state_n &#061; (ACK3_STOP  ) ? STOP  : (ACK3_RDATA ) ? RDATA : ACK3;<br \/>\n                RDATA  : state_n &#061; (RDATA_ACK4 ) ? ACK4  : RDATA  ;<br \/>\n                ACK4   : state_n &#061; (ACK4_STOP  ) ? STOP  : (ACK4_RDATA ) ? RDATA : ACK4;<br \/>\n                START2 : state_n &#061; (START2_IDR ) ? IDR   : START2 ;<br \/>\n                default: state_n &#061; IDLE;<br \/>\n            endcase<br \/>\n        end<br \/>\n    end  <\/p>\n<p>    assign  IDLE_START1 &#061; (state_c &#061;&#061; IDLE  ) &amp;&amp; start_reg &#061;&#061; 2&#039;b01;<br \/>\n    assign  START1_IDW  &#061; (state_c &#061;&#061; START1) &amp;&amp; cnt_time &#061;&#061; delay &#043; Q_MID &#8211; 1 &amp;&amp; worr_reg &#061;&#061; 0;<br \/>\n    assign  START1_IDR  &#061; (state_c &#061;&#061; START1) &amp;&amp; cnt_time &#061;&#061; delay &#043; Q_MID &#8211; 1 &amp;&amp; worr_reg &#061;&#061; 1;<br \/>\n    assign  IDW_ACK1    &#061; (state_c &#061;&#061; IDW   ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; cnt_bit &#061;&#061; 7;<br \/>\n    assign  ACK1_STOP   &#061; (state_c &#061;&#061; ACK1  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; ack_flag &#061;&#061; 1;<br \/>\n    assign  ACK1_WDATA  &#061; (state_c &#061;&#061; ACK1  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; ack_flag &#061;&#061; 0;<br \/>\n    assign  WDATA_ACK2  &#061; (state_c &#061;&#061; WDATA ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; cnt_bit &#061;&#061; 7;<br \/>\n    assign  ACK2_STOP   &#061; (state_c &#061;&#061; ACK2  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; (sendcnt &#061;&#061; sendnum &amp;&amp; recvnum &#061;&#061; 0 &amp;&amp; ack_flag &#061;&#061; 0)||ack_flag &#061;&#061; 1;<br \/>\n    assign  ACK2_WDATA  &#061; (state_c &#061;&#061; ACK2  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; sendcnt &lt; sendnum &amp;&amp; ack_flag &#061;&#061; 0;<br \/>\n    assign  IDR_ACK3    &#061; (state_c &#061;&#061; IDR   ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; cnt_bit &#061;&#061; 7;<br \/>\n    assign  ACK3_STOP   &#061; (state_c &#061;&#061; ACK3  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; ack_flag &#061;&#061; 1;<br \/>\n    assign  ACK3_RDATA  &#061; (state_c &#061;&#061; ACK3  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; ack_flag &#061;&#061; 0;<br \/>\n    assign  RDATA_ACK4  &#061; (state_c &#061;&#061; RDATA ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; cnt_bit &#061;&#061; 7;<br \/>\n    assign  ACK4_STOP   &#061; (state_c &#061;&#061; ACK4  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; recvcnt &#061;&#061; recvnum;<br \/>\n    assign  ACK2_START2 &#061; (state_c &#061;&#061; ACK2  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; sendcnt &#061;&#061; sendnum &amp;&amp; recvnum !&#061; 0;<br \/>\n    assign  ACK4_RDATA  &#061; (state_c &#061;&#061; ACK4  ) &amp;&amp; cnt_time &#061;&#061; delay &#8211; 1 &amp;&amp; recvcnt &lt; recvnum;<br \/>\n    assign  START2_IDR  &#061; (state_c &#061;&#061; START2) &amp;&amp; cnt_time &#061;&#061; delay &#043; Q_MID &#8211; 1 ;<br \/>\n    assign  STOP_IDLE   &#061; (state_c &#061;&#061; STOP  ) &amp;&amp; cnt_time &#061;&#061; delay &#043; Q_MID &#8211; 1 ;    <\/p>\n<p>    \/\/\u72b6\u6001\u673a\u7b2c\u4e09\u6bb5<br \/>\n    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (rst_n &#061;&#061; 0) begin<br \/>\n            \/\/\u8ba1\u6570<br \/>\n            cnt_time    &lt;&#061; 0;<br \/>\n            cnt_bit     &lt;&#061; 0;<br \/>\n            \/\/\u5bc4\u5b58<br \/>\n            worr_reg    &lt;&#061; 0;<br \/>\n            sendnum_reg &lt;&#061; 0;<br \/>\n            recvnum_reg &lt;&#061; 0;<br \/>\n            data_reg    &lt;&#061; 0;<br \/>\n            \/\/\u6570\u636e\u91cf<br \/>\n            sendcnt     &lt;&#061; 0;<br \/>\n            recvcnt     &lt;&#061; 0;    <\/p>\n<p>            data_temp   &lt;&#061; 0;<br \/>\n            ack_flag    &lt;&#061; 0;<br \/>\n            \/\/\u4e09\u6001\u95e8<br \/>\n            scl_en      &lt;&#061; 0;<br \/>\n            sda_en      &lt;&#061; 0;<br \/>\n            scl_out     &lt;&#061; 0;<br \/>\n            sda_out     &lt;&#061; 0;<br \/>\n        end<br \/>\n        else begin<br \/>\n            case (state_c)<br \/>\n                IDLE   :begin\/\/\u5bc4\u5b58\u4fe1\u53f7&#xff0c;\u4e3b\u673a\u4e0d\u5de5\u4f5c<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    cnt_time    &lt;&#061; 0;<br \/>\n                    cnt_bit     &lt;&#061; 0;<br \/>\n                    \/\/\u5bc4\u5b58<br \/>\n                    worr_reg    &lt;&#061; worr;<br \/>\n                    sendnum_reg &lt;&#061; sendnum;<br \/>\n                    recvnum_reg &lt;&#061; recvnum;<br \/>\n                    data_reg    &lt;&#061; data_i_iic;<br \/>\n                    \/\/\u6570\u636e\u91cf\u8ba1\u6570<br \/>\n                    sendcnt     &lt;&#061; 0;<br \/>\n                    recvcnt     &lt;&#061; 0;    <\/p>\n<p>                    data_temp   &lt;&#061; 0;<br \/>\n                    ack_flag    &lt;&#061; 0;<br \/>\n                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 0;<br \/>\n                    sda_en      &lt;&#061; 0;<br \/>\n                    scl_out     &lt;&#061; 1;\/\/\u8c61\u5f81\u4e3a\u9ad8\u963b&#xff0c;\u4f46\u5b9e\u9645\u4e0a\u4e0d\u4f1a\u88ab\u8f93\u51fa<br \/>\n                    sda_out     &lt;&#061; 1;\/\/\u8c61\u5f81\u4e3a\u9ad8\u963b&#xff0c;\u4f46\u5b9e\u9645\u4e0a\u4e0d\u4f1a\u88ab\u8f93\u51fa<br \/>\n                end<br \/>\n                START1,START2:begin\/\/\u5f00\u59cb\u65f6\u5e8f&#xff1a;\u4e3b\u673a\u5de5\u4f5c&#xff0c;sda\u5148\u62c9\u4f4e&#xff0c;scl\u540e\u62c9\u4f4e<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#043; Q_MID &#8211; 1) begin\/\/\u8ba1\u657012.5us<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    cnt_bit     &lt;&#061; 0;<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 1;<\/p>\n<p>                    if (cnt_time &gt;&#061; delay) begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    if (cnt_time &gt;&#061; MID) begin<br \/>\n                        sda_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        sda_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                end<br \/>\n                IDW    :begin\/\/\u4e3b\u673a\u5de5\u4f5c&#xff1a;\u53d1\u9001\u4ece\u673a\u5730\u5740<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin<br \/>\n                        if (cnt_bit &#061;&#061; 7) begin<br \/>\n                            cnt_bit &lt;&#061; 0;<br \/>\n                        end<br \/>\n                        else begin<br \/>\n                            cnt_bit &lt;&#061; cnt_bit &#043; 1;<br \/>\n                        end<br \/>\n                    end<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 1;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; 1) begin<br \/>\n                        sda_out &lt;&#061; ID_W[7 &#8211; cnt_bit];\/\/\u9ad8\u4f4d\u4f18\u5148<br \/>\n                    end<br \/>\n                end<br \/>\n                ACK1,ACK3:begin\/\/\u91c7\u96c6\u5e94\u7b54\u4fe1\u53f7\u3001\u7ef4\u6301\u65f6\u949f\u8f93\u51fa<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    cnt_bit     &lt;&#061; 0;<br \/>\n                    \/\/\u5bc4\u5b58   <\/p>\n<p>                    if (cnt_time &#061;&#061; MID) begin\/\/\u91c7\u6837\u70b9<br \/>\n                        ack_flag &lt;&#061; sda_in;<br \/>\n                    end    <\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 0;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    sda_out     &lt;&#061; 1;<br \/>\n                end<br \/>\n                WDATA  :begin\/\/\u4e3b\u673a\u5de5\u4f5c&#xff1a;\u5199\u6570\u636e\u3001\u6570\u636e\u91cf\u8ba1\u6570\u4fdd\u6301<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin<br \/>\n                        if (cnt_bit &#061;&#061; 7) begin<br \/>\n                            cnt_bit &lt;&#061; 0;<br \/>\n                        end<br \/>\n                        else begin<br \/>\n                            cnt_bit &lt;&#061; cnt_bit &#043; 1;<br \/>\n                        end<br \/>\n                    end<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 1;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; 0) begin<br \/>\n                        sda_out &lt;&#061; data_reg[7 &#8211; cnt_bit];\/\/\u9ad8\u4f4d\u4f18\u5148<br \/>\n                    end<br \/>\n                end<br \/>\n                ACK2   :begin\/\/\u91c7\u96c6\u5e94\u7b54\u4fe1\u53f7\u3001\u7ef4\u6301\u65f6\u949f\u8f93\u51fa\u3001\u5bf9\u6570\u636e\u91cf\u8fdb\u884c\u8ba1\u6570<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    cnt_bit     &lt;&#061; 0;<br \/>\n                    \/\/\u5bc4\u5b58<\/p>\n<p>                    if (cnt_time &#061;&#061; 0) begin\/\/\u5b8c\u6210\u4e00\u6b21\u6570\u636e\u5199\u5165&#xff0c;\u8ba1\u6570&#043;1<br \/>\n                       sendcnt &lt;&#061; sendcnt &#043; 1;<br \/>\n                    end<\/p>\n<p>                    \/\/\u66f4\u65b0\u6570\u636e<br \/>\n                    data_reg &lt;&#061; data_i_iic;<\/p>\n<p>                    if (cnt_time &#061;&#061; MID) begin\/\/\u91c7\u6837\u70b9<br \/>\n                        ack_flag &lt;&#061; sda_in;<br \/>\n                    end    <\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 0;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    sda_out     &lt;&#061; 1;<br \/>\n                end<br \/>\n                STOP   :begin\/\/\u505c\u6b62\u65f6\u5e8f&#xff1a;\u4e3b\u673a\u5de5\u4f5c&#xff0c;sda\u540e\u62c9\u9ad8&#xff0c;scl\u5148\u62c9\u9ad8<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#043; Q_MID &#8211; 1) begin\/\/\u8ba1\u657012.5us<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    cnt_bit     &lt;&#061; 0;<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 1;<\/p>\n<p>                    if (cnt_time &gt;&#061; Q_MID) begin<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    if (cnt_time &gt;&#061; TQ_MID) begin<br \/>\n                        sda_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        sda_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                end<br \/>\n                IDR    :begin\/\/\u4e3b\u673a\u5de5\u4f5c&#xff1a;\u53d1\u9001\u4ece\u673a\u5730\u5740<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin<br \/>\n                        if (cnt_bit &#061;&#061; 7) begin<br \/>\n                            cnt_bit &lt;&#061; 0;<br \/>\n                        end<br \/>\n                        else begin<br \/>\n                            cnt_bit &lt;&#061; cnt_bit &#043; 1;<br \/>\n                        end<br \/>\n                    end<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 1;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; 1) begin<br \/>\n                        sda_out &lt;&#061; ID_R[7 &#8211; cnt_bit];\/\/\u9ad8\u4f4d\u4f18\u5148<br \/>\n                    end<br \/>\n                end<br \/>\n                RDATA  :begin\/\/\u4ece\u673a\u5de5\u4f5c&#xff0c;\u4e3b\u673a\u8bfb\u6570\u636e\u3001\u6570\u636e\u91cf\u8ba1\u6570\u4fdd\u6301<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin<br \/>\n                        if (cnt_bit &#061;&#061; 7) begin<br \/>\n                            cnt_bit &lt;&#061; 0;<br \/>\n                        end<br \/>\n                        else begin<br \/>\n                            cnt_bit &lt;&#061; cnt_bit &#043; 1;<br \/>\n                        end<br \/>\n                    end<\/p>\n<p>                    if (cnt_time &#061;&#061; MID) begin<br \/>\n                        data_temp[7-cnt_bit] &lt;&#061; sda_in;<br \/>\n                    end<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 0;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    sda_out     &lt;&#061; 1;<br \/>\n                end<br \/>\n                ACK4   :begin\/\/\u53d1\u51fa\u5e94\u7b54\u4fe1\u53f7<br \/>\n                    \/\/\u8ba1\u6570<br \/>\n                    if (cnt_time &#061;&#061; delay &#8211; 1) begin\/\/\u5468\u671f\u8ba1\u6570<br \/>\n                        cnt_time &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        cnt_time &lt;&#061; cnt_time &#043; 1;<br \/>\n                    end<br \/>\n                    cnt_bit     &lt;&#061; 0;<br \/>\n                    \/\/\u5bc4\u5b58<\/p>\n<p>                    if (cnt_time &#061;&#061; 0) begin\/\/\u5b8c\u6210\u4e00\u6b21\u6570\u636e\u5199\u5165&#xff0c;\u8ba1\u6570&#043;1<br \/>\n                       recvcnt  &lt;&#061; recvcnt  &#043; 1;<br \/>\n                    end<\/p>\n<p>                    \/\/\u4e09\u6001\u95e8<br \/>\n                    scl_en      &lt;&#061; 1;<br \/>\n                    sda_en      &lt;&#061; 1;<\/p>\n<p>                    if (cnt_time &gt;&#061;Q_MID &amp;&amp; cnt_time &lt;&#061; TQ_MID-1) begin\/\/\u4e24\u8fb9\u9ad8\u4e2d\u95f4\u4f4e<br \/>\n                        scl_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        scl_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                    if (recvcnt &#061;&#061; recvnum) begin<br \/>\n                        sda_out &lt;&#061; 1;<br \/>\n                    end<br \/>\n                    else begin<br \/>\n                        sda_out &lt;&#061; 0;<br \/>\n                    end<br \/>\n                end<br \/>\n                default: begin<br \/>\n            \/\/\u8ba1\u6570<br \/>\n            cnt_time    &lt;&#061; 0;<br \/>\n            cnt_bit     &lt;&#061; 0;<br \/>\n            \/\/\u5bc4\u5b58<br \/>\n            worr_reg    &lt;&#061; 0;<br \/>\n            sendnum_reg &lt;&#061; 0;<br \/>\n            recvnum_reg &lt;&#061; 0;<br \/>\n            data_reg    &lt;&#061; 0;<br \/>\n            \/\/\u6570\u636e\u91cf<br \/>\n            sendcnt     &lt;&#061; 0;<br \/>\n            recvcnt     &lt;&#061; 0;    <\/p>\n<p>            data_temp   &lt;&#061; 0;<br \/>\n            ack_flag    &lt;&#061; 0;<br \/>\n            \/\/\u4e09\u6001\u95e8<br \/>\n            scl_en      &lt;&#061; 0;<br \/>\n            sda_en      &lt;&#061; 0;<br \/>\n            scl_out     &lt;&#061; 0;<br \/>\n            sda_out     &lt;&#061; 0;<br \/>\n        end<br \/>\n            endcase<br \/>\n        end<br \/>\n    end  <\/p>\n<p>    \/\/\u8f93\u51fa\u4fe1\u53f7<br \/>\n    assign data_o_iic &#061; (state_c &#061;&#061; ACK4) ? data_temp : 0;<br \/>\n    assign done_r     &#061; (state_c &#061;&#061; ACK4 &amp;&amp; cnt_time &#061;&#061; MID) ? 1 : 0;<br \/>\n    assign done_w     &#061; (state_c &#061;&#061; ACK2 &amp;&amp; cnt_time &#061;&#061; MID) ? 1 : 0;<br \/>\n    assign done_iic   &#061; (state_c &#061;&#061; STOP &amp;&amp; cnt_time &#061;&#061; MID) ? 1 : 0;<br \/>\n    assign wrong      &#061; (state_c &#061;&#061; STOP &amp;&amp; cnt_time &#061;&#061; MID &amp;&amp; (sendcnt!&#061;sendnum || recvcnt!&#061;recvnum ));<\/p>\n<p>endmodule<\/p>\n<ul>\n<li>\u4eff\u771f\u4ee3\u7801\u548c\u6ce2\u5f62<\/li>\n<\/ul>\n<p>module tb ();<\/p>\n<p>    reg            clk          ;<br \/>\n    reg            rst_n        ;<br \/>\n    reg            start_iic    ;<br \/>\n    reg    [7:0]   data_i_iic   ;<\/p>\n<p>    wire   [7:0]   data_o_iic   ;<br \/>\n    wire           done_w       ;<br \/>\n    wire           done_r       ;<br \/>\n    wire           done_iic     ;<br \/>\n    wire           wrong        ;<br \/>\n    tri0           scl          ;<br \/>\n    tri0           sda          ;  <\/p>\n<p>    initial begin<br \/>\n        clk       &lt;&#061; 0;<br \/>\n        rst_n     &lt;&#061; 0;<br \/>\n        start_iic &lt;&#061; 0;<br \/>\n        #20<br \/>\n        rst_n     &lt;&#061; 1;<br \/>\n        #100<br \/>\n        start_iic &lt;&#061; 1;<br \/>\n        #100<br \/>\n        start_iic &lt;&#061; 0;<br \/>\n    end<\/p>\n<p>    always #10 clk &#061; ~clk;<\/p>\n<p>    always &#064;(posedge clk or negedge rst_n) begin<br \/>\n        if (rst_n &#061;&#061; 0) begin<br \/>\n            data_i_iic &lt;&#061; 8&#039;h22;<br \/>\n        end<br \/>\n        else if(done_w)begin<br \/>\n            data_i_iic &lt;&#061;data_i_iic &#043; 1;<br \/>\n        end<br \/>\n    end<\/p>\n<p>top top_inst(<br \/>\n    .clk        (clk       ),<br \/>\n    .rst_n      (rst_n     ),<br \/>\n    .start_iic  (start_iic ),<br \/>\n    .worr       (0         ),<br \/>\n    .sendnum    (4         ),<br \/>\n    .recvnum    (3         ),<br \/>\n    .data_i_iic (data_i_iic),<br \/>\n    .data_o_iic (data_o_iic),<br \/>\n    .done_w     (done_w    ),<br \/>\n    .done_r     (done_r    ),<br \/>\n    .done_iic   (done_iic  ),<br \/>\n    .wrong      (wrong     ),<br \/>\n    .scl        (scl       ),<br \/>\n    .sda        (sda       )<br \/>\n);<\/p>\n<p>endmodule<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094135-6aa51e4feb43b.png\" alt=\"\u5728\u8fd9\u91cc\u63d2\u5165\u56fe\u7247\u63cf\u8ff0\" \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf \u6587\u7ae0\u76ee\u5f55IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf\u4e00\u3001IIC \u603b\u7ebf\u6982\u8ff0\u4e8c\u3001\u7269\u7406\u5c42\u4e09\u3001\u8bbe\u5907\u5bfb\u5740&#xff1a;71 \u5b57\u8282\u683c\u5f0f\u56db\u3001\u8bbe\u5907\u89d2\u8272\u4e0e\u529f\u80fd\u4e3b\u8bbe\u5907\u4ece\u8bbe\u5907\u4e94\u3001\u901a\u4fe1\u901f\u7387\u516d\u3001\u534f\u8bae\u5c426.1 \u8d77\u59cb\u4fe1\u53f7 &amp; \u505c\u6b62\u4fe1\u53f76.2 \u6570\u636e\u4f4d\u4f20\u8f93\u89c4\u52196.3 ACK \u5e94\u7b54\u4fe1\u53f76.4 \u4e09\u79cd\u5de5\u4f5c\u6a21\u5f0f6.5 \u591a\u4e3b\u673a\u4e0e\u603b\u7ebf\u4ef2\u88c1\u4e03\u3001IIC \u6838\u5fc3\u5c0f\u7ed3\u516b\u3001Verilog \u5b9e\u73b0 IIC \u534f\u8bae\u6458\u8981&#xff1a;<\/p>\n","protected":false},"author":2,"featured_media":104535,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[941],"topic":[],"class_list":["post-104546","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-server","tag-fpga"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.3 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.wsisp.com\/helps\/104546.html\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\" \/>\n<meta property=\"og:description\" content=\"IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf \u6587\u7ae0\u76ee\u5f55IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf\u4e00\u3001IIC \u603b\u7ebf\u6982\u8ff0\u4e8c\u3001\u7269\u7406\u5c42\u4e09\u3001\u8bbe\u5907\u5bfb\u5740&#xff1a;71 \u5b57\u8282\u683c\u5f0f\u56db\u3001\u8bbe\u5907\u89d2\u8272\u4e0e\u529f\u80fd\u4e3b\u8bbe\u5907\u4ece\u8bbe\u5907\u4e94\u3001\u901a\u4fe1\u901f\u7387\u516d\u3001\u534f\u8bae\u5c426.1 \u8d77\u59cb\u4fe1\u53f7 &amp; \u505c\u6b62\u4fe1\u53f76.2 \u6570\u636e\u4f4d\u4f20\u8f93\u89c4\u52196.3 ACK \u5e94\u7b54\u4fe1\u53f76.4 \u4e09\u79cd\u5de5\u4f5c\u6a21\u5f0f6.5 \u591a\u4e3b\u673a\u4e0e\u603b\u7ebf\u4ef2\u88c1\u4e03\u3001IIC \u6838\u5fc3\u5c0f\u7ed3\u516b\u3001Verilog \u5b9e\u73b0 IIC \u534f\u8bae\u6458\u8981&#xff1a;\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.wsisp.com\/helps\/104546.html\" \/>\n<meta property=\"og:site_name\" content=\"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\" \/>\n<meta property=\"article:published_time\" content=\"2026-09-12T09:41:38+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094130-6aa51e4a2f8dc.jpg\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"11 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/104546.html\",\"url\":\"https:\/\/www.wsisp.com\/helps\/104546.html\",\"name\":\"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\",\"isPartOf\":{\"@id\":\"https:\/\/www.wsisp.com\/helps\/#website\"},\"datePublished\":\"2026-09-12T09:41:38+00:00\",\"dateModified\":\"2026-09-12T09:41:38+00:00\",\"author\":{\"@id\":\"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41\"},\"breadcrumb\":{\"@id\":\"https:\/\/www.wsisp.com\/helps\/104546.html#breadcrumb\"},\"inLanguage\":\"zh-Hans\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.wsisp.com\/helps\/104546.html\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/104546.html#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"\u9996\u9875\",\"item\":\"https:\/\/www.wsisp.com\/helps\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/#website\",\"url\":\"https:\/\/www.wsisp.com\/helps\/\",\"name\":\"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\",\"description\":\"\u9999\u6e2f\u670d\u52a1\u5668_\u9999\u6e2f\u4e91\u670d\u52a1\u5668\u8d44\u8baf_\u670d\u52a1\u5668\u5e2e\u52a9\u6587\u6863_\u670d\u52a1\u5668\u6559\u7a0b\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.wsisp.com\/helps\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"zh-Hans\"},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41\",\"name\":\"admin\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"zh-Hans\",\"@id\":\"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery\",\"contentUrl\":\"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery\",\"caption\":\"admin\"},\"sameAs\":[\"http:\/\/wp.wsisp.com\"],\"url\":\"https:\/\/www.wsisp.com\/helps\/author\/admin\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.wsisp.com\/helps\/104546.html","og_locale":"zh_CN","og_type":"article","og_title":"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","og_description":"IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf \u6587\u7ae0\u76ee\u5f55IIC (Inter\u2011Integrated Circuit) \u96c6\u6210\u7535\u8def\u603b\u7ebf\u4e00\u3001IIC \u603b\u7ebf\u6982\u8ff0\u4e8c\u3001\u7269\u7406\u5c42\u4e09\u3001\u8bbe\u5907\u5bfb\u5740&#xff1a;71 \u5b57\u8282\u683c\u5f0f\u56db\u3001\u8bbe\u5907\u89d2\u8272\u4e0e\u529f\u80fd\u4e3b\u8bbe\u5907\u4ece\u8bbe\u5907\u4e94\u3001\u901a\u4fe1\u901f\u7387\u516d\u3001\u534f\u8bae\u5c426.1 \u8d77\u59cb\u4fe1\u53f7 &amp; \u505c\u6b62\u4fe1\u53f76.2 \u6570\u636e\u4f4d\u4f20\u8f93\u89c4\u52196.3 ACK \u5e94\u7b54\u4fe1\u53f76.4 \u4e09\u79cd\u5de5\u4f5c\u6a21\u5f0f6.5 \u591a\u4e3b\u673a\u4e0e\u603b\u7ebf\u4ef2\u88c1\u4e03\u3001IIC \u6838\u5fc3\u5c0f\u7ed3\u516b\u3001Verilog \u5b9e\u73b0 IIC \u534f\u8bae\u6458\u8981&#xff1a;","og_url":"https:\/\/www.wsisp.com\/helps\/104546.html","og_site_name":"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","article_published_time":"2026-09-12T09:41:38+00:00","og_image":[{"url":"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912094130-6aa51e4a2f8dc.jpg"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"\u4f5c\u8005":"admin","\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4":"11 \u5206"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/www.wsisp.com\/helps\/104546.html","url":"https:\/\/www.wsisp.com\/helps\/104546.html","name":"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","isPartOf":{"@id":"https:\/\/www.wsisp.com\/helps\/#website"},"datePublished":"2026-09-12T09:41:38+00:00","dateModified":"2026-09-12T09:41:38+00:00","author":{"@id":"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41"},"breadcrumb":{"@id":"https:\/\/www.wsisp.com\/helps\/104546.html#breadcrumb"},"inLanguage":"zh-Hans","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.wsisp.com\/helps\/104546.html"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.wsisp.com\/helps\/104546.html#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"\u9996\u9875","item":"https:\/\/www.wsisp.com\/helps"},{"@type":"ListItem","position":2,"name":"verilog\u5b9e\u73b0IIC\uff08\u96c6\u6210\u7535\u8def\u603b\u7ebf\uff09\u534f\u8bae"}]},{"@type":"WebSite","@id":"https:\/\/www.wsisp.com\/helps\/#website","url":"https:\/\/www.wsisp.com\/helps\/","name":"\u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3","description":"\u9999\u6e2f\u670d\u52a1\u5668_\u9999\u6e2f\u4e91\u670d\u52a1\u5668\u8d44\u8baf_\u670d\u52a1\u5668\u5e2e\u52a9\u6587\u6863_\u670d\u52a1\u5668\u6559\u7a0b","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.wsisp.com\/helps\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"zh-Hans"},{"@type":"Person","@id":"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/358e386c577a3ab51c4493330a20ad41","name":"admin","image":{"@type":"ImageObject","inLanguage":"zh-Hans","@id":"https:\/\/www.wsisp.com\/helps\/#\/schema\/person\/image\/","url":"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery","contentUrl":"https:\/\/gravatar.wp-china-yes.net\/avatar\/?s=96&d=mystery","caption":"admin"},"sameAs":["http:\/\/wp.wsisp.com"],"url":"https:\/\/www.wsisp.com\/helps\/author\/admin"}]}},"_links":{"self":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/posts\/104546","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/comments?post=104546"}],"version-history":[{"count":0,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/posts\/104546\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/media\/104535"}],"wp:attachment":[{"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/media?parent=104546"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/categories?post=104546"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/tags?post=104546"},{"taxonomy":"topic","embeddable":true,"href":"https:\/\/www.wsisp.com\/helps\/wp-json\/wp\/v2\/topic?post=104546"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}