{"id":104287,"date":"2026-09-12T11:25:13","date_gmt":"2026-09-12T03:25:13","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/104287.html"},"modified":"2026-09-12T11:25:13","modified_gmt":"2026-09-12T03:25:13","slug":"dds%e4%bf%a1%e5%8f%b7%e5%8f%91%e7%94%9f%e5%99%a8","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/104287.html","title":{"rendered":"DDS\u4fe1\u53f7\u53d1\u751f\u5668"},"content":{"rendered":"<\/p>\n<h4>\u6587\u7ae0\u76ee\u5f55<\/h4>\n<ul>\n<li>\u4e00&#xff0c;\u9879\u76ee\u4ecb\u7ecd<\/li>\n<li>\n<ul>\n<li>1.\u4ecb\u7ecd<\/li>\n<\/ul>\n<\/li>\n<li>\u4e8c&#xff0c;\u9879\u76ee\u539f\u7406<\/li>\n<li>\n<ul>\n<li>2.1DDS\u539f\u7406<\/li>\n<\/ul>\n<\/li>\n<li>\u4e09&#xff0c;\u9879\u76ee\u5b9e\u73b0<\/li>\n<li>\n<ul>\n<li>3.1\u9879\u76ee\u8bbe\u8ba1<\/li>\n<li>3.2\u4ee3\u7801\u89e3\u6790<\/li>\n<\/ul>\n<\/li>\n<li>\u56db&#xff0c;\u9879\u76ee\u4ee3\u7801<\/li>\n<li>\n<ul>\n<li>4.1order_analysis<\/li>\n<li>4.2ctrl_rom1<\/li>\n<li>4.3rom_ctrl<\/li>\n<li>4.4ctrl_dac<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h2>\u4e00&#xff0c;\u9879\u76ee\u4ecb\u7ecd<\/h2>\n<h3>1.\u4ecb\u7ecd<\/h3>\n<p>\u901a\u8fc7Verilog\u8bed\u8a00\u5728FPGA\u5f00\u53d1\u677f\u4e0a\u5b9e\u73b0\u6b63\u5f26\u6ce2&#xff0c;\u4e09\u89d2\u6ce2&#xff0c;\u65b9\u6ce2&#xff0c;\u952f\u9f7f\u6ce2\u4fe1\u53f7\u7684\u4ea7\u751f&#xff0c;\u5e76\u4e14\u53ef\u4ee5\u901a\u8fc7\u8c03\u9891&#xff0c;\u8c03\u5e45&#xff0c;\u8c03\u76f8\u6765\u63a7\u5236\u4fe1\u53f7\u3002<\/p>\n<h2>\u4e8c&#xff0c;\u9879\u76ee\u539f\u7406<\/h2>\n<h3>2.1DDS\u539f\u7406<\/h3>\n<p>DDS \u662f\u76f4\u63a5\u6570\u5b57\u5f0f\u9891\u7387\u5408\u6210\u5668&#xff08;Direct Digital Synthesizer&#xff09;\u7684\u82f1\u6587\u7f29\u5199&#xff0c;\u662f\u4e00\u9879\u5173\u952e\u7684\u6570\u5b57\u5316\u6280\u672f\u3002\u4e0e\u4f20\u7edf\u7684\u9891\u7387\u5408\u6210\u5668\u76f8\u6bd4&#xff0c;DDS \u5177\u6709\u4f4e\u6210\u672c\u3001\u4f4e\u529f\u8017\u3001\u9ad8\u5206\u8fa8\u7387\u548c\u5feb\u901f\u8f6c\u6362\u65f6\u95f4\u7b49\u4f18\u70b9&#xff0c;\u5e7f\u6cdb\u4f7f\u7528\u5728\u7535\u4fe1\u4e0e\u7535\u5b50\u4eea\u5668\u9886\u57df&#xff0c;\u662f\u5b9e\u73b0\u8bbe\u5907\u5168\u6570\u5b57\u5316\u7684\u4e00\u4e2a\u5173\u952e\u6280\u672f\u3002\u4f5c\u4e3a\u8bbe\u8ba1\u4eba\u5458&#xff0c;\u6211\u4eec\u4e60\u60ef\u79f0\u5b83\u4e3a\u4fe1\u53f7\u53d1\u751f\u5668&#xff0c;\u4e00\u822c\u7528\u5b83\u4ea7\u751f\u6b63\u5f26\u3001\u952f\u9f7f\u3001\u65b9\u6ce2\u7b49\u4e0d\u540c\u6ce2\u5f62\u6216\u4e0d\u540c\u9891\u7387\u7684\u4fe1\u53f7\u6ce2\u5f62&#xff0c;\u5728\u7535\u5b50\u8bbe\u8ba1\u548c\u6d4b\u8bd5\u4e2d\u5f97\u5230\u5e7f\u6cdb\u5e94\u7528\u3002<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912032511-6aa4c6176049b.png\" alt=\"image.png\" \/><\/p>\n<h2>\u4e09&#xff0c;\u9879\u76ee\u5b9e\u73b0<\/h2>\n<h3>3.1\u9879\u76ee\u8bbe\u8ba1<\/h3>\n<p><img decoding=\"async\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2026\/09\/20260912032511-6aa4c617d899d.png\" alt=\"image.png\" \/> \u4f7f\u7528Uart\u534f\u8bae\u6765\u8f93\u5165\u63a7\u5236\u4fe1\u53f7&#xff0c;\u7136\u540e\u6839\u636erom\u6765\u5b58\u50a8\u56db\u79cd\u6ce2\u5f62\u8f93\u51fa&#xff0c;\u8f93\u51fa\u7684\u6570\u5b57\u4fe1\u53f7\u7ecf\u8fc7DAC\u8f6c\u5316\u53d8\u4e3a\u6a21\u62df\u4fe1\u53f7&#xff0c;\u6700\u540e\u901a\u8fc7\u793a\u6ce2\u5668\u8f93\u51fa\u5c55\u793a<\/p>\n<h3>3.2\u4ee3\u7801\u89e3\u6790<\/h3>\n<p>\u4e00\u4e2arx\u6765\u8f93\u5165\u63a7\u5236\u4fe1\u53f7&#xff0c;order_analysis\u63a7\u5236\u547d\u4ee4\u89e3\u6790\u6a21\u5757&#xff0c;ctrl_rom\u6ce2\u5f62\u63a7\u5236\u6a21\u5757\u6765\u63a7\u5236\u6ce2\u5f62\u7684\u79cd\u7c7b&#xff0c;\u76f8\u4f4d&#xff0c;\u9891\u7387&#xff0c;\u5e45\u5ea6&#xff0c;spi_m\u6765\u4f20\u8f93dac\u7684\u63a7\u5236\u4fe1\u53f7&#xff0c;ctrl_dac\u6765\u63a7\u5236dac\u8f6c\u5316<\/p>\n<h2>\u56db&#xff0c;\u9879\u76ee\u4ee3\u7801<\/h2>\n<h3>4.1order_analysis<\/h3>\n<p>module order_analysis (<br \/>\ninput        clk     ,<br \/>\ninput        rst_n   ,<br \/>\ninput  [7:0] data_rx ,<br \/>\ninput        done_rx ,<br \/>\noutput [7:0] wave    ,<br \/>\noutput [7:0] phas    ,<br \/>\noutput [7:0] freq    ,<br \/>\noutput [7:0] ampl    ,<br \/>\noutput       done_cmd<br \/>\n);<\/p>\n<p>localparam  IDLE&#061;1,<br \/>\n            WAVA&#061;2,<br \/>\n            PHAS&#061;3,<br \/>\n            FREQ&#061;4,<br \/>\n            AMPL&#061;5,<br \/>\n            STOP&#061;6;<\/p>\n<p>reg [7:0] wave_reg;<br \/>\nreg [7:0] phas_reg;<br \/>\nreg [7:0] freq_reg;<br \/>\nreg [7:0] ampl_reg;<br \/>\nreg [3:0] c_state,n_state;<\/p>\n<p>always &#064;(posedge clk or negedge rst_n ) begin<br \/>\n    if(!rst_n)<br \/>\n    c_state&lt;&#061;IDLE;<br \/>\n    else<br \/>\n    c_state&lt;&#061;n_state;<br \/>\nend<\/p>\n<p>always &#064;(*) begin<br \/>\n    if(!rst_n)<br \/>\n    n_state&#061;IDLE;<br \/>\n    else<br \/>\n    case (c_state)<br \/>\n         IDLE:begin<br \/>\n            if(done_rx&amp;&amp;data_rx&#061;&#061;8&#039;hfe)<br \/>\n            n_state&#061;WAVA;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         WAVA:begin<br \/>\n            if(done_rx)<br \/>\n            n_state&#061;PHAS;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         PHAS:begin<br \/>\n            if(done_rx)<br \/>\n            n_state&#061;FREQ;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         FREQ:begin<br \/>\n            if(done_rx)<br \/>\n            n_state&#061;AMPL;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         AMPL:begin<br \/>\n            if(done_rx)<br \/>\n            n_state&#061;STOP;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         STOP:n_state&#061;IDLE;<br \/>\n        default:n_state&#061;IDLE;<br \/>\n    endcase<br \/>\nend<\/p>\n<p>always &#064;(posedge clk or negedge rst_n) begin<br \/>\n    if(!rst_n)begin<br \/>\n        wave_reg&lt;&#061;0;<br \/>\n        phas_reg&lt;&#061;0;<br \/>\n        freq_reg&lt;&#061;0;<br \/>\n        ampl_reg&lt;&#061;0;<br \/>\n    end<br \/>\n    else<br \/>\n    case (c_state)<br \/>\n         IDLE:begin<br \/>\n        wave_reg&lt;&#061;wave_reg;<br \/>\n        phas_reg&lt;&#061;phas_reg;<br \/>\n        freq_reg&lt;&#061;freq_reg;<br \/>\n        ampl_reg&lt;&#061;ampl_reg;<br \/>\n    end<br \/>\n         WAVA:begin<br \/>\n        if(done_rx)<br \/>\n        wave_reg&lt;&#061;data_rx;<br \/>\n        phas_reg&lt;&#061;0;<br \/>\n        freq_reg&lt;&#061;0;<br \/>\n        ampl_reg&lt;&#061;0;<br \/>\n    end<br \/>\n         PHAS:begin<br \/>\n        if(done_rx)<br \/>\n        phas_reg&lt;&#061;data_rx;<br \/>\n        freq_reg&lt;&#061;0;<br \/>\n        ampl_reg&lt;&#061;0;<br \/>\n    end<br \/>\n         FREQ:begin<br \/>\n        if(done_rx)<br \/>\n        freq_reg&lt;&#061;data_rx;<br \/>\n        ampl_reg&lt;&#061;0;<br \/>\n    end<br \/>\n         AMPL:begin<br \/>\n        if(done_rx&amp;&amp;done_rx!&#061;8&#039;hee)<br \/>\n        ampl_reg&lt;&#061;data_rx;<br \/>\n    end<br \/>\n         STOP:;<br \/>\n        default: begin<br \/>\n        wave_reg&lt;&#061;0;<br \/>\n        phas_reg&lt;&#061;0;<br \/>\n        freq_reg&lt;&#061;0;<br \/>\n        ampl_reg&lt;&#061;0;<br \/>\n    end<br \/>\n    endcase<br \/>\nend<\/p>\n<p>assign done_cmd&#061;(c_state&#061;&#061;STOP)?1:0;<br \/>\nassign wave &#061;wave_reg;<br \/>\nassign phas &#061;phas_reg;<br \/>\nassign freq &#061;freq_reg;<br \/>\nassign ampl &#061;ampl_reg;<br \/>\nendmodule<\/p>\n<h3>4.2ctrl_rom1<\/h3>\n<p>module ctrl_rom1 (<br \/>\ninput         clk     ,<br \/>\ninput         rst_n   ,<br \/>\ninput  [7:0]  wave    ,<br \/>\ninput  [7:0]  phas    ,<br \/>\ninput  [7:0]  freq    ,<br \/>\ninput  [7:0]  ampl    ,<br \/>\ninput         done_tx ,<br \/>\ninput         done_cmd,<br \/>\noutput        vali1    ,<br \/>\noutput [7:0]  data_tx1<br \/>\n);<\/p>\n<p>localparam IDLE&#061;1,<br \/>\n           FLAG&#061;2,<br \/>\n           WAVA&#061;3,<br \/>\n           PHAS&#061;4,<br \/>\n           FREQ&#061;5,<br \/>\n           AMPL&#061;6,<br \/>\n           DATA&#061;7,<br \/>\n           WAIT&#061;8;<br \/>\nreg [3:0] c_state,n_state;<br \/>\nreg [3:0] cnt_freq;<\/p>\n<p>reg     [7:0]  wave_reg;<br \/>\nreg     [7:0]  phas_reg;<br \/>\nreg     [7:0]  freq_reg;<br \/>\nreg     [7:0]  ampl_reg;<br \/>\nreg     [7:0]  data_reg;<br \/>\nreg    [9:0]  address;<br \/>\nwire[7:0]  q;<br \/>\nalways &#064;(posedge clk or negedge rst_n ) begin<br \/>\n    if(!rst_n)<br \/>\n    c_state&lt;&#061;IDLE;<br \/>\n    else<br \/>\n    c_state&lt;&#061;n_state;<br \/>\nend<\/p>\n<p>always &#064;(*) begin<br \/>\n    if(!rst_n)<br \/>\n    n_state&#061;IDLE;<br \/>\n    else<br \/>\n    case (c_state)<br \/>\n         IDLE:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         FLAG:begin<br \/>\n            n_state&#061;WAVA;<br \/>\n         end<br \/>\n         WAVA:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else<br \/>\n            if(wave_reg!&#061;8&#039;h01)<br \/>\n            n_state&#061;IDLE;<br \/>\n            else<br \/>\n            n_state&#061;PHAS;<br \/>\n         end<br \/>\n         PHAS:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else<br \/>\n            n_state&#061;FREQ;<br \/>\n         end<br \/>\n         FREQ:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else if((freq_reg[4]&#061;&#061;0&amp;&amp;cnt_freq&#061;&#061;freq_reg[3:0]-1)||freq_reg[4]&#061;&#061;1)<br \/>\n            n_state&#061;AMPL;<br \/>\n            else<br \/>\n            n_state&#061;c_state;<br \/>\n         end<br \/>\n         AMPL:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else<br \/>\n            n_state&#061;DATA;<br \/>\n         end<br \/>\n         DATA:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else<br \/>\n            n_state&#061;WAIT;<br \/>\n         end<br \/>\n         WAIT:begin<br \/>\n            if(done_cmd)<br \/>\n            n_state&#061;FLAG;<br \/>\n            else if(done_tx)<br \/>\n            n_state&#061;FREQ;<br \/>\n            else<br \/>\n            n_state&#061;WAIT;<br \/>\n         end<br \/>\n        default: n_state&#061;IDLE;<br \/>\n    endcase<br \/>\nend<\/p>\n<p>always &#064;(posedge clk or negedge rst_n) begin<br \/>\n    if(!rst_n)begin<br \/>\n   wave_reg&lt;&#061;0;<br \/>\n   phas_reg&lt;&#061;0;<br \/>\n   freq_reg&lt;&#061;0;<br \/>\n   ampl_reg&lt;&#061;0;<br \/>\n   data_reg&lt;&#061;0;<br \/>\n   address &lt;&#061;0;<br \/>\n   cnt_freq&lt;&#061;0;<br \/>\n    end<br \/>\n    else<br \/>\n    case (c_state)<br \/>\n         IDLE:begin<br \/>\n            wave_reg&lt;&#061;0;<br \/>\n            phas_reg&lt;&#061;0;<br \/>\n            freq_reg&lt;&#061;0;<br \/>\n            ampl_reg&lt;&#061;0;<br \/>\n            data_reg&lt;&#061;0;<br \/>\n            address &lt;&#061;0;<br \/>\n            cnt_freq&lt;&#061;0;<br \/>\n         end<br \/>\n         FLAG:begin<br \/>\n            wave_reg&lt;&#061;wave;<br \/>\n            phas_reg&lt;&#061;phas;<br \/>\n            freq_reg&lt;&#061;freq;<br \/>\n            ampl_reg&lt;&#061;ampl;<br \/>\n            data_reg&lt;&#061;0;<br \/>\n            address &lt;&#061;0;<br \/>\n            cnt_freq&lt;&#061;0;<br \/>\n         end<br \/>\n         WAVA:begin<br \/>\n            wave_reg&lt;&#061;wave_reg;<br \/>\n            phas_reg&lt;&#061;phas_reg;<br \/>\n            freq_reg&lt;&#061;freq_reg;<br \/>\n            ampl_reg&lt;&#061;ampl_reg;<br \/>\n            data_reg&lt;&#061;0;<br \/>\n            address &lt;&#061;0;<br \/>\n            cnt_freq&lt;&#061;0;<br \/>\n         end<br \/>\n         PHAS:<br \/>\n         begin<br \/>\n            data_reg&lt;&#061;0;<br \/>\n            address &lt;&#061;phas;<br \/>\n            cnt_freq&lt;&#061;0;<br \/>\n         end<br \/>\n         FREQ:begin<br \/>\n            address&lt;&#061;address&#043;1;<br \/>\n            data_reg&lt;&#061;data_reg;<br \/>\n            if(cnt_freq&#061;&#061;freq_reg[3:0]-1)<br \/>\n            cnt_freq&lt;&#061;0;<br \/>\n            else<br \/>\n            cnt_freq&lt;&#061;cnt_freq&#043;1;<br \/>\n         end<\/p>\n<p>         AMPL:begin<br \/>\n            cnt_freq&lt;&#061;cnt_freq;<br \/>\n            data_reg&lt;&#061;q\/ampl_reg;<br \/>\n            address&lt;&#061;address;<br \/>\n         end<br \/>\n         DATA:;<br \/>\n         WAIT:;<br \/>\n        default: begin<br \/>\n   wave_reg&lt;&#061;0;<br \/>\n   phas_reg&lt;&#061;0;<br \/>\n   freq_reg&lt;&#061;0;<br \/>\n   ampl_reg&lt;&#061;0;<br \/>\n   data_reg&lt;&#061;0;<br \/>\n   address &lt;&#061;0;<br \/>\n        end<br \/>\n    endcase<br \/>\nend<\/p>\n<p>rom_waverom_wave_rom1 (<br \/>\n.aclr    ( !rst_n ),<br \/>\n.address ( address ),<br \/>\n.clock   ( clk ),<br \/>\n.q       ( q )<br \/>\n);<\/p>\n<p>assign data_tx1&#061;data_reg;<br \/>\nassign vali1&#061;(c_state&#061;&#061;DATA)?1:0;<br \/>\nendmodule<\/p>\n<h3>4.3rom_ctrl<\/h3>\n<p>module rom_ctrl (<br \/>\ninput             clk     ,<br \/>\ninput             rst_n   ,<br \/>\ninput      [7:0]  wave    ,<br \/>\ninput             vali1   ,<br \/>\ninput      [7:0]  data_tx1,<br \/>\ninput             vali2   ,<br \/>\ninput      [7:0]  data_tx2,<br \/>\ninput             vali3   ,<br \/>\ninput      [7:0]  data_tx3,<br \/>\ninput             vali4   ,<br \/>\ninput      [7:0]  data_tx4,<br \/>\noutput reg        vali    ,<br \/>\noutput reg [7:0]  data_tx<br \/>\n);<\/p>\n<p>always &#064;(posedge clk or negedge rst_n ) begin<br \/>\n    if(!rst_n) begin<br \/>\n        vali   &lt;&#061; 0;<br \/>\n        data_tx&lt;&#061; 0;<br \/>\n    end<br \/>\n    else begin<br \/>\n        case (wave)<br \/>\n            8&#039;d1: begin vali &lt;&#061; vali1;   data_tx &lt;&#061; data_tx1; end<br \/>\n            8&#039;d2: begin vali &lt;&#061; vali2;   data_tx &lt;&#061; data_tx2; end<br \/>\n            8&#039;d3: begin vali &lt;&#061; vali3;   data_tx &lt;&#061; data_tx3; end<br \/>\n            8&#039;d4: begin vali &lt;&#061; vali4;   data_tx &lt;&#061; data_tx4; end<br \/>\n            default: begin vali &lt;&#061; 0; data_tx &lt;&#061; 0; end<br \/>\n        endcase<br \/>\n    end<br \/>\nend<br \/>\nendmodule<\/p>\n<h3>4.4ctrl_dac<\/h3>\n<p>module ctrl_dac(<br \/>\ninput             clk      ,<br \/>\ninput             rst_n    ,<br \/>\ninput             vali     ,<br \/>\ninput     [7:0]   data_tx  ,<br \/>\ninput             done_w   ,<br \/>\ninput             done_spi ,<br \/>\noutput            start_spi_dac,<br \/>\noutput    [7:0]   data_in_dac  ,\/\/\u8f93\u5165\u6570\u636e<br \/>\noutput    [7:0]   data_len_dac ,\/\/\u603b\u5b57\u8282\u957f\u5ea6<br \/>\noutput    [7:0]   wt_len_dac   ,\/\/\u5199\u5165\u5b57\u8282\u957f\u5ea6<br \/>\noutput            done_dac<br \/>\n);<\/p>\n<p>reg [15:0] data_reg;<br \/>\nreg        start_reg;<br \/>\nreg [7:0]  data_in_reg;<\/p>\n<p>localparam IDLE &#061; 1,<br \/>\n           START&#061; 2,<br \/>\n           DATA1&#061; 3,<br \/>\n           DATA2&#061; 4,<br \/>\n           STOP &#061; 5;<br \/>\nreg [2:0] c_state,<br \/>\n          n_state;<\/p>\n<p>assign start_spi_dac&#061;start_reg  ;<br \/>\nassign data_in_dac  &#061;data_in_reg;<br \/>\nassign data_len_dac &#061;2;<br \/>\nassign wt_len_dac   &#061;2;<br \/>\nassign done_dac&#061;(c_state&#061;&#061;STOP&amp;&amp;done_spi)?1:0;<\/p>\n<p>always &#064;(posedge clk or negedge rst_n) begin<br \/>\n    if(!rst_n)<br \/>\n    c_state&lt;&#061;IDLE;<br \/>\n    else<br \/>\n    c_state&lt;&#061;n_state;<br \/>\nend<\/p>\n<p>always &#064;(*) begin<br \/>\n    if(!rst_n)<br \/>\n    n_state&#061;IDLE;<br \/>\nelse<br \/>\ncase (c_state)<br \/>\n     IDLE :n_state&#061;START;<br \/>\n     START:begin<br \/>\n        if(vali)<br \/>\n        n_state&#061;DATA1;<br \/>\n        else<br \/>\n        n_state&#061;c_state;<br \/>\n     end<br \/>\n     DATA1:begin<br \/>\n        if(done_w)<br \/>\n        n_state&#061;DATA2;<br \/>\n        else<br \/>\n        n_state&#061;c_state;<br \/>\n     end<br \/>\n     DATA2:begin<br \/>\n        if(done_w)<br \/>\n        n_state&#061;STOP;<br \/>\n        else<br \/>\n        n_state&#061;c_state;<br \/>\n     end<br \/>\n     STOP :begin<br \/>\n        if(done_spi)<br \/>\n        n_state&#061;IDLE;<br \/>\n        else<br \/>\n        n_state&#061;c_state;<br \/>\n     end<br \/>\n    default: n_state&#061;IDLE;<br \/>\nendcase<br \/>\nend<\/p>\n<p>always &#064;(posedge clk or negedge rst_n) begin<br \/>\n    if(!rst_n)begin<br \/>\n    data_reg    &lt;&#061;0;<br \/>\n    start_reg   &lt;&#061;0;<br \/>\n    data_in_reg &lt;&#061;0;<br \/>\n    end<br \/>\nelse<br \/>\ncase (c_state)<br \/>\n    IDLE :begin<br \/>\n    data_reg    &lt;&#061;0;<br \/>\n    start_reg   &lt;&#061;0;<br \/>\n    data_in_reg &lt;&#061;0;<br \/>\n    end<br \/>\n    START:begin<br \/>\n    data_reg    &lt;&#061;{4&#039;b0,data_tx[7:0],4&#039;b0};<br \/>\n    start_reg   &lt;&#061;0;<br \/>\n    data_in_reg &lt;&#061;0;<br \/>\n    end<br \/>\n    DATA1:begin<br \/>\n    data_reg    &lt;&#061;data_reg;<br \/>\n    start_reg   &lt;&#061;1;<br \/>\n    data_in_reg &lt;&#061;data_reg[15:8];<br \/>\n    end<br \/>\n    DATA2:begin<br \/>\n    data_reg    &lt;&#061;data_reg;<br \/>\n    start_reg   &lt;&#061;0;<br \/>\n    data_in_reg &lt;&#061;data_reg[7:0];<br \/>\n    end<br \/>\n    STOP :begin<br \/>\n    data_reg    &lt;&#061;0;<br \/>\n    start_reg   &lt;&#061;0;<br \/>\n    data_in_reg &lt;&#061;0;<br \/>\n    end<br \/>\n    default:begin<br \/>\n    data_reg    &lt;&#061;0;<br \/>\n    start_reg   &lt;&#061;0;<br \/>\n    data_in_reg &lt;&#061;0;<br \/>\n    end<br \/>\nendcase<br \/>\nend<br \/>\nendmodule<\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u6587\u7ae0\u76ee\u5f55\u4e00&#xff0c;\u9879\u76ee\u4ecb\u7ecd1.\u4ecb\u7ecd\u4e8c&#xff0c;\u9879\u76ee\u539f\u74062.1DDS\u539f\u7406\u4e09&#xff0c;\u9879\u76ee\u5b9e\u73b03.1\u9879\u76ee\u8bbe\u8ba13.2\u4ee3\u7801\u89e3\u6790\u56db&#xff0c;\u9879\u76ee\u4ee3\u78014.1order_analysis4.2ctrl_rom14.3rom_ctrl4.4ctrl_dac\u4e00&#xff0c;\u9879\u76ee\u4ecb\u7ecd<br \/>\n1.\u4ecb\u7ecd<br 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