{"id":10131,"date":"2025-04-18T17:49:26","date_gmt":"2025-04-18T09:49:26","guid":{"rendered":"https:\/\/www.wsisp.com\/helps\/10131.html"},"modified":"2025-04-18T17:49:26","modified_gmt":"2025-04-18T09:49:26","slug":"%e3%80%90%e5%9b%bd%e4%ba%a7ai%e6%9c%8d%e5%8a%a1%e5%99%a8%e3%80%91%e5%85%a8%e5%9b%bd%e4%ba%a7pcie-4-0-5-0-switch-gpu%e6%89%a9%e5%b1%95%e8%a7%a3%e5%86%b3%e6%96%b9%e6%a1%88%ef%bc%8c%e6%94%af%e6%8c%81","status":"publish","type":"post","link":"https:\/\/www.wsisp.com\/helps\/10131.html","title":{"rendered":"\u3010\u56fd\u4ea7AI\u670d\u52a1\u5668\u3011\u5168\u56fd\u4ea7PCIe 4.0\/5.0 Switch GPU\u6269\u5c55\u89e3\u51b3\u65b9\u6848\uff0c\u652f\u6301\u6d77\u5149\/\u98de\u817e\/\u9f99\u82af\u7b49\u5e73\u53f0"},"content":{"rendered":"<p>\u524d\u8a00&#xff1a;<\/p>\n<p>PCIE \u534f\u8bae\u4e2d\u6709\u5f88\u5927\u7bc7\u5e45\u5728\u8bb2PCIE SWITCH\u3002\u5728\u5b9e\u9645\u7535\u8def\u5e94\u7528\u4e2d&#xff0c;\u6211\u4eec\u4e5f\u4f1a\u9047\u5230PCIE \u7aef\u53e3\u6570\u91cf\u4e0d\u591f&#xff0c;\u9700\u8981\u901a\u8fc7switch\u6765\u6269\u5c55\u7aef\u53e3\u7684\u6848\u4f8b\u3002<\/p>\n<p>\u76ee\u524d\u5e02\u9762\u4e0a\u80fd\u652f\u6301PCIe Gen5\u7684switch\u53ea\u6709Broadcom\u548cMicrochip\u4e24\u5bb6&#xff0c;\u5176\u4e2dBroadcom\u7684PEX8900\u7cfb\u5217\u8f83\u65e9\u9762\u5e02&#xff0c;\u652f\u6301PCIe Gen5\u7684\u901f\u7387&#xff0c;\u652f\u6301base switch mode&#xff08;fanout\u6269\u5c55\u6a21\u5f0f&#xff09;\u4ee5\u53casynthetic swith mode \u3002\u7b14\u8005\u7528\u8fc7broadcom\u5bb6\u7684PEX89144&#xff0c;PEX89104&#xff0c;\u5728\u4e0b\u6587\u7684\u5b9e\u9645\u5e94\u7528\u7ae0\u8282&#xff0c;\u5c06\u91cd\u70b9\u4ecb\u7ecdPEX89144\u7684\u6ce8\u610f\u4e8b\u9879&#xff1b;\u5bf9\u4e8eDiodes\u7684PI7C9X2G1616PR&#xff0c;\u548cmicrochip\u7684PM8536\u4e5f\u4f1a\u4f5c\u7b80\u8981\u5206\u6790\u3002<\/p>\n<p>\u4f5c\u4e3a\u786c\u4ef6\u5f00\u53d1&#xff0c;\u5728\u5b66\u4e60switch\u4e4b\u524d&#xff0c;\u9700\u8981\u901a\u8fc7PCIE\u534f\u8bae\u6765\u4e86\u89e3\u4e00\u4e9b\u6982\u5ff5&#xff0c;\u4e3e\u4f8b\u4e00\u6b3e\u535a\u901a\u7684PEX8724&#xff0c;DMA&#xff0c;PCIE LANE \/ PORT &#xff0c;\u4f20\u8f93\u7684\u5ef6\u8fdfLatency&#xff0c;NT\u529f\u80fd\u7b49\u8fd9\u4e9b\u53c2\u6570\u8981\u4e86\u89e3\u540e&#xff0c;\u624d\u80fd\u5bf9switch ic\u505a\u51fa\u6b63\u786e\u7684\u9009\u578b\u548c\u8bbe\u8ba1\u3002<\/p>\n<\/p>\n<p>\u56fd\u4ea7PCIe 4.0\/5.0 Switch GPU\u6269\u5c55\u89e3\u51b3\u65b9\u6848&#xff0c;\u652f\u6301\u6d77\u5149\/\u98de\u817e\/\u9f99\u82af\u7b49\u5e73\u53f0\u3002\u6df1\u5733\u4fe1\u8fc8\u63d0\u4f9b\u5168\u56fd\u4ea7\u80cc\u677f\u5b9a\u5236\u670d\u52a1\u3002<\/p>\n<h3 id=\"h_691389974_0\">\u4e00&#xff0c;PCIE\u534f\u8bae-switch\u76f8\u5173\u77e5\u8bc6\u70b9<\/h3>\n<p>\u5728\u5982\u4f55\u9009\u578bPCIe switch\u4e4b\u524d&#xff0c;\u9700\u8981\u5148\u719f\u6089\u4ee5\u4e0bPCIe Base\u534f\u8bae\u4e2d\u5173\u4e8eswitch\u7684\u77e5\u8bc6\u70b9\u8bb2\u89e3&#xff1a;<\/p>\n<h4 id=\"h_691389974_1\">1&#xff0c;\u4ec0\u4e48\u662fswitch&#xff1a;<\/h4>\n<p>\u534f\u8bae\u5b9a\u4e49 Switch: A defined System Element that connects two or more Ports to allow Packets to be routed from one Port to another. To configuration software, a Switch appears as a collection of virtual PCI-to-PCI Bridges.<\/p>\n<p>Switch\u7684\u6982\u5ff5&#xff1a;switch\u4e3a\u4e00\u7ec4\u865a\u62dfPCI-to-PCI Bridges\u7684\u96c6\u5408&#xff0c;\u8fde\u63a5\u4e24\u4e2a\u6216\u591a\u4e2aPorts\u4e14\u5141\u8bb8\u6570\u636e\u5305\u5728\u4e0d\u540cPorts\u4e4b\u95f4\u88ab\u8def\u7531\u8f6c\u53d1\u3002<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"513\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094923-680220236dc2e.jpg\" width=\"620\" \/><\/p>\n<p>\u56fe1<\/p>\n<h4 id=\"h_691389974_2\">2&#xff0c;switch\u7684\u5e94\u7528\u6a21\u5f0f&#xff1a;<\/h4>\n<ul>\n<li>Fanout\u6269\u5c55\u6a21\u5f0f<\/li>\n<li>Partition\u5206\u533a\u6a21\u5f0f<\/li>\n<li>NTB\u975e\u900f\u660e\u6865<\/li>\n<\/ul>\n<p>a,\u00a0Fanout\u6269\u5c55\u6a21\u5f0f\u6700\u4e3a\u7b80\u5355&#xff0c;Fanout\u5f62\u5f0f\u9075\u5faa\u6811\u5f62\u7ed3\u6784&#xff0c;\u56e0\u4e3a\u6811\u5f62\u7ed3\u6784\u6700\u7b80\u5355&#xff0c;\u6ca1\u6709\u73af\u8def&#xff0c;\u4e0d\u9700\u8981\u8003\u8651\u590d\u6742\u8def\u7531\u3002\u56fe2\u5373\u662ffanout\u6a21\u5f0f\u3002<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"617\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094923-6802202382a09.jpg\" width=\"1141\" \/><\/p>\n<p>\u56fe2<\/p>\n<p>b,\u00a0Partition\u5206\u533a\u6a21\u5f0f&#xff0c;\u5206\u533a\u529f\u80fd\u76f8\u5f53\u4e8e\u4ee5\u592a\u7f51Switch\u91cc\u7684Vlan&#xff0c;\u76f8\u5f53\u4e8eSAS Switch\/Expander\u91cc\u7684Zone\u3002\u4e24\u53f0\u6216\u8005\u591a\u53f0\u673a\u5668&#xff0c;\u53ef\u4ee5\u8fde\u63a5\u5230\u540c\u4e00\u7247PCI-E Switch&#xff0c;\u5728Switch\u505a\u5206\u533a\u914d\u7f6e&#xff0c;\u5c06\u67d0\u4e9bEP\u8bbe\u5907\u5206\u914d\u7ed9\u67d0\u4e2a\u670d\u52a1\u5668\u3002\u8fd9\u6837\u53ef\u4ee5\u505a\u5230\u7edf\u4e00\u7ba1\u7406&#xff0c;\u7075\u6d3b\u5206\u914d\u3002\u6bcf\u53f0\u670d\u52a1\u5668\u7684BIOS\u6216\u8005OS\u5728\u679a\u4e3ePCI-E\u603b\u7ebf\u65f6\u53ea\u4f1a\u53d1\u73b0\u5206\u914d\u7ed9\u5b83\u7684\u865a\u62df\u6865\u3001\u865a\u62dfBUS\u3001\u548cEP\u3002\u591a\u4e2a\u5206\u533a\u4e4b\u95f4\u4e92\u4e0d\u5e72\u6270\u3002\u591a\u53f0\u72ec\u7acb\u670d\u52a1\u5668\u8fde\u63a5\u5230\u540c\u4e00\u7247Switch\u4e0a&#xff0c;\u5982\u679c\u4e0d\u505aPartition&#xff0c;\u662f\u4f1a\u51fa\u73b0\u95ee\u9898\u7684&#xff0c;\u56e0\u4e3a\u4e24\u4e2aOS\u4f1a\u5206\u522b\u679a\u4e3e\u540c\u4e00\u5806PCI-E\u603b\u7ebf\u5185\u7684\u89d2\u8272&#xff0c;\u5e76\u4e3a\u5176\u5206\u914d\u8bbf\u95ee\u5730\u5740&#xff0c;\u6b64\u65f6\u4f1a\u51fa\u73b0\u51b2\u7a81\u3002<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"601\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094923-68022023b9a37.jpg\" width=\"761\" \/><\/p>\n<p>\u56fe3<\/p>\n<p>c,\u00a0NTB\u975e\u900f\u660e\u6865&#xff0c;\u5728\u6709\u4e9b\u7279\u6b8a\u573a\u666f\u4e0b&#xff0c;\u6bd4\u5982\u4f20\u7edf\u5b58\u50a8\u7cfb\u7edf\u4e2d\u7684\u591a\u4e2a\u63a7\u5236\u5668&#xff0c;\u5b83\u4eec\u4e4b\u95f4\u9700\u8981\u540c\u6b65\u5f88\u591a\u6570\u636e\u548c\u63a7\u5236\u4fe1\u606f&#xff0c;\u5e0c\u671b\u4f7f\u7528PCI-E\u94fe\u8def\u76f4\u63a5\u901a\u4fe1\u3002\u95ee\u9898\u662f&#xff0c;\u56fe\u4e2d\u7684\u4e24\u53f0\u670d\u52a1\u5668\u5e76\u4e0d\u53ef\u4ee5\u76f4\u63a5\u901a\u4fe1&#xff0c;\u56e0\u4e3a\u5fc5\u987b\u8eab\u5904\u4e24\u4e2a\u4e0d\u540c\u7684\u5206\u533a\u4e2d\u3002\u4e3a\u4e86\u6ee1\u8db3\u8fd9\u4e2a\u9700\u6c42&#xff0c;\u51fa\u73b0\u4e86NTB\u6280\u672f\u3002\u5176\u57fa\u672c\u539f\u7406\u662f\u5730\u5740\u7ffb\u8bd1&#xff0c;\u56e0\u4e3a\u4e24\u4e2a\u4e0d\u540c\u7684\u7cfb\u7edf&#xff08;\u672f\u8bedSystem Image&#xff0c;SI&#xff09;\u5404\u6709\u5404\u7684\u5730\u5740\u7a7a\u95f4&#xff0c;\u662f\u91cd\u53e0\u7684\u3002\u90a3\u4e48\u53ea\u8981\u5728PCI-E Switch\u5185\u90e8\u5c06\u5bf9\u5e94\u7684\u6570\u636e\u5305\u8fdb\u884c\u5730\u5740\u6620\u5c04\u7ffb\u8bd1&#xff0c;\u4fbf\u53ef\u4ee5\u5b9e\u73b0\u53cc\u65b9\u901a\u4fe1\u3002\u8fd9\u79cd\u5e26\u6709\u5730\u5740\u7ffb\u8bd1\u7684\u6865\u63a5\u6280\u672f\u53eb\u505aNone Transparent Bridge&#xff0c;\u975e\u900f\u660e\u6865\u3002<\/p>\n<p>\u4e0b\u56fe4 \u4e24\u4e2a\u5206\u533a\u4e2d\u7684\u4e0a\u884c\u7aef\u53e3\u914d\u7f6e\u4e3aNTB&#xff0c;\u8fd9\u6837\u4e24\u4e2aHOST\u5c31\u4e92\u76f8\u8bbf\u95ee\u5bf9\u65b9\u5206\u533a\u4e0b\u7684device\u3002<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"533\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094923-68022023cf7bb.jpg\" width=\"916\" \/><\/p>\n<p>\u56fe4<\/p>\n<p>\u4e0b\u56fe5\u89e3\u91ca\u4e86NTB\u4e0bTLP\u7684\u4f20\u64ad\u8def\u5f84&#xff1a;<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"691\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094923-68022023f0da3.jpg\" width=\"1158\" \/><\/p>\n<p>\u56fe5<\/p>\n<\/p>\n<h4 id=\"h_691389974_3\">3&#xff0c;PCIE link&#xff0c;PCIE port \u548c PCIE lane\u4e09\u8005\u7684\u533a\u522b&#xff1f;<\/h4>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"446\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-6802202439c4c.jpg\" width=\"720\" \/><\/p>\n<p>\u56fe6<\/p>\n<ul>\n<li>Link\u7684\u6982\u5ff5&#xff1a;\u4e24\u4e2aPorts\u548c\u4ed6\u4eec\u4e4b\u95f4\u6240\u8fde\u63a5Lanes\u7684\u96c6\u5408\u3002\u4e00\u4e2aLink\u662f\u5728\u4e24\u4e2a\u90e8\u4ef6\u4e4b\u95f4\u7684\u4e00\u4e2a\u53cc\u5de5\u901a\u4fe1\u901a\u9053\u3002&#xff08;\u534f\u8bae\u5b9a\u4e49&#xff1a;A Link represents a dual-simplex communications channel between two components. The fundamental PCI Express Link consists of two, low-voltage, differentially driven signal pairs: a Transmit pair and a Receive pair\u3002&#xff09;<\/li>\n<li>Lanes\u662f\u6307PCIe\u603b\u7ebf\u4e2d\u7684\u7269\u7406\u901a\u9053&#xff0c;\u6bcf\u4e2aLane\u7531\u4e00\u5bf9TX\u548cRX\u7684\u5dee\u5206\u4fe1\u53f7\u5bf9\u7ec4\u6210\u3002(\u534f\u8bae\u5b9a\u4e49&#xff1a;each Lane represents a set of differential signal pairs (one pair for transmission, one pair for reception )PCIe\u603b\u7ebf\u4e2d\u7684\u6bcf\u4e2aLane\u90fd\u662f\u4e00\u4e2a\u5355\u72ec\u7684\u3001\u5168\u53cc\u5de5\u7684\u901a\u9053&#xff0c;\u53ef\u4ee5\u652f\u6301\u4e00\u5b9a\u7684\u6570\u636e\u4f20\u8f93\u901f\u7387\u3002PCIe\u603b\u7ebf\u7684\u7248\u672c\u53f7\u4ee5\u53ca\u6bcf\u4e2a\u7248\u672c\u6240\u652f\u6301\u7684\u901f\u7387\u548cLane\u6570\u76ee\u90fd\u662f\u7531Lane\u6765\u5b9a\u4e49\u7684\u3002\u4f8b\u5982&#xff0c;PCIe 3.0 x16\u5c31\u8868\u793a\u670916\u4e2aLanes&#xff0c;\u800c\u6bcf\u4e2aLane\u7684\u6570\u636e\u4f20\u8f93\u901f\u7387\u5219\u4e3a8 GT\/s\u3002<\/li>\n<li>Port&#xff1a;\u903b\u8f91\u4e0a\u770b\u662f\u4f4d\u4e8e\u90e8\u4ef6\u548c\u4e00\u4e2aPCIE\u94fe\u8def\u4e4b\u95f4\u7684\u63a5\u53e3; \u7269\u7406\u4e0a\u770b&#xff0c;\u662f\u540c\u4e00\u4e2a\u82af\u7247\u4e0a\u7528\u6765\u5b9a\u4e49\u4e00\u4e2a\u94fe\u8def\u7684\u4e00\u7ec4\u53d1\u5c04\u5668\u548c\u63a5\u6536\u5668\u3002&#xff08;\u534f\u8bae\u5b9a\u4e49&#xff1a;logically&#xff0c;an interface between a component and a PCIE link; Physically&#xff0c;a group of Transmitters and Receivers located on the same chip that define a link\u3002&#xff09;<\/li>\n<\/ul>\n<p>\u603b\u7684\u6765\u8bf4&#xff1a;\u6bcf\u4e2aPort\u90fd\u5305\u542b\u591a\u4e2aLanes&#xff0c;\u4e0d\u540c\u7684PCIe\u603b\u7ebf\u4f20\u8f93\u901f\u7387\u548cLane\u6570\u76ee\u51b3\u5b9a\u4e86\u6bcf\u4e2a\u7aef\u53e3\u7684\u603b\u5e26\u5bbd\u3002<\/p>\n<h4 id=\"h_691389974_4\">4&#xff0c;Store-and-Forward Switching vs Cut-Through Switching<\/h4>\n<ul>\n<li>Store and Forward\u5f88\u597d\u7406\u89e3&#xff0c;\u5373Switch\u63a5\u6536\u6574\u4e2a\u62a5\u6587&#xff0c;\u7136\u540e\u518d\u5904\u7406&#xff0c;\u6ca1\u6709\u9519\u8bef&#xff0c;\u518d\u7ee7\u7eed\u5411\u76ee\u6807\u7aef\u53e3\u53d1\u9001\u3002\u6709\u9519\u8bef&#xff0c;\u5219\u6309\u7167ACK\/NAK\u534f\u8bae\u8981\u6c42\u53d1\u9001\u7aef\u91cd\u65b0\u53d1\u9001\u3002\u8fd9\u79cd\u65b9\u5f0f\u7684\u4f18\u70b9\u662f\u786e\u4fdd\u6b63\u786e\u7684\u62a5\u6587\u624d\u5411egress port\u7aef\u53e3\u53d1\u9001&#xff0c;\u4fdd\u8bc1\u4e86egress port\u7684\u5e26\u5bbd\u4e0d\u6d6a\u8d39\u3002\u7f3a\u70b9\u663e\u800c\u6613\u89c1&#xff0c;\u589e\u52a0\u4e86\u62a5\u6587\u5728Switch\u4e2d\u7684\u5ef6\u65f6\u3002<\/li>\n<li>\u4e3a\u4e86\u964d\u4f4e\u5ef6\u65f6&#xff0c;Spec\u5b9a\u4e49\u4e86\u53e6\u4e00\u79cd\u4f20\u8f93\u65b9\u5f0f&#xff0c;\u79f0\u4e4b\u4e3aCut-Through\u3002\u8ddf\u4ee5\u592a\u7f51\u4e2d\u7684Cut-Through\u6a21\u5f0f\u7c7b\u4f3c&#xff0c;Switch\u5728\u6536\u5230\u62a5\u6587\u5934\u540e&#xff0c;\u5e76\u4e0d\u9700\u8981\u7b49\u5b8c\u6574\u7684\u62a5\u6587\u63a5\u6536\u5b8c\u6210&#xff0c;\u5c31\u5f00\u59cb\u5411\u76ee\u6807\u7aef\u53e3\u8f6c\u53d1\u62a5\u6587\u3002\u8fd9\u79cd\u6a21\u5f0f\u660e\u663e\u51cf\u4f4e\u4e86\u62a5\u6587\u5728Switch\u4e2d\u7684\u5ef6\u65f6&#xff0c;\u4e0d\u8fc7\u62a5\u6587\u6709\u9519\u7684\u8bdd&#xff0c;\u4f1a\u6d6a\u8d39egress port\u7684\u5e26\u5bbd\u3002\u603b\u7684\u6765\u8bf4&#xff0c;\u94fe\u8def\u62a5\u6587\u9519\u8bef\u662f\u5c11\u6570\u60c5\u51b5&#xff0c;\u6574\u4f53\u4e0a\u770b\u8fd9\u79cd\u6a21\u5f0f\u66f4\u52a0\u4f18\u8d8a\u3002<\/li>\n<\/ul>\n<p>\u4e0b\u56fe7&#xff0c;\u662f\u535a\u901aPEX8733\u4e2d\u5173\u4e8ecut through\u6a21\u5f0f\u7684\u89e3\u91ca&#xff1a;<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"325\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-680220244d419.jpg\" width=\"1045\" \/><\/p>\n<p>\u56fe7<\/p>\n<p>\u535a\u901a\u7684PEX8733\u7684cut through latency\u6700\u5927132ns.<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"223\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-68022024703d3.jpg\" width=\"1028\" \/><\/p>\n<p>\u56fe8<\/p>\n<p>\u535a\u901a\u7684PEX89144\u7684cut through latency\u7ea6115ns.<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"150\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-680220248bb7b.png\" width=\"1200\" \/><\/p>\n<h4 id=\"h_691389974_5\">5&#xff0c;DMA (Direct Memory Access)<\/h4>\n<p>DMA\u6307\u7684\u662fDirect Memory Access&#xff0c;\u5373\u76f4\u63a5\u5185\u5b58\u8bbf\u95ee\u3002\u5728PCIe\u4ea4\u6362\u673a\u4e2d&#xff0c;DMA\u901a\u5e38\u7528\u4e8e\u63d0\u9ad8\u6570\u636e\u4f20\u8f93\u7684\u6548\u7387&#xff0c;\u907f\u514dCPU\u53c2\u4e0e\u6bcf\u4e2a\u6570\u636e\u4f20\u8f93\u64cd\u4f5c\u3002\u901a\u8fc7DMA&#xff0c;PCIe\u8bbe\u5907\u53ef\u4ee5\u76f4\u63a5\u8bbf\u95ee\u7cfb\u7edf\u5185\u5b58&#xff0c;\u4ece\u800c\u5b9e\u73b0\u9ad8\u6548\u7684\u6570\u636e\u4f20\u8f93\u3002\u5177\u4f53\u5b9e\u73b0\u65b9\u6cd5&#xff1a;CPU\u8bbe\u7f6eDMA Descriptions\u6765\u642c\u8fd0\u6570\u636e&#xff0c;\u6253\u5f00DMA\u5f15\u64ce&#xff0c;\u7136\u540e\u5728DMA engine\u642c\u8fd0\u6570\u636e\u65f6\u53ef\u4ee5\u81ea\u7531\u5730\u6267\u884c\u5176\u4ed6\u8fdb\u7a0b\u3002DMA\u5f15\u64ce\u8fd8\u53ef\u4ee5\u5728\u53ef\u7f16\u7a0b\u7684\u95f4\u9694\u5185\u4e2d\u65adCPU\u5e76\u63d0\u4f9b\u8fdb\u5ea6\u72b6\u6001\u3002<\/p>\n<p>microchip\u6700\u65b0 GEN5 PCIe switch \u6700\u591a\u80fd\u652f\u630164 DMA channels&#xff1a;<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"97\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-68022024a792e.png\" width=\"660\" \/><\/p>\n<p>\u4e0b\u9762\u4ee5PEX8733\u6765\u8bb2\u89e3DMA&#xff1a;<\/p>\n<p>\u5982\u4e0b\u56fe9&#xff0c;\u8bf4\u660e\u4e86DMA\u64cd\u4f5c\u5e8f\u5217\u4e3a\u4e00\u4e2a\u5355\u4e00\u901a\u9053\u3002\u5728\u8fd9\u4e2a\u4f8b\u5b50\u4e2d&#xff0c;DMA engine\u642c\u8fd0\u6570\u636e\u4ece\u4e3bRAM\u5230\u4e00\u4e2a\u7ec8\u7aef\u3002CPU\u53ea\u5728\u6b65\u9aa41\u30012\u548c6\u4e2d\u4f7f\u7528&#xff1b;\u5176\u4f59\u6b65\u9aa4\u7531DMA\u5f15\u64ce\u6267\u884c\u3002<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"618\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-68022024b26ce.jpg\" width=\"892\" \/><\/p>\n<p>\u56fe9<\/p>\n<h4 id=\"h_691389974_6\">6&#xff0c;Transparent and Non-Transparent Modes<\/h4>\n<p>\u5728PCIe\u4ea4\u6362\u673a\u4e2d&#xff0c;NT Ports\u6307\u7684\u662fNon-Transparent Ports&#xff08;\u975e\u900f\u660e\u7aef\u53e3&#xff09;\u3002\u8fd9\u662f\u4e00\u79cdPCIe\u4ea4\u6362\u673a\u7aef\u53e3\u7c7b\u578b&#xff0c;\u4e0eTransparent Ports&#xff08;\u900f\u660e\u7aef\u53e3&#xff09;\u76f8\u5bf9\u5e94\u3002<\/p>\n<p>\u900f\u660e\u7aef\u53e3&#xff08;Transparent Port&#xff09;\u662f\u4e00\u79cd\u5c06PCIe TLP&#xff08;Transaction Layer Packets&#xff0c;\u4e8b\u52a1\u5c42\u6570\u636e\u5305&#xff09;\u900f\u660e\u5730\u4f20\u8f93\u5230\u76ee\u6807\u7aef\u53e3\u7684\u7aef\u53e3\u7c7b\u578b\u3002\u900f\u660e\u7aef\u53e3\u5c06TLP\u4e2d\u7684\u4fe1\u606f\u76f4\u63a5\u8f6c\u53d1\u5230\u76ee\u6807\u8bbe\u5907&#xff0c;\u76ee\u6807\u8bbe\u5907\u65e0\u9700\u77e5\u9053\u4e2d\u95f4\u5b58\u5728\u7684\u900f\u660e\u7aef\u53e3\u3002<\/p>\n<p>\u76f8\u6bd4\u4e4b\u4e0b&#xff0c;\u975e\u900f\u660e\u7aef\u53e3\u5219\u4f1a\u62e6\u622aTLP\u5e76\u5728\u672c\u5730\u8fdb\u884c\u5904\u7406\u3002\u8fd9\u4e9b\u7aef\u53e3\u901a\u5e38\u88ab\u7528\u4e8e\u5b9e\u73b0\u4e00\u4e9b\u9ad8\u7ea7\u529f\u80fd&#xff0c;\u4f8b\u5982PCIe\u4ea4\u6362\u673a\u4e4b\u95f4\u7684\u4e92\u8054&#xff0c;\u4ee5\u53ca\u9519\u8bef\u7ba1\u7406\u548c\u8bca\u65ad\u3002\u5728\u5904\u7406TLP\u65f6&#xff0c;\u975e\u900f\u660e\u7aef\u53e3\u4f1a\u68c0\u67e5TLP\u7684\u5934\u90e8&#xff0c;\u5e76\u6839\u636e\u9700\u8981\u8fdb\u884c\u4fee\u6539\u6216\u5206\u6790\u3002<\/p>\n<p>NT Ports\u901a\u5e38\u4e0eSR-IOV&#xff08;Single Root I\/O Virtualization&#xff0c;\u5355\u6839I\/O\u865a\u62df\u5316&#xff09;\u548cMR-IOV&#xff08;Multi Root I\/O Virtualization&#xff0c;\u591a\u6839I\/O\u865a\u62df\u5316&#xff09;\u76f8\u5173\u3002\u8fd9\u4e9b\u6280\u672f\u5141\u8bb8\u5c06\u7269\u7406\u8bbe\u5907\u865a\u62df\u5316\u4e3a\u591a\u4e2a\u865a\u62df\u8bbe\u5907&#xff0c;\u5e76\u5c06\u5176\u5206\u914d\u7ed9\u4e0d\u540c\u7684\u865a\u62df\u673a\u3002\u975e\u900f\u660e\u7aef\u53e3\u53ef\u4ee5\u63d0\u4f9b\u5bf9SR-IOV\u548cMR-IOV\u6240\u9700\u7684\u786c\u4ef6\u529f\u80fd\u7684\u652f\u6301\u3002<\/p>\n<h4 id=\"h_691389974_7\">7&#xff0c;AER (Advanced Error Reporting)<\/h4>\n<p>AER &#xff1a;\u9ad8\u7ea7\u9519\u8bef\u62a5\u544a&#xff0c;\u662fPCIE\u5f02\u5e38\u4fe1\u606f\u5904\u7406\u673a\u5236&#xff0c;\u7528\u4e8e\u62a5\u544aPCIe \u9519\u8bef\u4fe1\u606f\u3002<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"806\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-68022024d709e.jpg\" width=\"748\" \/><\/p>\n<p>\u56fe10<\/p>\n<h4 id=\"h_691389974_8\">8&#xff0c;PCIE lane reversal and polarity inversion\u3002<\/h4>\n<p>PCIE lane\u7ffb\u8f6c&#xff0c;\u4ee5\u53caPCIe\u5dee\u5206\u4fe1\u53f7\u6b63\u8d1f\u6781\u6027\u53cd\u8f6c\u3002\u4e0b\u56fe\u662fbroacom PEX89144\u7684PCIe\u7279\u6027\u652f\u6301&#xff1a;<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"201\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094924-68022024ef011.jpg\" width=\"620\" \/><\/p>\n<h4 id=\"h_691389974_9\">9&#xff0c;PCI power management spec<\/h4>\n<p>PCIe\u603b\u7ebf\u7684\u7535\u6e90\u7ba1\u7406\u5305\u62ec\u4e24\u65b9\u9762\u7684\u5185\u5bb9&#xff1a;<\/p>\n<ul>\n<li>\u4e00\u662f\u57fa\u4e8e\u8f6f\u4ef6\u63a7\u5236\u7684PCI-PM\u7535\u6e90\u7ba1\u7406\u673a\u5236&#xff0c;\u8fd9\u90e8\u5206\u4e0ePCI\u603b\u7ebf\u517c\u5bb9&#xff1b;<\/li>\n<li>\u4e8c\u662f\u57fa\u4e8e\u786c\u4ef6\u63a7\u5236\u7684ASPM\u7535\u6e90\u7ba1\u7406\u673a\u5236, \u4e0d\u9700\u8981Host\u7aef\u8f6f\u4ef6\u53e3\u63a7\u5236&#xff0c;PCIe\u94fe\u8def\u81ea\u4e3b\u7ba1\u7406\u3002<\/li>\n<\/ul>\n<p>\u6ce8: ASPM&#061; Active State Power Management<\/p>\n<\/p>\n<p class=\"img-center\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" height=\"333\" src=\"https:\/\/www.wsisp.com\/helps\/wp-content\/uploads\/2025\/04\/20250418094925-6802202508d4f.jpg\" width=\"998\" \/><\/p>\n<h4 id=\"h_691389974_10\">10&#xff0c;cut through latency<\/h4>\n<p>11&#xff0c;base mode&#xff1a;PEX 8733 acts as a standard PCI Express switch, supporting one Host hierarchy (equivalent to Conventional PCI mode).<\/p>\n<h4 id=\"h_691389974_11\">11, \u4ec0\u4e48\u662fP2P&#xff1f;<\/h4>\n<p>P2P&#xff1a;peer to peer communication&#xff1b;P2P\u662fPCIe\u8bbe\u5907\u4e4b\u95f4\u76f4\u63a5\u4f20\u8f93\u6570\u636e&#xff0c;\u800c\u4e0d\u9700\u8981\u4f7f\u7528HOST RAM\u4f5c\u4e3a\u4e34\u65f6\u5b58\u50a8\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u6587\u7ae0\u6d4f\u89c8\u9605\u8bfb1.9k\u6b21\uff0c\u70b9\u8d5e16\u6b21\uff0c\u6536\u85cf19\u6b21\u3002\u534f\u8bae\u5b9a\u4e49 Switch: A defined System Element that connects two or more Ports to allow Packets to be routed from one Port to another. To configuration software, a Switch appears as a collection of virtual PCI-to-PCI Bridges._pcie switch<\/p>\n","protected":false},"author":2,"featured_media":10117,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[58,413,78,44],"topic":[],"class_list":["post-10131","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-server","tag-linux","tag-pcie-switch-ai","tag-78","tag-44"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.3 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>\u3010\u56fd\u4ea7AI\u670d\u52a1\u5668\u3011\u5168\u56fd\u4ea7PCIe 4.0\/5.0 Switch GPU\u6269\u5c55\u89e3\u51b3\u65b9\u6848\uff0c\u652f\u6301\u6d77\u5149\/\u98de\u817e\/\u9f99\u82af\u7b49\u5e73\u53f0 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.wsisp.com\/helps\/10131.html\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"\u3010\u56fd\u4ea7AI\u670d\u52a1\u5668\u3011\u5168\u56fd\u4ea7PCIe 4.0\/5.0 Switch GPU\u6269\u5c55\u89e3\u51b3\u65b9\u6848\uff0c\u652f\u6301\u6d77\u5149\/\u98de\u817e\/\u9f99\u82af\u7b49\u5e73\u53f0 - \u7f51\u7855\u4e92\u8054\u5e2e\u52a9\u4e2d\u5fc3\" \/>\n<meta property=\"og:description\" content=\"\u6587\u7ae0\u6d4f\u89c8\u9605\u8bfb1.9k\u6b21\uff0c\u70b9\u8d5e16\u6b21\uff0c\u6536\u85cf19\u6b21\u3002\u534f\u8bae\u5b9a\u4e49 Switch: A defined System Element that connects two or more Ports to allow Packets to be routed from one Port to another. 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